abejgonzalez
5b1b4b3efe
Bump Gemmini/Hwacha/Sha3
2020-11-19 15:28:24 -08:00
abejgonzalez
a0d479f3ea
Working FIRRTL/RC/Chisel3 build | chisel-testers still broken
2020-11-16 22:55:04 -08:00
abejgonzalez
9d9813fe0a
[temp] Following RC's way to build Chisel from source or Maven [ci skip]
2020-11-16 22:24:29 -08:00
abejgonzalez
70d43210d8
[temp] Unable to build/get past chisel-testers
2020-11-15 18:18:04 -08:00
abejgonzalez
ba59d0318f
Bump barstools
2020-11-15 16:14:38 -08:00
abejgonzalez
9ea23d43a7
Merge remote-tracking branch 'origin/dev' into local-chisel34
2020-11-15 16:03:25 -08:00
Abraham Gonzalez
f54dce13d6
Merge pull request #709 from ucb-bar/small-backwards-compat
...
Bump Dromajo | Optional ignore QEMU toolchain flag
2020-11-15 14:07:31 -08:00
David Biancolin
650ba7cc63
Merge pull request #715 from ucb-bar/bus-crossing-fix
...
Fix Crossing Insertions Between Buses in Hierarchical Topology
2020-11-14 15:37:08 -08:00
Tim Snyder
1110dd702c
Bump RC, firesim and barstools for chisel3.4 updates
...
Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).
Requires: ucb-bar/barstools#92 and firesim/firesim#658
The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests. You will likely want to bump further.
2020-11-11 18:57:16 +00:00
David Biancolin
80487cc371
Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out}
2020-11-10 11:58:53 -08:00
David Biancolin
bb5d6bc9fb
Merge pull request #713 from ucb-bar/better-bus-freq-spec
...
Better Bus Frequency Specification
2020-11-09 19:18:44 -08:00
David Biancolin
230bd81e0e
[firechip] Update legacy firechip config
2020-11-09 09:26:30 -08:00
David Biancolin
098a83ce98
[CI] Add a multiclock config
2020-11-09 09:26:30 -08:00
David Biancolin
08c31014cc
Build out a more complete multiclock example configuration
2020-11-09 09:26:23 -08:00
David Biancolin
4da9e49fc1
[clocking] Fix up() invocations in freq specification fragments
2020-11-09 08:32:25 -08:00
David Biancolin
04cd6b59bd
[clocking] Add a fragment to set bus clock-sink freqs more intuitively
2020-11-09 08:32:19 -08:00
David Biancolin
a559d624df
[clocking] Drive all buses directly from the asyncClockGroup
2020-11-07 21:57:42 -08:00
Abraham Gonzalez
5c5a4b51e3
Merge pull request #710 from ucb-bar/rename-ariane
...
Rename Ariane to CVA6
2020-11-06 14:53:54 -08:00
abejgonzalez
2de5f7dd7e
[ci skip] Note that CVA6 was called Ariane in the past
2020-11-05 15:48:50 -08:00
abejgonzalez
0685812c34
Bump CVA6
2020-11-05 10:30:00 -08:00
David Biancolin
c083d5d947
Merge pull request #707 from ucb-bar/simple-pll-fixes
...
Update Reference Frequency Selection for Divider-Only Clock Generator
2020-11-05 09:59:54 -05:00
abejgonzalez
60cd999002
Bump CVA6 for Make fix
2020-11-04 21:09:24 -08:00
Abraham Gonzalez
9052b41328
Re-ignore QEMU from gnu-toolchain | Avoid piping make version in toolchain build
2020-11-04 20:59:14 -08:00
abejgonzalez
59c9163bd5
Bump CVA6 for submodule fixes
2020-11-04 18:37:26 -08:00
abejgonzalez
fc8c5e4b30
Use HTTPS for submodules
2020-11-04 18:02:49 -08:00
Abraham Gonzalez
94eceeb624
Use empty variable instead of t/f
2020-11-04 15:54:09 -08:00
abejgonzalez
a2ebbee2ac
Rename Ariane to CVA6
2020-11-04 15:42:30 -08:00
Abraham Gonzalez
5e3d1a605d
Add --ignore-qemu flag to toolchains | Prepare QEMU when it builds
2020-11-04 11:57:23 -08:00
Abraham Gonzalez
16c34e2cf3
Bump Dromajo for old glibc
2020-11-04 11:46:02 -08:00
David Biancolin
f504b7a0f5
[clocking] Improve reference clock selection using a multiple-of-fastest strategy
2020-11-03 09:14:55 -08:00
David Biancolin
aa4a44925e
[clocking] Add ScalaTests for the divider-only PLL configurator
2020-11-03 09:14:55 -08:00
David Biancolin
f387634a41
[clocking] Bound SimplePllConfiguration by maximum reference freq
2020-11-03 09:14:55 -08:00
David Biancolin
946a191221
[clocking] Provide a default div for ClockDividerN sv implementation ( #706 )
2020-11-03 12:14:18 -05:00
David Biancolin
57a0bc5dfc
Fix zsh compatibility in init-submodules-no-rv-tools ( #705 )
2020-11-03 12:14:02 -05:00
Jerry Zhao
37415157d6
Merge pull request #699 from ucb-bar/lazy-iobinders
...
Support diplomatic IOBinders
2020-11-02 20:14:54 -08:00
Jerry Zhao
2d010b63f3
Merge branch 'dev' into lazy-iobinders
2020-11-02 10:02:44 -08:00
Jerry Zhao
a38596323c
Merge pull request #703 from ucb-bar/default-async-reset
...
Make the ChipTop reset pin always async
2020-10-29 10:34:22 -07:00
Jerry Zhao
7b83da054a
Clean up HarnessBinders
2020-10-28 16:18:22 -07:00
Jerry Zhao
f4d70128c0
Remove redundant ChipTop reset synchronizer
2020-10-28 15:37:31 -07:00
Jerry Zhao
93e57ef230
Make the ChipTop reset pin async always
2020-10-26 15:18:34 -07:00
Jerry Zhao
d61b31a6fe
Merge pull request #702 from ucb-bar/multirocc-gemmini
...
Add MultiRoCCGemmini config fragment
2020-10-26 10:03:26 -07:00
Fang, Zitao
4fdb9eb6b0
Merge pull request #647 from ucb-bar/verilator-makefile-fix
...
Fix Verilator Simulation run-binary-debug Error
2020-10-23 21:54:58 -07:00
Zitao Fang
abbeb2af9e
Fixed comments
2020-10-23 17:00:56 -07:00
Zitao Fang
0c4dcffb0d
Fixed lowercase p bug
2020-10-23 16:39:56 -07:00
Jerry Zhao
ac19117ec5
Add MultiRoCCGemmini config fragment
2020-10-23 15:41:49 -07:00
Jerry Zhao
7a55c55aa3
Fix no-MBUS configs
2020-10-20 01:12:28 -07:00
Jerry Zhao
e0bf907a06
Merge remote-tracking branch 'origin/dev' into lazy-iobinders
2020-10-19 13:22:01 -07:00
David Biancolin
a3c0e3a0b2
Merge pull request #690 from ucb-bar/diplomatic-clocks-mbus-crossing
...
DRAM In A Separate Domain Take 2
2020-10-19 15:15:09 -04:00
Jerry Zhao
f3d666d2b7
Clarify HarnessBinders ClassTag naming
2020-10-19 10:16:44 -07:00
Jerry Zhao
11fdf69544
Merge pull request #693 from ucb-bar/smartelf2hex-memsiz
...
Update smartelf2hex to use MemSiz instead of FileSiz
2020-10-19 09:05:50 -07:00
