wu-arch/chipyard
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86593e294898c4b9e911e20e8ad7afe8926ac030
Commit Graph

612 Commits

Author SHA1 Message Date
David Biancolin
15a30a73e9 [firechip] Memomize Clock RecordMap creation to fix supernode 2021-05-07 06:39:45 +00:00
Tim Snyder
cdca36a935 bump testchipip 2021-05-05 03:25:39 +00:00
abejgonzalez
65154b7910 Merge branch 'master' of ssh://github.com/milovanovic/chipyard into dev 2021-05-03 14:10:52 -07:00
Jiuyang Liu
4901e2d257 remove toBool to asBool. 2021-04-20 02:54:29 +00:00
Vladimir Milovanović
c046af0de2 Bump tests for scalatest version change. 2021-04-18 17:43:10 +02:00
Jerry Zhao
fd0ba3f315 Synchronize JTAG reset to JTAG.TCK. 2021-04-17 01:27:07 -07:00
Jerry Zhao
3a52b709db Bump testchipip 2021-04-01 18:20:41 -07:00
Jerry Zhao
709c6bb365 Bump testchipip 2021-03-31 09:19:29 -07:00
Jerry Zhao
c061ea0ac9 Bump testchipip | Add custom boot pin 2021-03-30 01:45:34 -07:00
Jerry Zhao
ed2bfa8249 Don't pass JTAG oe signal off-chip (#832) 2021-03-24 01:08:46 -07:00
abejgonzalez
09ef82cabf Update harnessClk/Rst naming to buildtop | Small docs cleanup 2021-03-22 13:11:12 -07:00
abejgonzalez
5ffad327db Bump testchipip 2021-03-21 15:34:01 -07:00
abejgonzalez
55263971bc Use async queue to connect serdesser + other components 2021-03-19 20:49:49 -07:00
abejgonzalez
f59a7901b0 Bump testchipip 2021-03-19 18:43:17 -07:00
abejgonzalez
87fa481cbb Fix TileResetCtrl so that tiles come out of reset after rest of uncore 2021-03-19 17:35:30 -07:00
abejgonzalez
1e42113926 Splitting up FireSim default frequencies into a separate config frag. 2021-03-19 17:33:39 -07:00
abejgonzalez
4a565088b5 Small spacing fixes 2021-03-18 20:01:45 -07:00
abejgonzalez
7b7bcf7996 Merge remote-tracking branch 'origin/dev' into offchip-axi-setup 2021-03-18 17:56:57 -07:00
abejgonzalez
5301723404 Use def instead of var Option for ref frequency 2021-03-16 19:42:24 -07:00
abejgonzalez
6476c7e7f0 Small renaming/cleanup | Use LinkedHashMaps 2021-03-15 16:54:42 -07:00
Jerry Zhao
c5e7d8a9b2 Give HarnessRAM implicit clock/reset in SerialTiedOff 2021-03-15 15:35:41 -07:00
Jerry Zhao
a013f0d561 Fix SerialTL HarnessRAM BridgeBinder 2021-03-15 15:09:29 -07:00
Jerry Zhao
edd54e776c Bump testchipip 2021-03-15 14:05:33 -07:00
Jerry Zhao
8a78565c04 Update BridgeBinders with new HarnessRAM clocking 2021-03-15 12:45:40 -07:00
Jerry Zhao
c27c9d5d18 Add option to add async queues between chip-serialIO and harness serdes 2021-03-15 02:16:18 -07:00
Jerry Zhao
f52822ff7a Merge pull request #826 from ucb-bar/tile-reset-async 
Fix TileResetCtrl to be ahead of reset synchronizers.
 2021-03-12 16:51:58 -08:00
Jerry Zhao
2260fffc9c Bump testchipip 2021-03-12 09:33:50 -08:00
Jerry Zhao
c5cb8f1329 Bump testchipip for TileResetCtrl changes 2021-03-11 18:23:36 -08:00
Abraham Gonzalez
30c9b63e7b More clarifications on harness clocks 2021-03-11 03:54:56 +00:00
Abraham Gonzalez
1ebc0f7a7e Allow the PLL to request the max freq 2021-03-11 03:30:14 +00:00
Abraham Gonzalez
e6b2a9c583 Merge pull request #821 from ucb-bar/pmp-fragment 
Add fragment to configure PMPs
 2021-03-10 19:13:47 -08:00
Kartik Prabhu
7bcfaf1b7d Fix IOCell generation for clock and reset to use IOCellKey 2021-03-10 16:54:06 -08:00
Jerry Zhao
aac77b3d74 Move TileResetCtrl before the ResetSynchronizers, and give them an async reset 2021-03-10 14:46:53 -08:00
Jerry Zhao
8f511aeaf3 Add fragment to configure PMPs 
Surprisingly there is no existing fragment to do this defined in rocketchip. Add our own here.
 2021-03-09 00:02:24 -08:00
Abraham Gonzalez
ed6d10ac2b Merge remote-tracking branch 'origin/dev' into offchip-axi-setup 2021-03-08 21:20:26 -08:00
Abraham Gonzalez
ade8457870 First doc pass (no updated imgs) [ci skip] 2021-03-09 05:11:24 +00:00
Abraham Gonzalez
e4ccfe1bb9 Renaming updates | Have FireSim clocks request frequency by default 2021-03-08 23:43:00 +00:00
Abraham Gonzalez
6ab8f8f8fc Update FireSim to support harness clocks | Small config renaming 2021-03-08 22:03:07 +00:00
Jerry Zhao
d98d6d1875 Merge pull request #808 from ucb-bar/gemmini-bump 
Bump gemmini for config changes
 2021-03-07 18:59:03 -08:00
abejgonzalez
562d8e5116 Distinguish between implicit clock/reset and reference harnessClock/Reset | Don't use parameter system to pass referenceFreq 2021-03-05 16:31:18 -08:00
abejgonzalez
2b7e359326 Cleanup config + fragments | Remove reference clk div/rst catch in harness [ci skip] 2021-03-05 12:26:10 -08:00
abejgonzalez
60a616e320 1st pass at connecting to harness PLL | Put UART adapter on harnessClock/Reset 2021-03-05 00:08:02 -08:00
abejgonzalez
d2a6dd6822 Add support for harness pll 2021-03-04 23:31:57 -08:00
abejgonzalez
3d9cd61d16 Slightly cleaner implementation 2021-03-03 22:38:44 -08:00
Abraham Gonzalez
a165763350 Merge pull request #807 from ucb-bar/tile_clk_assignment_fix 
Use "tile" instead of "core" to assign freq's in WithTileFrequency config. fragment
 2021-03-03 13:30:33 -08:00
Abraham Gonzalez
3d962180be Cleanup | Fix BlockDevice clocking issues 2021-03-03 19:44:55 +00:00
Abraham Gonzalez
c52fce79ae Fix FireChip compilation | Remove extra DefaultSerialTL in bridges 2021-03-03 07:25:49 +00:00
abejgonzalez
f850df7a9f General renaming / cleanup 2021-03-02 22:58:05 -08:00
Abraham Gonzalez
1d287bede5 Enlarge serial width | Bugfix loadmem disable | Add TracerV 2021-03-03 02:43:38 +00:00
Jerry Zhao
ffcb3156c9 Add WithMultiRoCCFromBuildRoCC to make heterogeneous accelerator configs easier 2021-03-01 00:14:15 -08:00