Commit Graph

52 Commits

Author SHA1 Message Date
Jerry Zhao
0a0dd647cd Merge pull request #1845 from ucb-bar/empty-chiptop
Add EmptyChipTop example
2024-04-22 10:14:44 -07:00
Jerry Zhao
088460f266 Update docs to reflect in-tree barstools 2024-04-19 11:38:00 -07:00
Jerry Zhao
d6d5446893 Add EmptyChipTop example 2024-04-12 09:59:19 -07:00
Jerry Zhao
0ccd032a73 Remove references to legacy softcore-based bringup 2024-01-29 07:57:36 -08:00
Jerry Zhao
9ab5067e35 Update docs on bringup sims 2023-09-20 11:44:43 -07:00
abejgonzalez
dafd7be273 Bump docs 2023-09-08 15:32:01 -07:00
abejgonzalez
284f276fbb Remove Dromajo + documentation 2023-09-08 14:28:10 -07:00
abejgonzalez
c7f1fe220d Enable precommit | Format files 2023-08-28 14:56:55 -07:00
Jerry Zhao
43789d77dd Merge pull request #1538 from JL102/patch-1
Fixed typos in CDE docs page, and added info on how config fragments in the chain can be overridden
2023-07-05 09:23:43 -07:00
Jordan Lees
487009181e Added details on how properties can be overridden 2023-06-30 17:15:24 -07:00
Jordan Lees
5237d3f115 Fixed typos so that the scala code can be pasted into a project & it runs 2023-06-30 17:01:06 -07:00
Jerry Zhao
a89b86c785 Update HarnessClocking docs 2023-05-12 15:21:27 -07:00
Jerry Zhao
eced8e63d9 Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness 2023-05-08 18:19:18 -07:00
Jerry Zhao
ad98363add Update docs/Advanced-Concepts/Harness-Clocks.rst
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2023-05-08 18:17:20 -07:00
Jerry Zhao
ac281daa78 Move TestHarness to chipyard.harness, make chipyard/harness directory 2023-05-08 08:00:56 -07:00
-T.K.-
3196d44f22 FIX: fix wording in doc
We don't require the host computer to be x86 (can be RISC-V!)
2023-05-07 22:22:37 -07:00
Jerry Zhao
d42b195b91 Add notes to docs indicating SoftCore bringup with VCU118 is legacy 2023-05-07 22:22:37 -07:00
Jerry Zhao
4a712a7de5 Add doc page on architectural checkpoints 2023-04-19 20:09:14 -07:00
Jerry Zhao
2831111134 Mention custom ChipTop in documentation' 2023-04-03 17:31:20 -07:00
Jerry Zhao
b92928090d Update doc source references 2023-02-11 13:00:57 -08:00
abejgonzalez
292cc753ce Run pre-commit on all files 2022-12-21 15:59:46 -08:00
Jerry Zhao
f634fde083 Add doc links for constellation 2022-09-27 15:28:30 -07:00
David Biancolin
8666889a53 Update docs/Advanced-Concepts/Managing-Published-Scala-Dependencies.rst
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2021-12-08 07:28:16 +00:00
David Biancolin
2904260509 Update docs/Advanced-Concepts/Managing-Published-Scala-Dependencies.rst
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2021-12-08 07:13:25 +00:00
David Biancolin
f5ac1a3f46 [docs] Explain how to modify published dependencies 2021-12-07 04:58:54 +00:00
John Fang
21a44d7596 Add torture run options to makefile (#992)
* Add torture option to chipyard makefile

* Bump spike to get the signature bug fix
2021-10-01 11:19:43 -07:00
Abraham Gonzalez
1dd2698e11 Update ref in chip communication docs. 2021-04-13 22:30:35 -07:00
abejgonzalez
09ef82cabf Update harnessClk/Rst naming to buildtop | Small docs cleanup 2021-03-22 13:11:12 -07:00
Abraham Gonzalez
0d6e971d17 Update docs/Advanced-Concepts/Chip-Communication.rst
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
2021-03-18 20:02:15 -07:00
abejgonzalez
3439266b2e Small renaming in docs 2021-03-15 16:55:13 -07:00
Abraham Gonzalez
30c9b63e7b More clarifications on harness clocks 2021-03-11 03:54:56 +00:00
Abraham Gonzalez
d204ccd9fc Clean up the chip communication docs a bit more [ci skip] 2021-03-09 23:56:32 -08:00
Abraham Gonzalez
6e1b9429bd Fix docs harness binders reference 2021-03-08 21:32:13 -08:00
Abraham Gonzalez
d5d547d27b Update doc images [ci skip] 2021-03-08 21:18:34 -08:00
Abraham Gonzalez
ade8457870 First doc pass (no updated imgs) [ci skip] 2021-03-09 05:11:24 +00:00
alonamid
7e092c655b docs label disambiguation 2021-01-08 20:11:21 -08:00
Jerry Zhao
ab21c53a42 Add documentation on HarnessBinders 2020-09-04 23:51:36 -07:00
Jerry Zhao
3258fd8db8 Remove JTAG from firesim comfigs due to @(posedge ~clk) issue 2020-09-03 23:53:51 -07:00
Jerry Zhao
4b30462320 Change default IO set to JTAG+Serial, instead of JTAG+DMI 2020-09-02 20:19:27 -07:00
abejgonzalez
33e83e0644 [dromajo] separate documentation | move header file gen to tcip 2020-05-16 13:08:57 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480)
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
2020-04-01 14:03:56 -07:00
Howard Mao
ffb9c81ce2 fix literalincludes and other path references in documentation 2020-03-16 12:06:59 -07:00
Abraham Gonzalez
01238c8b7a Rename Config Mixins to Fragments (#451)
* [docs] rename config mixins -> fragments [ci skip]

* [docs] cleanup naming | link similar sections [ci skip]

* [boom] bump for mixin rename [ci skip]

* [docs] cleanup capitalization [ci skip]

* [docs] consistent config fragment naming [ci skip]

* [boom] bump boom for documentation changes [ci skip]

* [docs] update source comments [ci skip]

* [docs] fix last config fragment name [ci skip]

Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>

Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
2020-02-27 09:31:08 -08:00
Jerry Zhao
708a5fb9a6 Address generator unification PR reviews 2020-02-23 22:53:14 -08:00
Jerry Zhao
c12819eb52 Update docs 2020-02-13 12:33:28 -08:00
Abraham Gonzalez
1859054f73 [docs] update documentation [ci skip] (#393) 2020-01-23 13:36:21 -08:00
Jerry Zhao
ac5235e5ed Revamp the config system for Top/Harness (#347)
* Refactor how Configs parameterize the Top and TestHarnesses

* Bump sha3, testchipip, icenet, firesim
2020-01-21 20:44:54 -08:00
alonamid
a07a1d2b8a some docs cleanup 2019-10-04 00:16:25 -07:00
Jerry Zhao
48c8e0f571 [docs][ci skip] Address comments 2019-09-28 22:09:18 -07:00