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Author SHA1 Message Date
abejgonzalez
f45369365b rename build.sh and move to scripts 2019-04-15 10:17:42 -07:00
abejgonzalez
d80acd8cf8 added boom and torture | added csmith 2019-04-15 10:17:42 -07:00
abejgonzalez
8b899c519d rename makefiles | move verilog rule to common.mk 2019-04-15 10:17:41 -07:00
abejgonzalez
eb44ae13d4 makefile changes/split | add scripts 2019-04-15 10:17:41 -07:00
alonamid
31e30b2ec7 change dir structure 2019-04-15 10:17:41 -07:00
alonamid
419d41239f Merge pull request #59 from ucb-bar/rebar-srams-fix 
Bump barstools and re-add infer-rw for better SRAM mapping
 2019-03-18 09:30:01 -07:00
Colin Schmidt
ffee1f1e98 Bump barstools and re-add infer-rw for better SRAM mapping 2019-03-18 07:31:27 -07:00
alonamid
319d2fedf7 more docs 2019-03-16 00:15:02 -07:00
Abraham Gonzalez
87f9c14dcc Merge pull request #54 from ucb-bar/misc-changes 
Makefile + Ctags
 2019-03-15 18:47:00 -07:00
abejgonzalez
e33f2fcedf find now follows symlinks 2019-03-12 15:39:19 -07:00
abejgonzalez
c364869563 default to .gitignoring all files in verisim/vsim | read verilator.mk 2019-03-12 14:39:15 -07:00
abejgonzalez
4fd1bfbd56 delete .ctags (have the user put this in their home) 2019-03-12 14:39:15 -07:00
abejgonzalez
2c246af110 rename makefiles | move verilog rule to common.mk 2019-03-12 14:39:15 -07:00
abejgonzalez
82273107c1 makefile changes/split | add scripts 2019-03-12 14:39:15 -07:00
alonamid
49ab106b9e docs placeholder 2019-03-12 14:30:38 -07:00
alonamid
6ccb3defc1 add toolchains 2019-03-12 14:30:38 -07:00
alonamid
4d62a2b215 docs placeholder 2019-03-12 14:30:38 -07:00
alonamid
2e7791a57d add chisel and firrtl submodules 2019-03-12 14:30:38 -07:00
alonamid
2def0dfea7 change dir structure 2019-03-12 14:30:38 -07:00
Colin Schmidt
17c38a502a Help people who want to run tests (#50) 
* Help people who want to run tests

* Include generated makefrags for simulation
 2019-03-11 11:26:27 -07:00
Paul Rigge
0b7f7b43bc Merge pull request #52 from ucb-bar/fixAXI 
Fix AXI4 example.
 2019-03-07 20:59:05 -08:00
Paul Rigge
61d1798888 Fix AXI4 example. 
I accidentally stumbled into a working AXI4 configuration by multiplying
pbus.beatBytes by 8, but it was fragile. This is the "right way" to add
an AXI4 peripheral.
 2019-03-07 20:58:23 -08:00
Paul Rigge
bf23d7aa6c Fix VCS build. 
VCS doesn't use the same arguments for C headers that verilator uses.
Generate the dot-f file differently for the different simulators.
 2019-03-06 23:06:24 -08:00
Paul Rigge
467fdd06e9 Bump to testchipip from a dev branch to master 2019-03-06 23:03:33 -08:00
Paul Rigge
8a522ba404 Fix some build system problems. 
1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps
 2019-03-06 22:10:31 -08:00
Paul Rigge
c7d56c09a0 Bump testchipip to master 2019-03-06 21:15:14 -08:00
Paul Rigge
ddf3159d61 Bump rocket, make possible to use published deps (#47) 
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
 2019-03-06 18:22:21 -08:00
Howard Mao
e5cbf49bb4 fix README documentation for RoCC accelerators 2019-02-27 14:10:00 -08:00
Paul Rigge
51ca3dd1b9 Merge pull request #49 from ucb-bar/fix-verisim-debug 
Debug simulator still needs all vsrcs
 2019-02-26 13:34:31 -08:00
Colin Schmidt
358e6ad49d Debug simulator still needs all vsrcs 2019-02-26 13:08:13 -08:00
Paul Rigge
cd71e3232e Merge pull request #46 from ucb-bar/updateGitmodules 
Update gitmodule url to use https
 2019-02-19 10:49:44 -08:00
Paul Rigge
0de9d396b4 Update gitmodule url to use https 
The .git suffix was dropped and git@ was used instead of https://

Update to be consistent with other submodules.
 2019-02-19 10:48:23 -08:00
John Wright
d97afcdfbc Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a 
bug using verilator, make the whitespace consistend in
Makefrag-verilator, explicitly name the verilog sources to match vsim,
and update verisim/Makefile to use the new source variable names
 2019-02-13 21:13:08 -08:00
John Wright
acd76e5410 Adding barstools to separate the top from harness and to generate the 
memories as external modules, which makes VLSI flows easier to plug in.
 2019-02-13 21:13:08 -08:00
Abraham Gonzalez
d01e38ef8a Re-add line on updated Makefrag 2019-02-03 20:17:45 -08:00
Howard Mao
fc06c909c0 fix README section on adding new submodules 2019-01-28 14:31:13 -08:00
Paul Rigge
de1ab1d8a9 Merge pull request #42 from grebe/axiPWM 
Add an AXI4 flavor of PWM peripheral.
 2019-01-25 14:52:09 -08:00
Paul Rigge
8cf06db45c Add an AXI4 flavor of PWM peripheral. 
Also closes #41.
 2019-01-24 17:13:40 -08:00
John Wright
304592f61e Fixes FIRRTL compilation bug in testchipip unit tests 2019-01-18 00:04:04 -08:00
Edward Wang
d48587b671 Update project-template for testchipip master 2018-11-02 12:05:36 -07:00
Albert Ou
cd82131748 verisim: Add verilator-harness.cc from testchipip/csrc 
This fixes #35 and matches firechip.

238afa543f
49b7982c82
 2018-10-05 09:24:35 -07:00
Albert Ou
048492e54c mk: Ensure that FIRRTL jar has updated timestamp 
SBT does not replace $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar if
compilation produces the same results.
 2018-10-02 17:43:51 -07:00
Albert Ou
220aeea4c8 Bump rocket-chip 
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
 2018-09-29 13:30:07 -07:00
Howard Mao
a3684d01dd use build.sbt instead of jar files to collect packages 2018-05-03 17:09:59 -07:00
Howard Mao
4c8c6e29f0 update rocket-chip again 2018-04-18 17:13:07 -07:00
olix86
b599514934 Update Makefrag-verilator 
Changed verilator version from 3.904 to 3.920, which fixes a bug that prevented the default example to compile correctly
 2018-04-17 17:11:30 -07:00
Howard Mao
728251a922 fix bootrom race condition 2018-04-17 16:47:48 -07:00
Howard Mao
7dc738a831 DualCoreConfig should be actually dual core 2018-04-17 16:06:44 -07:00
Howard Mao
b8f369a4bd switch to rebased testchipip branch 2018-04-17 15:56:22 -07:00
Howard Mao
7e70e3525f move bootrom to testchipip 2018-04-17 15:13:47 -07:00