Albert Magyar 28664ea8df Update section header on Verilog support in chipyard tools

2019-09-26 09:50:41 -07:00

..

_static/images

Add boom picture [ci skip]

2019-09-25 20:43:55 -07:00

Advanced-Usage

small clarifications + cleanup [skip ci]

2019-09-20 12:25:23 -07:00

Chipyard-Basics

Merge branch 'dev' into howie-docs

2019-09-25 20:26:22 -07:00

Customization

Update section header on Verilog support in chipyard tools

2019-09-26 09:50:41 -07:00

Generators

Add boom picture [ci skip]

2019-09-25 20:43:55 -07:00

Simulation

another bug fix

2019-09-25 20:33:38 -07:00

Software

Update docs/Software/FireMarshal.rst [skip ci]

2019-09-25 20:06:58 -07:00

TileLink-Diplomacy-Reference

move NodeTypes code to scala source

2019-09-16 10:25:10 -07:00

Tools

emphasize that firrtl-interpreter is deprecated | mention smaller modules [ci skip]

2019-09-25 16:38:09 -07:00

VLSI

docs reorg

2019-09-25 14:03:54 -07:00

.gitignore

[docs] gitignore build files

2019-09-08 15:45:21 -07:00

conf.py

rename to "Chipyard"

2019-06-23 22:47:23 -07:00

index.rst

Added software section. Marshal is populated (mostly points to Marshal's own readthedocs). Spike is a stub.

2019-09-25 17:22:18 -07:00

Makefile

rename to "Chipyard"

2019-06-23 22:47:23 -07:00

Quick-Start.rst

Merge remote-tracking branch 'origin/dev' into alon-docs-dev

2019-09-25 20:35:06 -07:00

requirements.txt

readthedocs fix

2019-05-14 22:16:29 -07:00