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kernels/rtl
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Lyons, Ethan Tyler b583e206a2 Fixed GPR Stage to be Generic when ASIC is defined
2019-11-22 09:20:20 -05:00
..
cache
Synthesis Compatible
2019-11-21 21:41:41 -05:00
interfaces
Add files via upload
2019-11-08 10:56:44 -05:00
modelsim
8Warp 32Threads for GTCAD synthesis
2019-11-21 23:51:11 -05:00
pipe_regs
Warps/Threads Parameterization
2019-11-21 01:15:21 -05:00
quartus
Full Evaluation Attempt 1
2019-09-11 01:39:00 -04:00
shared_memory
Warps/Threads Parameterization
2019-11-21 01:15:54 -05:00
simulate
Before evict_wb_old removal
2019-11-07 13:27:38 -05:00
.DS_Store
New RF with Evaluation
2019-09-11 01:04:23 -04:00
byte_enabled_simple_dual_port_ram.v
Synthesis Cleanup 1
2019-10-28 13:43:12 -04:00
Makefile
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
results.txt
CACHE FINALLY WORKING
2019-10-25 04:01:23 -04:00
Vortex.v
Add files via upload
2019-11-08 10:55:08 -05:00
VX_alu.v
Synthesis Compatible
2019-11-21 21:42:34 -05:00
VX_back_end.v
Improving critical path
2019-11-18 13:11:05 -05:00
VX_countones.v
Modelsim Makefile compile + simulate - DPI
2019-10-26 19:01:49 -04:00
VX_csr_handler.v
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
VX_csr_wrapper.v
Removed dependancy on
2019-10-27 22:30:32 -04:00
VX_decode.v
vecadd bug fixing + ebreak for termination
2019-11-15 14:18:45 -05:00
VX_define_synth.v
reverted to 4 thread configuration
2019-11-22 00:13:55 -05:00
VX_define.v
Started synthesis script
2019-11-22 00:32:19 -05:00
VX_dmem_controller.v
Shared Memory Implemented
2019-11-13 10:06:13 -05:00
VX_execute_unit.v
Warps/Threads Parameterization
2019-11-21 01:14:50 -05:00
VX_fetch.v
Before way logic change
2019-11-08 18:16:40 -05:00
VX_front_end.v
vecadd bug fixing + ebreak for termination
2019-11-15 14:18:45 -05:00
VX_generic_priority_encoder.v
Add files via upload
2019-11-08 10:55:08 -05:00
VX_generic_register.v
reset posedge
2019-10-21 11:34:12 -04:00
VX_generic_stack.v
Readded IPDOM stack + SPLIT/Join tested
2019-10-21 21:24:49 -04:00
VX_gpgpu_inst.v
Intrinsics: tests for TMC+Control Divergence
2019-11-01 21:53:37 -04:00
VX_gpr_stage.v
Fixed GPR Stage to be Generic when ASIC is defined
2019-11-22 09:20:20 -05:00
VX_gpr_wrapper.v
Fixed ASIC GPR warp number delay
2019-11-03 15:56:18 -05:00
VX_gpr.v
8Warp 32Threads for GTCAD synthesis
2019-11-21 23:51:11 -05:00
VX_inst_multiplex.v
Before evict_wb_old removal
2019-11-07 13:27:38 -05:00
VX_lsu_addr_gen.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00
VX_lsu.v
Warps/Threads Parameterization
2019-11-21 01:14:50 -05:00
VX_priority_encoder_w_mask.v
Add files via upload
2019-11-08 10:55:08 -05:00
VX_priority_encoder.v
Modelsim basic sim
2019-10-26 00:34:57 -04:00
VX_scheduler.v
Fixed ASIC GPR warp number delay
2019-11-03 15:56:18 -05:00
VX_warp_scheduler.v
Added a pipeline stage + fixed SM param errors
2019-11-13 12:25:28 -05:00
VX_warp.v
Modelsim Working + Simulating + dumping - Some bugs
2019-10-27 03:36:02 -04:00
VX_writeback.v
VCD for power
2019-11-21 23:25:51 -05:00