87a4bbc757
Integrate WU architecture in Radiance
2026-05-25 19:25:59 +08:00
5112f3665a
Add Blackwell tensor core implementation and tests
...
- Implement TensorCoreBlackwell.scala with BWGMMA and TCGEN05 instructions
- Update TensorDPU, RadianceTile, and VortexCore for Blackwell integration
- Add TensorCoreBlackwellExtendedTest for comprehensive testing
- Update vortex submodule with Blackwell ISA support
2026-05-06 14:51:11 +08:00
136cf70a58
Add Blackwell tensor core baseline plumbing
2026-04-25 10:15:31 +08:00
Richard Yan
4a0b1c05cd
add defines for flash config
2025-01-30 23:58:50 -08:00
Richard Yan
34c33278d2
Merge branch 'asplos-ae' of https://github.com/ucb-bar/radiance into asplos-ae
2025-01-30 22:34:43 -08:00
Richard Yan
68e4ebb471
remove tensor dpu sv
2025-01-30 22:34:38 -08:00
Hansung Kim
dd6c53bd85
Deinit cyclotron submodules
2025-01-30 21:35:39 -08:00
Richard Yan
adcb033edf
Merge branch 'asplos-ae' of https://github.com/ucb-bar/radiance into asplos-ae
2025-01-30 02:55:44 -08:00
Richard Yan
f1c9488081
set NUM_CORES and EXT_T_HOPPER based on config name
2025-01-30 02:55:40 -08:00
Hansung Kim
892485eac9
Exclude cyclotron from build
2025-01-29 00:04:15 -08:00
Hansung Kim
1cd1f6fdcd
Bump vortex
2025-01-28 22:37:46 -08:00
Hansung Kim
1ed1f4ceb0
Merge remote-tracking branch 'origin/main' into asplos-ae
2025-01-28 22:29:42 -08:00
Richard Yan
52eeed277b
correct loop count to start after receiving command
2025-01-28 17:41:00 -08:00
Richard Yan
d38f69fc5e
Merge branch 'main' of https://github.com/ucb-bar/radiance
2025-01-28 17:34:01 -08:00
Hansung Kim
9b2328c252
Update submodule URLs
2025-01-28 14:28:38 -08:00
Richard Yan
18064f0c3c
update final config and connect completion io
2025-01-28 14:24:20 -08:00
Hansung Kim
dd2721d262
Bump cyclotron
2025-01-05 00:12:11 -08:00
Hansung Kim
17001efbf3
Remove emulator_generate and merge into emulator_tick
2025-01-05 00:04:28 -08:00
Hansung Kim
049394518b
Default to debug mode for cyclotron
2025-01-04 23:03:49 -08:00
Hansung Kim
a4fa1522ab
Add D data to DPI interface
2025-01-04 23:03:25 -08:00
Hansung Kim
3af0670527
Add cyclotron-main
2024-12-05 11:51:49 +09:00
Hansung Kim
ba67263b40
Update paths
2024-12-04 18:14:37 -08:00
Hansung Kim
81595a9a9f
Bump cyclotron
2024-12-04 18:10:19 -08:00
Hansung Kim
e3080bf3ee
Update DPI for tick/generate split
2024-12-04 18:07:55 -08:00
Hansung Kim
6de4e875d4
Bump radpie
2024-11-26 15:26:39 -08:00
Hansung Kim
7cc40eedde
Add EmulatorTile
...
also split core-specific config keys from radiance.memory to radiance.core.
2024-11-26 15:23:24 -08:00
Hansung Kim
bf0527e2ad
radiance.mk: Re-enable radpie; sync csrc/ as well
2024-11-26 14:57:08 -08:00
Hansung Kim
33ff495feb
Fix doc errors and warnings for memfuzzer
2024-11-26 11:49:26 -08:00
Hansung Kim
9d70370801
Fix deprecation warnings in FuzzerTile
2024-11-25 22:33:29 -08:00
Hansung Kim
3b71276c4a
tensor: Do dot-product in fp16, only do accum in fp32
...
This is to better match Gemmini PEs doing MACs in full fp16, and only
doing accumulation in fp32.
2024-11-15 15:36:32 -08:00
Richard Yan
8c473f52e3
no tc client if not decoupled
2024-11-11 18:16:26 -08:00
Richard Yan
6488cb5c78
support no gemminis, trim debug prints
2024-11-11 16:14:02 -08:00
Hansung Kim
465322af38
Merge branch 'new-cisc'
2024-11-09 22:36:27 -08:00
Hansung Kim
8056fa4ada
Bump vortex
2024-11-09 22:35:40 -08:00
Hansung Kim
31f0905567
Add new opcode for compute and spad mvout
2024-11-09 22:35:14 -08:00
Hansung Kim
ca63c9fa74
Bump vortex
2024-11-08 21:53:21 -08:00
Richard Yan
c87858b6f4
new cisc operations
2024-11-08 20:49:49 -08:00
Richard Yan
0c6618c65d
back to non-blocking read
2024-11-07 18:20:37 -08:00
Richard Yan
d49abf97ff
amend config based on gemmini update
2024-11-03 21:07:06 -08:00
Richard Yan
9a5af03672
blocking gemmini fence and bump vortex
2024-11-01 02:45:08 -07:00
Hansung Kim
99da429cb1
tensor: Move C reg access to execute stage for higher util
...
This prevents coupling between C access in frontend & queue freeup in
backend.
2024-10-29 17:51:32 -07:00
Hansung Kim
37b8b6470b
Bump vortex with race fix
2024-10-29 14:50:26 -07:00
Hansung Kim
216cfb0589
Bump vortex
2024-10-28 23:39:58 -07:00
Hansung Kim
752effdb21
tensor: Add FIFOFixer to smem tensor port
...
TODO: get area result for this
2024-10-28 23:38:56 -07:00
Hansung Kim
daabeb03ab
tensor: Fix wrong addressGen that used bits not bytes
2024-10-28 22:27:34 -07:00
Hansung Kim
1ae1965580
tensor: Add IO and latching for smem address
2024-10-28 19:28:45 -07:00
Hansung Kim
c22fd20616
Bump vortex to 8cores
2024-10-27 19:47:52 -07:00
Hansung Kim
0e389dc362
Bump vortex
2024-10-27 18:49:42 -07:00
Hansung Kim
0ba61aabb6
tensor: Instantiate correct fake tcore module according to parameter
...
This has to align with what the verilog source actually uses.
2024-10-27 18:48:44 -07:00
Hansung Kim
13b9577723
Instantiate fake tensor modules outside of diplomacy
...
Adding them to the Diplomacy graph will cause to widen source widths
which can have area implications.
This gets rid of the need to do addResource() calls to the manually
generated Verilog files. Their module parameters should be kept the
same as what's used in the parent Verilog module, however.
2024-10-25 23:02:25 -07:00
