Hansung Kim
2364cd213e
Bump vortex
2024-08-15 13:40:09 -07:00
Hansung Kim
d8823a0416
Add back generated verilog for FP32 TensorDPU
2024-08-12 19:52:13 -07:00
Hansung Kim
7b06c1778c
Bump vortex
2024-08-07 11:30:09 -07:00
Hansung Kim
c1d95ff205
Revert rename
2024-08-07 11:29:42 -07:00
Hansung Kim
477f3955ed
Update generated SV for tensordpu
2024-08-07 11:09:57 -07:00
Hansung Kim
32c7aed263
Fix fp exception by rounding right after MulRawFN
2024-08-07 11:09:55 -07:00
Richard Yan
b7a342fcf6
bump vortex
2024-08-06 02:33:48 -07:00
Richard Yan
b7239917c0
temporary fix to rename fp units
2024-08-06 02:33:13 -07:00
Richard Yan
af60ae3332
fp16 gemmini support
2024-08-06 02:32:35 -07:00
Richard Yan
0d9c2ca6ad
rename TensorDPU.scala
2024-08-06 02:30:37 -07:00
Hansung Kim
d8674b753e
Support fp16 input, fp32 output in TensorDPU
...
TODO could see improvement towards handling raw format as much as
possible.
2024-08-01 22:01:26 -07:00
Hansung Kim
ee79fdaa05
Fix typetag for half
2024-07-31 17:17:03 -07:00
Hansung Kim
4e3ed96c94
Support fp16 operand/accum in TensorDPU
...
TODO: fp32 accum
2024-07-31 16:37:01 -07:00
Hansung Kim
33aa4e08db
Bump vortex
2024-07-26 16:27:40 -07:00
Hansung Kim
42285c7193
Instantiate StallingPipe as a separate module
...
To allow having flop/mac breakdown in area/power reports.
2024-07-25 16:29:08 -07:00
Hansung Kim
79604f51be
Fix possible CIRCT bug on SourceGenerator
...
When migrated to amd3 (possibly wiht newer CIRCT version), a new bug
shows up where storing both meta and valid into a single table doesn't
work, since writing meta writes {1'b0, meta} to the whole row of the
table overwriting the valid bit. Work this around by creating separate
tables for the meta and valid bits.
While at it, remove use of outdated NewSourceGenerator in VortexBank.
2024-07-23 15:09:03 -07:00
Hansung Kim
4566f954ee
Update doc; move code out of copypaste block
2024-07-23 15:05:09 -07:00
Hansung Kim
37fd0c6200
Bump vortex
2024-07-19 16:39:32 -07:00
Hansung Kim
21baeae758
Separate read and write counter for smem
2024-07-02 14:52:58 -07:00
Hansung Kim
7aad800a2d
Fix module imports after rocket-chip bump
2024-06-27 17:17:27 -07:00
Hansung Kim
e1342e431c
Bump radiance
2024-06-26 14:28:31 -07:00
Hansung Kim
018167480d
Add access counter to smem banks
2024-06-26 14:28:31 -07:00
Richard Yan
74cd633246
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-20 01:45:18 -07:00
Richard Yan
5eb581c7e5
different sized gemminis
2024-06-20 01:45:14 -07:00
Hansung Kim
5a79d7ff79
Add new opcodes for tensor-core DMA
2024-06-12 09:52:59 -07:00
Richard Yan
5b4d34864f
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-12 02:24:20 -07:00
Richard Yan
19852693b7
dual core gemmini, unpeg gemmini size and smem width
2024-06-12 02:17:40 -07:00
Hansung Kim
1401c4a090
Separate out core id from tile id in TileParams
...
Create a new config key to distinguish number of cores from number of
total tiles (which can be different when there are Gemmini tiles).
It is important to give contiguous IDs for Vortex cores for the
cluter-wide barrier to work.
2024-06-11 17:13:51 -07:00
Hansung Kim
7ced63bd62
Remove clbus definition from RadianceCluster
...
Should be in conjunction with the rocket-chip change that defines clbus
in the base Cluster class.
2024-06-11 16:23:54 -07:00
Hansung Kim
a0bff40a87
Set correct static tileId for core and Gemmini tiles
...
Otherwise, in multiple cluster configs, tiles can have duplicate global
tileId which results in Diplomacy connection errors for interrupt nodes
(among other things).
2024-06-11 16:17:08 -07:00
Richard Yan
a8e35b1f5a
oopsie doopsie
2024-06-09 15:35:11 -07:00
Richard Yan
17756d5f53
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-09 15:26:07 -07:00
Richard Yan
3badd75473
framebuffer, shared memory key, etc
2024-06-09 15:05:31 -07:00
Hansung Kim
ca3fd8b515
Bump vortex with doc changes
2024-06-09 13:41:18 -07:00
Hansung Kim
3254ac3741
Doc changes
2024-06-09 13:39:53 -07:00
Hansung Kim
c7e2cd2387
Bump vortex with dispatch_unit fix
2024-05-30 22:00:10 -07:00
Hansung Kim
503a3ff246
Bump vortex
2024-05-30 18:33:56 -07:00
Hansung Kim
091115bb90
Bump vortex
2024-05-29 17:06:27 -07:00
Hansung Kim
2c196bb9a0
Update generated dpu verilog for stalls
2024-05-29 16:22:24 -07:00
Hansung Kim
17886dc050
Implement proper stalls for dpu
2024-05-29 16:21:12 -07:00
Hansung Kim
8e79e620cb
Bump vortex
2024-05-29 13:35:43 -07:00
Hansung Kim
d34c5836a8
Add chisel-generated verilog for dpu
2024-05-29 13:33:23 -07:00
Hansung Kim
4a43d0126d
Make dpu 2-stage
...
For debugging, need to revert.
2024-05-29 13:31:38 -07:00
Hansung Kim
40b27c9600
Fix test for DPU
2024-05-28 21:18:51 -07:00
Hansung Kim
793db0e29d
Add stall IO to dpu
2024-05-28 21:18:19 -07:00
Hansung Kim
907150e51c
Add accumulation to dpu
2024-05-28 18:40:47 -07:00
Hansung Kim
3b1ab4e10d
Write four-element dpu without accumulation
2024-05-28 18:27:56 -07:00
Hansung Kim
db889c5e22
Disable coalescer chiseltests
2024-05-28 16:43:02 -07:00
Hansung Kim
4dba0def01
Do proper recoding and boxing for FMA input
2024-05-28 16:41:44 -07:00
Hansung Kim
615815acf5
Add placeholder tensor core DPU module
2024-05-27 21:16:53 -07:00
