Hansung Kim
|
719b8048ab
|
[debug] Print warp id for memtraces
|
2023-09-26 13:36:22 -07:00 |
|
Hansung Kim
|
d34177ea9c
|
[debug] Elevate DEBUG_LEVEL for load/store; trace prefetch and fence
|
2023-09-26 11:44:20 -07:00 |
|
Hansung Kim
|
c90fe56588
|
More doc comments
|
2023-09-20 14:42:56 -07:00 |
|
Hansung Kim
|
f46383f350
|
Add #include <array> to fix compile error
gcc complains std::array being undeclared when trying to build a fresh
clone.
|
2023-07-02 13:47:41 -07:00 |
|
Hansung Kim
|
8caf476b1a
|
Merge remote-tracking branch 'upstream/master'
|
2023-07-02 13:27:08 -07:00 |
|
Blaise Tine
|
dce5e79f65
|
toolchain update
|
2023-05-15 18:53:24 -04:00 |
|
Hansung Kim
|
9cf5a29917
|
simx: add cycle and core id to load/store memory debug trace
|
2023-02-17 18:31:29 -08:00 |
|
Hansung Kim
|
d81e4085e2
|
simx: add thread ID and vlen to load/store memory debug trace
|
2023-02-17 17:59:56 -08:00 |
|
Blaise Tine
|
1bd25acb0b
|
cmov
|
2022-02-05 17:58:12 -05:00 |
|
Blaise Tine
|
d297351211
|
simx64 bug fix
|
2022-02-05 17:13:16 -05:00 |
|
Blaise Tine
|
2fd93e1d89
|
Merge branch 'staging' of https://github.com/vortexgpgpu/vortex
|
2022-02-05 16:12:52 -05:00 |
|
Santosh Srivatsan
|
b7e5a83ba3
|
Merged branch xlen-parameterization into staging
|
2022-02-05 13:47:42 -05:00 |
|
Blaise Tine
|
3179541efe
|
minor update
|
2022-02-05 12:24:16 -05:00 |
|
Blaise Tine
|
bda77760c8
|
addition bug fixes
|
2022-02-05 09:14:35 -05:00 |
|
Blaise Tine
|
140124b423
|
additional bug fixes
|
2022-02-05 07:42:50 -05:00 |
|
Blaise Tine
|
703d3faf27
|
minor bug fixes
|
2022-02-05 06:37:54 -05:00 |
|
Blaise Tine
|
5fbace9fa0
|
fixed several bugs and refactor memory access
|
2022-02-04 17:50:19 -05:00 |
|
Blaise Tine
|
cf2a0a5f39
|
code refactoring
|
2022-02-04 00:07:24 -05:00 |
|
Santosh Srivatsan
|
836c777680
|
XLEN parameterization for simx
|
2022-02-03 15:19:31 -05:00 |
|
Blaise Tine
|
a06812f93f
|
minor updates
|
2022-02-01 22:51:33 -05:00 |
|
Santosh Srivatsan
|
54dd2cfe1d
|
Added xlen parameterization to types.h instead of xlen.h
|
2022-02-01 14:02:46 -05:00 |
|
Santosh Srivatsan
|
01d183c6a9
|
Removed xlen.h
|
2022-02-01 13:59:39 -05:00 |
|
Santosh Srivatsan
|
3eb2b71955
|
removed traces of xlen. Overloaded sext
|
2022-02-01 13:54:51 -05:00 |
|
Blaise Tine
|
d48f1c1c5f
|
minor updates
|
2022-02-01 06:53:31 -05:00 |
|
Santosh Srivatsan
|
a73f656d06
|
Minor bug fixes
|
2022-01-31 17:01:14 -05:00 |
|
Santosh Srivatsan
|
4cf596338d
|
Minor bug fixes
|
2022-01-31 15:53:49 -05:00 |
|
Blaise Tine
|
f7887d8720
|
refactoring device memory allocation and cleanup
|
2022-01-28 21:57:16 -05:00 |
|
Santosh Srivatsan
|
7e3a2fdb0f
|
Modifications to allow 64-bit riscv tests to run on travis CI
|
2022-01-27 15:55:19 -05:00 |
|
Santosh Srivatsan
|
7aa93a735d
|
Added FLEN parameterization for RV32/64 F and D instructions
|
2022-01-24 15:42:15 -05:00 |
|
Santosh Srivatsan
|
ad92c09f5b
|
Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile
|
2022-01-22 13:47:44 -05:00 |
|
Santosh Srivatsan
|
91c22a2592
|
Fixed some riscv-tests
|
2022-01-22 12:54:10 -05:00 |
|
Santosh Srivatsan
|
d762d401cd
|
Added 64-bit linker script
|
2022-01-11 17:22:16 -05:00 |
|
Blaise Tine
|
29df0da8b5
|
minor warning fixes
|
2022-01-10 20:33:37 -05:00 |
|
Santosh Srivatsan
|
f93303bac7
|
Minor update
|
2021-12-15 17:21:38 -05:00 |
|
Santosh Srivatsan
|
71acf4eadb
|
Changed instruction size from wsize() * 4 to wsize() * 8
|
2021-12-13 20:42:44 -05:00 |
|
Santosh Srivatsan
|
d8796efd89
|
Minor update
|
2021-12-13 20:39:40 -05:00 |
|
Santosh Srivatsan
|
b1e82223ee
|
Renamed rv_f* functions to rvf*_s to follow the naming convention between single and double precision floating point
|
2021-12-13 20:37:29 -05:00 |
|
Santosh Srivatsan
|
76eb79d7fa
|
Removed pipeline.cpp
|
2021-12-13 19:57:47 -05:00 |
|
Santosh Srivatsan
|
4abfca4cb2
|
Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI
|
2021-12-13 19:55:02 -05:00 |
|
Santosh Srivatsan
|
e82d5fe48f
|
Removed all comments labelled \'simx64\'
|
2021-12-13 19:52:13 -05:00 |
|
Santosh Srivatsan
|
67daa6e616
|
Minor update
|
2021-12-11 17:58:31 -05:00 |
|
Santosh Srivatsan
|
885bb58ca9
|
Merged RV64IMFD extensions to master branch
|
2021-12-11 17:06:29 -05:00 |
|
Santosh Srivatsan
|
3324b32a29
|
Moved Dockerfile to miscs
|
2021-12-10 21:54:41 -05:00 |
|
Santosh Srivatsan
|
5edb9098ce
|
Merge branch 'simx64'
|
2021-12-10 21:48:29 -05:00 |
|
Santosh Srivatsan
|
e7bc436b52
|
Renamed simX to simx
|
2021-12-10 16:57:29 -05:00 |
|
Santosh Raghav Srivatsan
|
bde789b320
|
Added support for RV32D and RV64D instructions
|
2021-12-10 16:30:24 -05:00 |
|
Blaise Tine
|
0e2de4f13a
|
prefetch test fixes
|
2021-12-09 04:54:10 -05:00 |
|
Blaise Tine
|
5825b7c15a
|
dram simulator fix
|
2021-12-07 22:44:06 -05:00 |
|
Santosh Raghav Srivatsan
|
e6eda67d0c
|
Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension
|
2021-12-06 18:55:13 -05:00 |
|
Blaise Tine
|
b741807f8c
|
using ramulator dram simulator
|
2021-12-06 01:22:45 -05:00 |
|