0ad87bde81
Implement WU architecture support
2026-05-25 19:25:05 +08:00
joshua
5bd25985c6
i kinda forgot most of changes
2024-05-04 23:01:47 -07:00
Blaise Tine
4e7a536918
adding tensor regression test.
2023-11-14 05:37:46 -08:00
Blaise Tine
62cdd8e993
minor update
2023-11-11 15:49:39 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
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cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
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minor updates
minor updates
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minor updates
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minor update
2023-11-10 02:47:05 -08:00
felsabbagh3
9a0c5e0dbc
Removed kernel
2019-11-07 00:15:07 -05:00
felsabbagh3
87ae5c8cdf
Fixed emulator
2019-11-06 23:30:07 -05:00
felsabbagh3
46b09028d0
Added runtime (kernel 2.0)
2019-10-30 23:40:01 -04:00
felsabbagh3
7863175233
Set associative bank working
2019-10-30 14:57:20 -04:00
felsabbagh3
3b49b82c46
GPR ASIC Working
2019-10-29 23:20:16 -04:00
felsabbagh3
4aa04e76e6
Simulate debug
2019-10-29 14:28:20 -04:00
felsabbagh3
0ee74bc566
migrated 100% to modelsim
2019-10-27 20:08:44 -04:00
felsabbagh3
715982cca7
Modelsim Working + Simulating + dumping - Some bugs
2019-10-27 03:36:02 -04:00
felsabbagh3
89d0390965
CACHE FINALLY WORKING
2019-10-25 04:01:23 -04:00
felsabbagh3
01efe02e8b
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
felsabbagh3
1e648c5819
FIxed first circular issue
2019-10-24 10:38:04 -04:00
felsabbagh3
1645a04b1d
Fixed SM + added def SYN
2019-10-22 15:56:30 -04:00
felsabbagh3
b7af8c3f34
Integrated Shared Memory
2019-10-22 05:03:47 -04:00
felsabbagh3
b3f464dd89
Barriers impl + tested
2019-10-22 01:47:39 -04:00
felsabbagh3
31d3d51392
WSPAWN imp + tested
2019-10-21 23:35:53 -04:00
felsabbagh3
b6375e76de
Readded IPDOM stack + SPLIT/Join tested
2019-10-21 21:24:49 -04:00
felsabbagh3
84f5ccb484
Added CSR TID/WID reads
2019-10-21 02:10:05 -04:00
felsabbagh3
62db9ae691
minor
2019-10-17 12:04:06 -04:00
felsabbagh3
8bc3b8b0a5
Need to link SystemC for sc_time_stamp()
2019-10-14 23:25:14 -04:00
felsabbagh3
ee83e6d8c8
Moved GPR to back-end
2019-10-14 19:08:32 -04:00
felsabbagh3
e67310acfb
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
felsabbagh3
8d143d7739
Quartus + GPR evaluation
2019-09-10 20:23:01 -04:00
felsabbagh3
4e8da1811a
New GPR structure - Clone or WSPAWN
2019-09-09 22:17:20 -04:00
felsabbagh3
cde45648ea
Added Bug coments
2019-06-12 08:27:48 -07:00
felsabbagh3
3e93301846
Added Bug coments
2019-06-12 08:26:04 -07:00
felsabbagh3
32d1bfb140
Barrier bug comment
2019-06-12 08:22:03 -07:00
felsabbagh3
db0860a7fb
Recompiled kernel
2019-06-12 08:09:31 -07:00
felsabbagh3
b3256a7b7f
Fix barrier bug
2019-06-12 08:03:30 -07:00
felsabbagh3
b216da5a6a
ram stdint + Quartus Files
2019-06-11 21:13:30 -07:00
felsabbagh3
d7afef04a9
Sim Work miss
2019-05-18 23:42:55 +04:00
felsabbagh3
8995267cd3
Added barriers
2019-05-17 08:34:00 +04:00
felsabbagh3
48468ed26a
Proper SIMT with fine-grain scheduler implemented
2019-05-10 00:49:54 -07:00
felsabbagh3
79356c7ab1
Changed hierarchy + Identified private + public modules
2019-05-07 23:45:05 -07:00
felsabbagh3
f21eaec79f
Provisioned SM
2019-04-05 19:25:54 -04:00
felsabbagh3
166b9ae48d
Before Scratchpad
2019-04-05 17:56:05 -04:00
felsabbagh3
8c2ae97510
1 WARP 8 THREADS TESTED + FULLY WORKING
2019-03-31 05:21:00 -04:00
felsabbagh3
c83ef94d02
1 WARP 2 THREADS WORKING
2019-03-31 05:02:55 -04:00
felsabbagh3
6c64fa35f8
Restructure
2019-03-22 04:14:52 -04:00
