Hansung Kim
d9ad4809ec
Add 'tensor' bit to commit_if and writeback_if
...
For use in the asynchronous tensor instruction. When 1'b1, sets/unsets
the inuse_tensor status bit in the scoreboard to signal
kickoff/completion of the asynchronous tensor op.
2024-10-11 15:42:25 -07:00
Hansung Kim
87b966a5fa
Add perf counter for stall by any operand hazard
2024-04-15 01:01:26 -07:00
Hansung Kim
62c7d1f4cf
Report any fire cycles from scoreboard as well
2024-03-29 12:23:15 -07:00
Hansung Kim
50263a5f7d
Rename sched_barrier_stalls -> perf_sched_barrier_idles
...
Sched stall by barrier is really idle because it causes !scheduler_if.valid,
which is counted as part of sched_idle.
2024-03-28 22:45:12 -07:00
Hansung Kim
83e151a189
Add valid / fire / cycles-issued perf counters to dispatch
2024-03-23 00:01:15 -07:00
Hansung Kim
9438862389
Add perf counter for barrier schedule stalls
2024-03-20 15:29:28 -07:00
Blaise Tine
8ab7c590fd
disabling fetch's deadlock check when L1 caches are present
2024-01-31 06:16:54 -08:00
Blaise Tine
e217bc2c23
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
Blaise Tine
c7a81d1493
adding sockets support to simx and cache subsystem refactoring
...
minor update
minor update
minor updates
2023-12-20 15:16:12 -08:00
Blaise Tine
e04e026a14
profiling update
...
minor updates
2023-12-18 04:43:44 -08:00
Blaise Tine
24973ffca0
scoreboard optimization & profiling
2023-11-27 05:53:36 -08:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
d7737542e4
cache uuid support
2021-12-09 20:43:22 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
fe862f64b1
dispatch refactoring
2021-10-19 15:16:00 -04:00
Blaise Tine
e248f744d5
Merge branch 'master' of https://github.com/vortexgpgpu/vortex
2021-10-19 03:07:13 -04:00
Blaise Tine
58a2140b92
merge update
2021-10-15 19:58:13 -07:00
Blaise Tine
e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
Santosh Raghav Srivatsan
dd12d3f848
vortex tutorial assignment 5 solution
2021-10-15 18:25:54 -04:00
Blaise Tine
04249c3ee9
code refactoring for Vivado compatibility
2021-09-29 04:48:53 -04:00
Blaise Tine
a45261b530
code refactoring for Vivado compatibility
2021-09-29 03:24:17 -04:00
Blaise Tine
18c1dc2f0e
fixed interface modports
2021-09-28 02:42:04 -07:00
Blaise Tine
9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
3d052e9428
fmax optimization bundle (250 MHz).
2021-09-08 02:26:39 -07:00
Blaise Tine
05bc970900
minor update
2021-09-07 23:57:14 -07:00
Blaise Tine
3e014c8285
fmax optimizations bundles
2021-09-06 01:36:57 -07:00
Blaise Tine
b52ace5142
area optimization bundle
2021-09-05 23:35:44 -07:00
Blaise Tine
a801a16062
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
Blaise Tine
b1eef0fb7c
warp scheduler optimization
2021-08-07 23:45:01 -07:00
Blaise Tine
b5af2065ee
fetch optimization
2021-08-07 12:57:14 -07:00
Blaise Tine
e4d9fd8a00
thread mask redesign
2021-08-05 17:32:58 -07:00
Blaise Tine
7b8fe11e6a
unused variables refactoring
2021-08-05 01:46:26 -07:00
Blaise Tine
bb1ceffadd
rebase master update
2021-07-30 21:03:14 -07:00
Blaise Tine
0319283ea7
minor update
2021-07-20 21:42:22 -07:00
Blaise Tine
8048796102
minor update
2021-07-20 21:23:31 -07:00
Blaise Tine
aa7b0da877
minor update
2021-07-20 21:07:41 -07:00
Blaise Tine
d3b788784a
memory interface refactoring
2021-07-20 21:06:55 -07:00
Blaise Tine
382585d33d
minor update
2021-07-17 07:22:16 -07:00
Blaise Tine
5c40422e4f
dcache response bus optimization
2021-07-12 10:14:48 -07:00
Blaise Tine
c6afc35989
adding data fence support
2021-06-28 06:12:18 -07:00
Blaise Tine
f84c8a0b5d
instr_sched => ibuffer
2021-06-27 19:36:43 -07:00
Blaise Tine
1ea738ed26
lkg build
2021-06-25 16:28:10 -07:00
Blaise Tine
3cc1190cd7
CSRs I/O refactoring
2021-06-11 03:08:07 -07:00
Blaise Tine
5d2437d887
refactoring cache_config
2021-05-27 14:41:46 -07:00
Blaise Tine
8410c49f53
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
Blaise Tine
d808aa2735
perf counters generic size
2021-04-25 21:15:24 -07:00
Blaise Tine
10a994d11a
csr minor update
2021-03-08 03:46:07 -08:00
Blaise Tine
062d02ddce
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
Blaise Tine
b441870789
rename use_imm and use_PC
2021-03-01 00:38:46 -08:00
Blaise Tine
e64996946d
using 44-bit perf counters - aligned with DSP counters width
2021-02-28 02:05:47 -08:00
