Commit Graph

56 Commits

Author SHA1 Message Date
Hansung Kim
0e078b2701 Remove unnecessary make clean in run-radiance.sh 2024-01-17 11:36:40 -08:00
Hansung Kim
3190224cfe Squelch inout coerce lint messages from vortex RTL 2024-01-16 16:32:30 -08:00
Hansung Kim
0bb2a5c6f2 Accept EXTRA_SIM_PREPROC_DEFINES in run-radiance.sh 2024-01-16 16:31:26 -08:00
Hansung Kim
fdf02063a3 Add scripts for vortex binfile setup and sim runs 2023-12-30 16:36:34 -08:00
Hansung Kim
2e3a2af0c6 run-coalperfs.sh: Fix output directory path 2023-07-22 16:28:34 -07:00
Hansung Kim
016f293da1 Add 2bit-sourceId configs to CoalescerConfigs
... and add those to run-coalperf.sh

It seemed before that configs with narrower sourceId are more likely to
fail because of more contention between outstanding requests, so test
more of those configs.
2023-07-22 15:41:13 -07:00
Hansung Kim
d60dacf6ea Merge remote-tracking branch 'upstream/main' into graphics 2023-07-22 14:45:48 -07:00
Hansung Kim
d85a651324 run-coalperf.sh: disable 512-bit sbus configs
Currently Chipyard fails to elaborate with SBus width of 512 bits. It's
unclear if this is a problem in the coalescing unit or in Chipyard in
general.  For now, only enable configs that use sbus widths up to 256
bits.
2023-07-22 14:31:57 -07:00
Hansung Kim
cbe982a7ac run-coalperf.sh: exit on error, use output dir, don't make clean 2023-07-22 14:09:26 -07:00
Abraham Gonzalez
c1ad70c10f Merge pull request #1375 from ucb-bar/use-fat-jar
Use fat jar's to remove SBT invocations
2023-05-26 17:03:42 -07:00
abejgonzalez
b65d8ef6c6 Have global location to store jar files (avoid issue with sbt assembly caching) 2023-05-26 13:14:06 -07:00
Jerry Zhao
4da1dea50f Support multi-binary-run in RTL sim 2023-05-24 16:48:18 -07:00
Vamber Yang
9efd72ee2b Add more configs for coalescer perf testing
Add run-coalperfs.sh in sims/vcs for ease of testing (please delete this file in the future)
2023-05-20 08:52:15 -07:00
Jerry Zhao
a0569208a5 Fix VCS waveforms 2023-05-10 15:49:59 -07:00
abejgonzalez
95349755b5 Support TestDriver.v as top 2023-03-13 11:11:23 -07:00
joey0320
a9209c4aaa Fix TestDriver.v missing from gen-collateral after recompiling 2023-02-21 21:52:03 -08:00
abejgonzalez
55950b61b9 Move sim_files creation after FIRTOOL | Have FIRTOOL delete collateral dir 2023-02-15 12:01:58 -08:00
joey0320
58a6e72528 rename OUT_DIR to GEN_COLLATERAL_DIR 2023-02-13 13:24:04 -08:00
joey0320
6cd46d3c73 fixes 2023-02-13 02:14:23 -08:00
abejgonzalez
9f2fd22cc0 Rename variables | Small fixes | Move out-srcs to new dir 2023-01-09 10:32:44 -08:00
abejgonzalez
c179f53ed0 Fix comments 2023-01-09 10:25:29 -08:00
abejgonzalez
ca88bf5a2f Fix VCS 2023-01-09 10:25:29 -08:00
Jerry Zhao
a72d466646 Add support for FSDB (#1072) 2022-01-10 09:24:05 -08:00
abejgonzalez
16cdc88c52 Small comment + org. fix | Remove extra mkdirs 2021-05-12 16:42:05 -07:00
abejgonzalez
a0de9a0cfb Depend on build_dir 2021-05-06 20:36:28 -07:00
abejgonzalez
95f55a667f Elaborate comments a bit more | Remove BB'ed files that are auto-copied/added 2021-05-06 14:45:45 -07:00
abejgonzalez
1d52899736 Remove GenerateSimFiles and use make instead 2021-05-06 00:27:11 -07:00
abejgonzalez
b729a5f4a4 Allow run-asm/bmark debug make targets to specify random seed 2021-03-19 17:34:47 -07:00
abejgonzalez
fa97359516 Cleanup VCS's csrc directory | Fix small doc typo 2020-08-21 17:02:06 -07:00
Abraham Gonzalez
4f3319dc01 Revert make clean for VCS 2020-08-19 22:16:45 -07:00
Abraham Gonzalez
b7d9472b4a Cleanup help commands 2020-08-19 22:10:18 -07:00
Abraham Gonzalez
3b991f3ed7 Move vcs flags to vcs.mk | Misc. cleanup 2020-08-18 11:14:01 -07:00
Abraham Gonzalez
4e7b9d195f Dedup default simulation rules 2020-08-18 10:45:11 -07:00
Abraham Gonzalez
d82e7dbed5 Cleanup more 2020-08-18 10:40:45 -07:00
Abraham Gonzalez
b007d79820 Add help section to makefiles + Reorganize 2020-08-17 20:28:05 -07:00
Jerry Zhao
b719919934 Add RANDOM_SEED variable to set random init for VCS and Verilator simulations 2020-07-20 18:25:18 -07:00
Jerry Zhao
71f340a0af Use output_dir for run-binary logs and waveforms (#596)
* Dump run-binary files in output/$(long_name) instead of current directory
* Remove run-none rules, these were equivalent to run-binary BINARY=none
2020-06-12 10:08:55 -07:00
Colin Schmidt
171b805d0e Allow dramsim_ini folder to be set at the command line 2020-06-05 16:55:13 -07:00
Colin Schmidt
400b4e0c58 Merge remote-tracking branch 'origin/dev' into hammer-sim-integration 2020-05-23 21:35:37 -07:00
Colin Schmidt
5407018bb4 Respond to PR comments
clean up usage of vcs.mk
Bump hammer and plugins for updated API
2020-05-21 12:26:45 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Howard Mao
a905dbedcc add make rules for running simulator without executable 2020-04-28 10:32:28 -07:00
Howard Mao
b813caf6fd get icenet and testchipip unit tests working 2020-04-28 10:32:28 -07:00
Abraham Gonzalez
3d253c0f67 [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder
2020-03-30 17:04:45 -07:00
Abraham Gonzalez
d0bec3fba7 Ariane Integration (#448)
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile

* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore

* [firesim] bump

* [ci] add midas ariane tests

* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments

* [ci] remove references to local verilator install

* [verilator] update flags

* [verilator] minimal set of flags for ariane

* [ariane] bump ariane to master

* [ci] revert to 4.016 verilator

* [ci] install verilator to ci server | misc compile fixes

* [ci/make] add longer ci timeout | update when assert is added in verilator sim

* [firesim] bump for misc. updates

* [make/ci] cleanup makefile and remove firesim tests of it

* [docs/firesim] bump and clean docs

* [firesim] bump

* [ci] use remote verilator for midas tests

* [misc] cleanup built.sbt more

* [firesim] bump

* [misc] bump build.sbt patch for tutorials

* [firesim/ci] cleanup and bump firesim
2020-03-09 18:06:41 -07:00
Howard Mao
24fe57d447 use blackboxed SimDRAM instead of SimAXIMem 2020-03-02 20:49:20 -08:00
Colin Schmidt
f3d1bb8219 WIP: Add the ability to generate a hammer-sim config for gate-level sims
Still need to work on the asm-test/benchmark integration
2020-02-27 16:34:39 -08:00
Jerry Zhao
5d27ac5bbc [sim] Pipe /dev/null to simulators to fix VCS messing up stdout (#417) 2020-01-30 10:08:53 -08:00
abejgonzalez
8f2c5d4796 add *.log files whenever a binary is run 2019-10-14 20:55:40 -07:00
Albert Ou
383b58542f vcs: Statically link against libfesvr
libfesvr.so is no longer built after fesvr merged with riscv-isa-sim.
2019-10-02 13:16:02 -07:00