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2f1776fc6ac846392d2cc44bb0ad2c8fa8cab891
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224 Commits

Author SHA1 Message Date
Jerry Zhao
2f1776fc6a Add LLCChiplet to CI 2024-02-25 15:54:55 -08:00
Jerry Zhao
466ff06548 Merge remote-tracking branch 'origin/main' into serial-phits 2024-02-25 15:12:35 -08:00
joonho.whangbo
74998229fb Add large boom cospike config 2024-02-05 23:17:26 -08:00
Jerry Zhao
bf010668e3 Bump firechip 2024-01-26 18:40:08 -08:00
Jerry Zhao
45d74f6db2 Merge remote-tracking branch 'origin/main' into symmetric_sertl 2024-01-11 11:43:24 -08:00
Jerry Zhao
8073ecb1e8 Merge pull request #1697 from ucb-bar/clock_tap 
Add debug clock tap port to all default designs
 2024-01-11 11:38:20 -08:00
Jerry Zhao
d51a9a74d3 Merge remote-tracking branch 'origin/main' into clusters 2024-01-09 13:30:26 -08:00
-T.K.-
3eef3c36a6 Merge branch 'main' into clock_tap 2023-12-29 16:59:29 -08:00
Jerry Zhao
835562238a Explicitly pass chipId to all HarnessBinders 2023-12-26 18:37:39 -08:00
Jerry Zhao
194d4462f9 Update testchipip with source-synchronous serdes 2023-12-21 20:33:24 -08:00
Jerry Zhao
cfd555ee94 Bump testchipip for updated sertl type names 2023-12-21 14:18:06 -08:00
Jerry Zhao
1e5ebf192a Update firesim/firechip with new testchipip packaging 2023-12-19 12:11:12 -08:00
Jerry Zhao
b02621db35 Merge remote-tracking branch 'origin/main' into clusters 2023-12-16 17:00:34 -08:00
Jerry Zhao
2f1012294d Merge branch 'main' into clock_tap 2023-12-16 16:56:10 -08:00
Jerry Zhao
e7f10348b0 Merge remote-tracking branch 'origin/main' into clusters 2023-12-15 16:46:51 -08:00
Jerry Zhao
b37b6b0d9b Remove clock tap from firesim designs 2023-12-15 15:51:04 -08:00
Jerry Zhao
30ac9dc2c8 Merge remote-tracking branch 'origin/main' into tcip-bump 2023-12-14 10:58:57 -08:00
Abraham Gonzalez
4132296831 Update TargetConfigs.scala 2023-11-15 16:49:19 -08:00
Jerry Zhao
a8766ea8fc Precisely specify bus frequencies 2023-10-31 14:25:16 -07:00
Jerry Zhao
d83f395738 Update firechip for new testchipip 2023-10-24 18:42:27 -07:00
Jerry Zhao
a4be708771 Fix firechip cbus freq 2023-10-22 14:23:35 -07:00
Jerry Zhao
aa057239f2 Bump rocket-chip + submodules for new clustered-tile API 2023-10-17 14:38:28 -07:00
Jerry Zhao
3cbcf6b6e8 Fix TSIBridge loadmem param 2023-10-11 15:01:39 -07:00
Jerry Zhao
b949324d5a Fix FireSim UARTBridge 2023-10-06 17:55:14 -07:00
Jerry Zhao
e6203bb25c Fix fsim supernode memmodel 2023-10-05 23:56:29 -07:00
Jerry Zhao
eb3a0aecf4 Add PortAPI between IO and Harness blocks 2023-10-05 15:02:56 -07:00
Jerry Zhao
57ee757016 Remove MultiClockHarnessAXIMem 
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.

Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
 2023-09-16 09:47:47 -07:00
abejgonzalez
a48746f113 Deprecate Dromajo in FireSim, use cospike 
Move Cospike to testchipip
 2023-08-30 17:55:04 -07:00
Jerry Zhao
563897ba22 Add WithUARTInitBaud/fix firesim uart configs 2023-06-19 06:03:56 -07:00
Jerry Zhao
1e3d4aad46 Update WithBackingScratchpad for firechip 2023-06-09 00:06:30 -07:00
Jerry Zhao
2f2cb1ac8b Fix firesim clockgen to auto-generated the reference pll clock if not requested 2023-05-27 11:16:18 -07:00
Jerry Zhao
3f06dbc280 Fix clock group combiner behavior for rational-tile clocks 2023-05-26 17:50:55 -07:00
Jerry Zhao
f73951ac7f Add TestChipConfigTweaks to model 2/1 tile/uncore division 2023-05-26 11:56:58 -07:00
Jerry Zhao
b69bcffc91 Merge remote-tracking branch 'origin/main' into unify 2023-05-19 11:28:52 -07:00
Jerry Zhao
f4739be632 Update multi-chip API for harnesses 2023-05-15 00:03:22 -07:00
Jerry Zhao
d4d81f7d22 Rename serialManagerParams -> serialTLManagerParams 2023-05-13 19:25:14 -07:00
Jerry Zhao
3330c23193 Support uni-directional TLSerdesser 2023-05-13 14:14:38 -07:00
Jerry Zhao
2077e4304d Explicitly provide refClockFreqMHz to harnessClockInstantiator 2023-05-13 11:18:03 -07:00
Jerry Zhao
b8e95e0305 Rename implicit clock/reset to referenceclock/reset 2023-05-12 15:11:44 -07:00
Jerry Zhao
94d471bd9a Set firesim harnessbinder freq to 1000 MHz by default 2023-05-12 14:44:07 -07:00
Jerry Zhao
607c2b5a73 Unify multi-node btw chipyard/firechip | unify harness clocking 2023-05-12 08:41:34 -07:00
Jerry Zhao
fbfb518b72 Merge remote-tracking branch 'origin/main' into renameserial 2023-05-10 11:39:11 -07:00
Sagar Karandikar
1c10f75622 Merge pull request #1471 from ucb-bar/lowmem-configs 
Add 1GB / 4GB DRAM firechip configs for FireSim VCU118
 2023-05-10 11:32:01 -07:00
Sagar Karandikar
abe8a7fb8b remove extra newlines 2023-05-10 11:31:05 -07:00
Jerry Zhao
eced8e63d9 Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness 2023-05-08 18:19:18 -07:00
Sagar Karandikar
95da9cefb5 4GB DRAM configs 2023-05-08 13:41:51 -07:00
Jerry Zhao
ac281daa78 Move TestHarness to chipyard.harness, make chipyard/harness directory 2023-05-08 08:00:56 -07:00
Jerry Zhao
4f5bbdca97 Flip serial_tl.clock for firechip BridgeBinders 2023-05-07 22:22:37 -07:00
Sagar Karandikar
40d0a1f3bd low mem configs 2023-05-07 11:47:14 -07:00
Jerry Zhao
df2e5ad9dc Bump to latest rocket-chip/chisel3.5.6 2023-03-28 16:48:27 -07:00