Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).
Requires: ucb-bar/barstools#92 and firesim/firesim#658
The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests. You will likely want to bump further.
* Fixes bug with AXI4 MMIO ports not being generated properly due to
IOBinders issue. Additionally adds IOCells to AXI4 ports so that they
appear in ChipTop
* Change IOBinders to also require passing p: Parameters
to child functions. Serialization of type targets via ClassTags fails
for compound types, so we cannot use `BaseSubsystem with HasSomeTrait`
as the type target in OverrideIOBinders.
* [uart] add uart adapter | add uart + adapter to all configs
* [uart] change pty define name | add uart to all configs that need it
* [uart] default to 115200 baudrate
* [dromajo] first working commit
* [dromajo] bump boom for commit-width > 1 fix
* [dromajo] adjust dromajo commits
* [dromajo] bump boom
* commit dromajo changes
* extra
* [dromajo] add block device to configs
* rebump older modules
* bump firesim
* [chipyard] enable dromajo in midas level simulation
* [testchipip] forgot to bump
* get rid of breaking things
* bump firesim
* bump boom
* Bump BOOM to ifu3 WIP
* bump firesim
* fix how memory is passed to dromajo
* bump boom and firesim
* fix merge issues
* add dromajo cosim bridge in chipyard
* move traceio back into testchipip (#488)
* refer to testchipip traceio in firechip (#490)
* Move TraceIO fragment to chipyard (#492)
* fix chipyard dromajo bridge (#493)
* Sboom dromajo bump (#501)
* [FireChip] Use clock in BridgeBinders
* [firesim] Update TraceGen BridgeBinder
* [Firechip] Add support for Tile <-> Uncore rational division
* [firesim] Update the multiclock test
* [firechip] Commit some Eagle X-related mock configs
* [firechip] Instantiate multiple TracerV bridges
* [Firechip] Include reset in tracerv tokens
* [TracerV] Drop the first token in comparison tests
* [Firechip] Make reverse instruction order in trace printf
* WARNING: Point at a fork of boom @ davidbiancolin
* [firesim] Update ClockBridge API
* Add Gemmini to README [ci skip] (#487)
* [firechip] Isolate all firesim-multiclock stuff in a single file
* add documentation on ring network and system bus
* Bump firesim for CI
* Bump FireSim
* Bump testchipip to dev
[ci skip]
* Bump FireSim
* [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags
* [make] move dramsim and max-cycles into SIM_FLAGS
* [misc] move ariane configs to configs/ folder
* [dromajo] add dromajo
* [dromajo] bump for new traceio changes
* bump firesim
* bump firesim
* point to chipyard traceio
* bump boom
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
* Support Dromajo + TracerV configurations
* [docs] add documentation for Dromajo in FireSim + Chipyard
* add a bit more docs
* [docs] bump docs
* [firesim] dump artefacts in firesim
* [firesim] update firesim
* [testchipip] remove extraneous items in testchipip
* [dromajo] prevent dromajo from breaking when params unset
* update firesim, dromajo, and testchipip
* [firesim] bump firesim
* [firesim] bump firesim
* [misc] bump firesim and testchipip for reviewer comments
* remove WithNoGPIO fragment
* bump firesim
* bump dromajo boom config
* bump firesim
* generate artefacts in firesim testsuite
Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.
BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.
The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork
Treadle is bumped to its release branch
* Add c test files for DSPTools example
* Update tests Makefile to build DSPTools c tests
* Add DSPTools example configs to ConfigMixins and RocketConfigs
* Add dsptools and rocket-dsptools as dependancies for example
* Add Scala implementations of DSPTools test blocks
* Clean up GenericFIR scala
* Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial
* Update documentation, will need reworking once FIR is characterized as fixed point
* Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain
* Fix capitalization in docs (#419)
* Add c test files for DSPTools example
* Update tests Makefile to build DSPTools c tests
* Add DSPTools example configs to ConfigMixins and RocketConfigs
* Add dsptools and rocket-dsptools as dependancies for example
* Add Scala implementations of DSPTools test blocks
* Clean up GenericFIR scala
* Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial
* Update documentation, will need reworking once FIR is characterized as fixed point
* Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain
* Update docs/Customization/Dsptools-Blocks.rst
Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>
* Docummentation update for clarity and to explain how this can be applied to a generalized block
* Some refactoring to get dsptools working with these examples
* Oops, old files crept in
Co-authored-by: Ryan Lund <ryan.lund@bwrcrdsl-4.eecs.berkeley.edu>
Co-authored-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
Co-authored-by: Paul Rigge <rigge@berkeley.edu>
[WIP] Minimally elaborating design
Bring up a feature-complete Chipyard stage
Pull in Makefrag generation; Bump submodules
Update config generation, and global reset scheme
Bump submodules; clean up
Bump FireSim
Remove some unhygenic comments / WS
Remove the rocketchip subproject
[CI] Lengthen ariane tests timeout
Address some remaining reviewer comments
[firechip] Refresh a Field that cannot be used across repeated instantiations
Bump all submodules
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019
* Fix subprojects that aren't tested from normal sims
* Fix firechip for chisel 3.2.0 and rc bump
* Bump boom for bug fix rebase
* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]
* Bump boom for rc bump fix to bug fix
* Bump FireSim for CI check
* Bump FireSim
* Bump submodules after merge
