Abraham Gonzalez
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0eca51ba4d
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Reorganize into bringup/simple | Bump sifive-blocks
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2020-10-27 12:57:34 -07:00 |
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Abraham Gonzalez
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3c42e2cae7
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Fixed BootROM | Updated HarnessBinders
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2020-10-26 18:15:58 -07:00 |
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Abraham Gonzalez
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db73cab164
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Add BootROM | Fix ResetWrangler for DDR | Add scripts
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2020-10-20 21:20:11 -07:00 |
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Abraham Gonzalez
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dd358f45ab
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UART Working... Bumped to newer fpga-shells
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2020-10-19 11:29:25 -07:00 |
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abejgonzalez
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9ba4918cb8
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Inject MMCDevice into TLSPI Node
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2020-10-15 11:46:42 -07:00 |
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abejgonzalez
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7f387a254b
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Working up until the MMC attachment
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2020-10-14 23:09:49 -07:00 |
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abejgonzalez
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dcac9b79df
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Basic working with UART
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2020-10-14 16:15:10 -07:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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abejgonzalez
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5bbd865447
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Add MMC Device section to the DTS
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2020-10-13 16:18:00 -07:00 |
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abejgonzalez
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8257775e96
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Connect DDR from harness
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2020-10-12 21:50:50 -07:00 |
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abejgonzalez
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f1b40d51af
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Connected clocks | Exposed Master TL port
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2020-09-15 12:58:58 -07:00 |
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abejgonzalez
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72c0f4b3d3
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Add GPIO Overlay
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2020-09-13 16:37:20 -07:00 |
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abejgonzalez
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69bf39bf13
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Added more overlays | Closer to bringup platform
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2020-09-12 18:18:13 -07:00 |
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abejgonzalez
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382e5f1ae8
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Add forgotten file
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2020-09-11 17:02:22 -07:00 |
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abejgonzalez
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e98a0f172f
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Connected UART nicely
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2020-09-11 16:55:25 -07:00 |
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abejgonzalez
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56eead4053
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NOT WORKING: VCU118 Commit
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2020-09-08 17:04:56 -07:00 |
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abejgonzalez
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2580073d75
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Comment cleanup
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2020-09-07 15:30:21 -07:00 |
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abejgonzalez
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c49eef3224
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Small cleanup to CY DigitalTop | Move E300 configs to unique folder
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2020-09-07 15:26:30 -07:00 |
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abejgonzalez
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a8083aa570
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First pass at fpga-shells with IOBinders
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2020-09-07 11:48:27 -07:00 |
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abejgonzalez
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1fa1b6d57f
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Small makefile cleanup
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2020-09-04 19:03:26 -07:00 |
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abejgonzalez
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8eb807a2fd
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Use DigitalTop in Platform | Use Chipyard BootRom
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2020-09-04 18:56:32 -07:00 |
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James Dunn
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990362933d
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Simple makefile variable fix to allow make mcs
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2020-09-04 14:16:42 -07:00 |
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abejgonzalez
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5a885fdcfd
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Delete old makefiles | Full switch to CY make system
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2020-09-03 21:28:05 -07:00 |
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abejgonzalez
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0656c5da4f
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First pass on using CY make system
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2020-09-03 20:29:19 -07:00 |
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James Dunn
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a8834c7766
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First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
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2020-09-02 12:48:44 -07:00 |
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