Jerry Zhao
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f9cc1dc2c2
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Merge remote-tracking branch 'origin/dev' into serial-tl
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2020-09-14 19:35:43 -07:00 |
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Jerry Zhao
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23a199eccf
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Merge pull request #674 from ucb-bar/iocells-fix
Undo regression in iocells flexibility
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2020-09-14 19:32:37 -07:00 |
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Jerry Zhao
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10625a3a6c
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Undo regression in iocells flexibility
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2020-09-14 13:27:31 -07:00 |
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Jerry Zhao
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16c80112a7
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Merge pull request #670 from ucb-bar/harness-refactor
Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges
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2020-09-14 12:45:46 -07:00 |
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Zitao Fang
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5506f77679
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Add CircleCI check and update Sodor config
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2020-09-14 09:14:57 -07:00 |
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abejgonzalez
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72c0f4b3d3
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Add GPIO Overlay
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2020-09-13 16:37:20 -07:00 |
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Jerry Zhao
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6c5bce5430
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Support Tilelink over serial
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2020-09-13 11:59:16 -07:00 |
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Jerry Zhao
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be0c041232
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Bump Firesim
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2020-09-13 06:36:37 +00:00 |
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Jerry Zhao
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d2b42cee2c
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Bump testchipip
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2020-09-12 23:31:54 -07:00 |
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abejgonzalez
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69bf39bf13
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Added more overlays | Closer to bringup platform
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2020-09-12 18:18:13 -07:00 |
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abejgonzalez
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382e5f1ae8
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Add forgotten file
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2020-09-11 17:02:22 -07:00 |
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abejgonzalez
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e98a0f172f
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Connected UART nicely
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2020-09-11 16:55:25 -07:00 |
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Jerry Zhao
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a5385c0a54
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Update testchipip/icenet to use rocket-chip Located API
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2020-09-11 00:02:07 -07:00 |
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Zitao Fang
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15d53e2cda
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Bump to the latest Rocket
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2020-09-09 15:12:37 -07:00 |
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Jerry Zhao
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facef464e6
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Update BridgeBinders | fix runtime HarnessBinder port type checks
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2020-09-09 00:15:02 -07:00 |
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Jerry Zhao
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8f9574fd79
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Clean up passing ports from IOBinders to HarnessBinders
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2020-09-08 22:30:17 -07:00 |
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abejgonzalez
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56eead4053
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NOT WORKING: VCU118 Commit
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2020-09-08 17:04:56 -07:00 |
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Jerry Zhao
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11a9ad2428
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Address code review comments
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2020-09-08 15:52:09 -07:00 |
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abejgonzalez
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2580073d75
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Comment cleanup
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2020-09-07 15:30:21 -07:00 |
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abejgonzalez
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c49eef3224
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Small cleanup to CY DigitalTop | Move E300 configs to unique folder
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2020-09-07 15:26:30 -07:00 |
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Jerry Zhao
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b4e270219d
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Bump firesim
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2020-09-07 14:02:31 -07:00 |
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abejgonzalez
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a8083aa570
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First pass at fpga-shells with IOBinders
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2020-09-07 11:48:27 -07:00 |
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Jerry Zhao
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7ed02a7d38
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Fix Typos
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2020-09-07 11:36:37 -07:00 |
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Zitao Fang
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fb7804070c
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-06 23:09:50 -07:00 |
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Zitao Fang
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11dcd71a48
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Clean up 5-stage instruction fetch
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2020-09-06 23:06:00 -07:00 |
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Abraham Gonzalez
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b6a54ead59
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Merge pull request #669 from ucb-bar/local-fpga-arty-abe
Misc Additions to Local FPGA Branch
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2020-09-06 21:00:57 -07:00 |
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Jerry Zhao
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24b39da31c
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Merge pull request #672 from ucb-bar/htif-dts-fix
DTM only supports HTIF in DMI mode
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2020-09-05 17:40:48 -07:00 |
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Jerry Zhao
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927244bf2e
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DTM only supports HTIF in DMI mode
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2020-09-05 11:45:06 -07:00 |
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Jerry Zhao
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ab21c53a42
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Add documentation on HarnessBinders
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2020-09-04 23:51:36 -07:00 |
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Jerry Zhao
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9eb88c55fc
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Fix FireSim submodule
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2020-09-04 23:07:23 -07:00 |
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Jerry Zhao
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b613c14f1c
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Fix remaining HarnessBinders bugs
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2020-09-04 20:03:12 -07:00 |
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abejgonzalez
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1fa1b6d57f
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Small makefile cleanup
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2020-09-04 19:03:26 -07:00 |
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abejgonzalez
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8eb807a2fd
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Use DigitalTop in Platform | Use Chipyard BootRom
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2020-09-04 18:56:32 -07:00 |
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Jerry Zhao
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0f50e4d118
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Split IOBinders into IOBinders and Harness Binders | punch out clocks to harness for simwidgets and bridges
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2020-09-04 15:20:13 -07:00 |
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James Dunn
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990362933d
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Simple makefile variable fix to allow make mcs
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2020-09-04 14:16:42 -07:00 |
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Jerry Zhao
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178a0e38b5
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Merge pull request #664 from ucb-bar/fix-debug-ios
Only punch realistic subset of DebugIO through chiptop | default to JTAG+Serial
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2020-09-04 09:47:59 -07:00 |
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Jerry Zhao
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3258fd8db8
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Remove JTAG from firesim comfigs due to @(posedge ~clk) issue
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2020-09-03 23:53:51 -07:00 |
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abejgonzalez
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5a885fdcfd
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Delete old makefiles | Full switch to CY make system
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2020-09-03 21:28:05 -07:00 |
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abejgonzalez
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0656c5da4f
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First pass on using CY make system
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2020-09-03 20:29:19 -07:00 |
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Jerry Zhao
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942d881c60
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Merge pull request #667 from ucb-bar/fast-find
Don't run find in base_dir to avoid slow filesystem search
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2020-09-03 13:47:09 -07:00 |
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Jerry Zhao
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23e4c22a44
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Don't run find in base_dir to avoid slow filesystem search
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2020-09-02 23:52:55 -07:00 |
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Zitao Fang
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0995f1b04b
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UCode passed all tests
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2020-09-02 21:25:36 -07:00 |
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Jerry Zhao
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4b30462320
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Change default IO set to JTAG+Serial, instead of JTAG+DMI
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2020-09-02 20:19:27 -07:00 |
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James Dunn
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3b6d584672
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Adding submodule update script for FPGA tools.
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2020-09-02 13:27:31 -07:00 |
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James Dunn
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a8834c7766
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First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
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2020-09-02 12:48:44 -07:00 |
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Zitao Fang
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bb1d0a10ae
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Stage 3 (single port) passed all tests
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2020-08-31 18:00:40 -07:00 |
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Jerry Zhao
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c8448cc3e1
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Bore out a bus clock to drive DebugIO from ChipTop
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2020-08-30 18:10:52 -07:00 |
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Zitao Fang
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5c5af7bfad
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Stage 3 passed all tests
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2020-08-28 18:37:47 -07:00 |
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Jerry Zhao
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17239c56f8
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Update AddIOCells.debug comment
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2020-08-28 14:36:09 -07:00 |
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Jerry Zhao
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20013d1348
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Add DTM based bringup to regressions
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2020-08-28 14:31:00 -07:00 |
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