John Wright
d97afcdfbc
Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a
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bug using verilator, make the whitespace consistend in
Makefrag-verilator, explicitly name the verilog sources to match vsim,
and update verisim/Makefile to use the new source variable names
2019-02-13 21:13:08 -08:00
John Wright
acd76e5410
Adding barstools to separate the top from harness and to generate the
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memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00
Abraham Gonzalez
d01e38ef8a
Re-add line on updated Makefrag
2019-02-03 20:17:45 -08:00
Howard Mao
fc06c909c0
fix README section on adding new submodules
2019-01-28 14:31:13 -08:00
Paul Rigge
de1ab1d8a9
Merge pull request #42 from grebe/axiPWM
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Add an AXI4 flavor of PWM peripheral.
2019-01-25 14:52:09 -08:00
Paul Rigge
8cf06db45c
Add an AXI4 flavor of PWM peripheral.
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Also closes #41 .
2019-01-24 17:13:40 -08:00
John Wright
304592f61e
Fixes FIRRTL compilation bug in testchipip unit tests
2019-01-18 00:04:04 -08:00
Edward Wang
d48587b671
Update project-template for testchipip master
2018-11-02 12:05:36 -07:00
Albert Ou
cd82131748
verisim: Add verilator-harness.cc from testchipip/csrc
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This fixes #35 and matches firechip.
238afa543f49b7982c82
2018-10-05 09:24:35 -07:00
Albert Ou
048492e54c
mk: Ensure that FIRRTL jar has updated timestamp
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SBT does not replace $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar if
compilation produces the same results.
2018-10-02 17:43:51 -07:00
Albert Ou
220aeea4c8
Bump rocket-chip
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- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
2018-09-29 13:30:07 -07:00
Howard Mao
a3684d01dd
use build.sbt instead of jar files to collect packages
2018-05-03 17:09:59 -07:00
Howard Mao
4c8c6e29f0
update rocket-chip again
2018-04-18 17:13:07 -07:00
olix86
b599514934
Update Makefrag-verilator
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Changed verilator version from 3.904 to 3.920, which fixes a bug that prevented the default example to compile correctly
2018-04-17 17:11:30 -07:00
Howard Mao
728251a922
fix bootrom race condition
2018-04-17 16:47:48 -07:00
Howard Mao
7dc738a831
DualCoreConfig should be actually dual core
2018-04-17 16:06:44 -07:00
Howard Mao
b8f369a4bd
switch to rebased testchipip branch
2018-04-17 15:56:22 -07:00
Howard Mao
7e70e3525f
move bootrom to testchipip
2018-04-17 15:13:47 -07:00
Howard Mao
f1a55d531e
bump rocket-chip to April commit
2018-04-17 11:59:45 -07:00
Howard Mao
28539dc562
bump rocket-chip to March commit
2018-04-16 19:33:51 -07:00
Howard Mao
d88c2fa84f
add regression tests to makefile
2018-02-23 13:48:45 -08:00
Howard Mao
073c16961e
make sure annotations are generated and carried through to verilog elaboration
2018-02-23 11:50:33 -08:00
Howard Mao
1dfe9b1c9f
bump rocket-chip and fix deprecated code in testchipip.GeneratorApp
2018-02-23 11:46:40 -08:00
Howard Mao
eaff48e312
fix issue #20 : PWMConfig elaboration error due to requirement failure
2018-02-23 10:54:05 -08:00
Howard Mao
e3f05011c1
bugfix for verilator test harness
2018-02-23 10:35:01 -08:00
Howard Mao
080fdb835e
fix testchipip SimSerial csrc for new htif_t constructor
2018-01-29 10:44:16 -08:00
Donggyu Kim
ed13397967
changes for new rocket-chip
2018-01-15 16:07:44 -08:00
Howard Mao
269660bbfe
take pingd and nic-loopback out of Makefile
2017-11-30 20:50:01 -08:00
Howard Mao
e4a4046375
get RV32 working
2017-11-03 18:00:27 -07:00
Howard Mao
52068497c4
changes to block device memory map
2017-10-26 13:27:20 -07:00
Howard Mao
2223932bd2
disable compressed instructions in bootrom
2017-10-26 13:26:57 -07:00
Howard Mao
5c200ddb6e
bump rocket-chip and testchipip
2017-10-26 13:20:13 -07:00
Colin Schmidt
44899f1b01
Merge pull request #19 from cpehle/patch-1
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Point to correct path of riscv-tools directory
2017-09-26 15:33:41 -04:00
cpehle
2e544f03e0
Point to correct path of riscv-tools directory
2017-09-26 19:52:39 +02:00
Howard Mao
93d6c52024
make sure mstatus bits are set properly before entering second boot stage
2017-09-14 23:41:32 -07:00
Howard Mao
4dd2d5f881
have core 0 interrupt other cores
2017-09-12 20:33:36 -07:00
Howard Mao
2a4e994b09
bump rocket-chip and testchipip
2017-09-11 16:52:23 +00:00
Howard Mao
92087ef388
get rid of NIC tests
2017-09-08 10:35:49 -07:00
Howard Mao
506afbb363
bump rocket-chip for flattened coreplex/system
2017-08-31 14:35:13 -07:00
Howard Mao
cb79078641
get rid of tlserdes project
2017-08-31 14:34:35 -07:00
Howard Mao
91df4098f3
remove SimpleNIC
2017-08-31 11:06:41 -07:00
Howard Mao
171abb54e7
fix README
2017-08-22 16:09:31 +00:00
Howard Mao
758e09037a
use stored MAC address in pingd
2017-07-21 21:50:28 +00:00
Howard Mao
f28f2379a4
SerialInterfaceWidth is not actually configurable
2017-07-21 06:12:25 +00:00
Howard Mao
ada96f3724
update verilator so that plusarg_reader works
2017-07-20 20:19:02 +00:00
Howard Mao
fae57b6daa
make sure verilator builds correctly
2017-07-20 19:44:23 +00:00
Howard Mao
6175249845
add project using a SERDES memory
2017-07-18 20:25:32 -07:00
Howard Mao
752a28893d
test multi-channel memory
2017-07-18 20:25:32 -07:00
Colin Schmidt
8e910df8ba
Merge pull request #12 from ucb-bar/fix-firrtl-error
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Build firrtl first so we dont get that weird error
2017-07-17 12:34:47 -07:00
Colin Schmidt
098b031dc6
remove old readme about publish local
2017-07-13 17:07:28 -07:00
