Richard Yan
5b4d34864f
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-12 02:24:20 -07:00
Richard Yan
19852693b7
dual core gemmini, unpeg gemmini size and smem width
2024-06-12 02:17:40 -07:00
Hansung Kim
1401c4a090
Separate out core id from tile id in TileParams
...
Create a new config key to distinguish number of cores from number of
total tiles (which can be different when there are Gemmini tiles).
It is important to give contiguous IDs for Vortex cores for the
cluter-wide barrier to work.
2024-06-11 17:13:51 -07:00
Hansung Kim
7ced63bd62
Remove clbus definition from RadianceCluster
...
Should be in conjunction with the rocket-chip change that defines clbus
in the base Cluster class.
2024-06-11 16:23:54 -07:00
Hansung Kim
a0bff40a87
Set correct static tileId for core and Gemmini tiles
...
Otherwise, in multiple cluster configs, tiles can have duplicate global
tileId which results in Diplomacy connection errors for interrupt nodes
(among other things).
2024-06-11 16:17:08 -07:00
Richard Yan
a8e35b1f5a
oopsie doopsie
2024-06-09 15:35:11 -07:00
Richard Yan
17756d5f53
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-09 15:26:07 -07:00
Richard Yan
3badd75473
framebuffer, shared memory key, etc
2024-06-09 15:05:31 -07:00
Hansung Kim
ca3fd8b515
Bump vortex with doc changes
2024-06-09 13:41:18 -07:00
Hansung Kim
3254ac3741
Doc changes
2024-06-09 13:39:53 -07:00
Hansung Kim
c7e2cd2387
Bump vortex with dispatch_unit fix
2024-05-30 22:00:10 -07:00
Hansung Kim
503a3ff246
Bump vortex
2024-05-30 18:33:56 -07:00
Hansung Kim
091115bb90
Bump vortex
2024-05-29 17:06:27 -07:00
Hansung Kim
2c196bb9a0
Update generated dpu verilog for stalls
2024-05-29 16:22:24 -07:00
Hansung Kim
17886dc050
Implement proper stalls for dpu
2024-05-29 16:21:12 -07:00
Hansung Kim
8e79e620cb
Bump vortex
2024-05-29 13:35:43 -07:00
Hansung Kim
d34c5836a8
Add chisel-generated verilog for dpu
2024-05-29 13:33:23 -07:00
Hansung Kim
4a43d0126d
Make dpu 2-stage
...
For debugging, need to revert.
2024-05-29 13:31:38 -07:00
Hansung Kim
40b27c9600
Fix test for DPU
2024-05-28 21:18:51 -07:00
Hansung Kim
793db0e29d
Add stall IO to dpu
2024-05-28 21:18:19 -07:00
Hansung Kim
907150e51c
Add accumulation to dpu
2024-05-28 18:40:47 -07:00
Hansung Kim
3b1ab4e10d
Write four-element dpu without accumulation
2024-05-28 18:27:56 -07:00
Hansung Kim
db889c5e22
Disable coalescer chiseltests
2024-05-28 16:43:02 -07:00
Hansung Kim
4dba0def01
Do proper recoding and boxing for FMA input
2024-05-28 16:41:44 -07:00
Hansung Kim
615815acf5
Add placeholder tensor core DPU module
2024-05-27 21:16:53 -07:00
Hansung Kim
387e05404e
Bump vortex
2024-05-27 18:31:51 -07:00
Hansung Kim
09d9d3c3f9
Bump vortex with multi-warp tensor core fix
2024-05-25 20:13:56 -07:00
Hansung Kim
114dd75f2f
Fix no-coalescer config by removing coreTagWidth from L1 config
...
coreTagWidth logic in WithVortexL1Banks doesn't work, because
VortexL1Key is defined before the CoalescerKey and therefore
WithVortexL1Banks fragment has no way of knowing if coalescer is
defined. Instead, figure out the core-side tag width within
VortexBankImp by querying the TL parameters.
The downside of this is that since VortexBankPassthrough's client node
no longer has a way of knowing the core tag width before the Diplomacy
phase, we need to set its sourceId bits as a fixed constant. A require
is in place to ensure no truncation of core-side's sourceId.
2024-05-25 15:08:45 -07:00
Hansung Kim
18e6a1f82d
Fix diplomacy import warning in coalescer
2024-05-25 12:41:57 -07:00
Hansung Kim
4b58958a8e
Bump vortex
2024-05-23 16:28:08 -07:00
Hansung Kim
047b5a33ee
Enable all-to-all unaligned smem by default
2024-05-16 20:11:06 -07:00
Hansung Kim
1bd4be301e
Fix double import error from diplomacy migration
2024-05-16 20:10:29 -07:00
Richard Yan
697c37b980
waddr cycle off by one
2024-05-15 23:42:27 -07:00
Richard Yan
c33ebeb906
microcode for dma and larger tile
2024-05-15 21:47:07 -07:00
Richard Yan
de29e5ca82
store fencing
2024-05-15 21:46:23 -07:00
Richard Yan
76fd951054
shared memory config and sane smem write delays
2024-05-15 21:37:51 -07:00
Richard Yan
1215bf4260
add synthesized printf for print buffer
2024-05-08 15:02:29 -07:00
Richard Yan
71edc439a0
revert lsuq size
2024-05-08 11:41:33 -07:00
Richard Yan
98ddc291c2
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-05-08 11:32:13 -07:00
Richard Yan
63b0bfdcd3
bump vortex
2024-05-08 11:32:12 -07:00
Hansung Kim
358bf18b6d
Bump vortex with merge fix
2024-05-07 18:38:25 -07:00
Hansung Kim
a0c7ce93d7
Add back LSUQ_SIZE logic
2024-05-07 16:17:59 -07:00
Hansung Kim
8148cc361c
Add assertion on numWarps >= numLsuLanes
2024-05-07 16:15:33 -07:00
Richard Yan
f698768b39
fix mshr size
2024-05-07 14:01:12 -07:00
Richard Yan
c5c4b3eb8b
bump vortex
2024-05-07 14:00:43 -07:00
Richard Yan
6ff8686b96
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-05-07 13:51:14 -07:00
Richard Yan
c916c2052d
acclerator cisc, fpga ready
2024-05-07 13:51:09 -07:00
Hansung Kim
9b2846fcee
Bump vortex to tensor_core merge
2024-05-02 16:18:51 -07:00
Hansung Kim
3e3678fbcb
Enable addResources for tensor_core
...
Adds back some non-synthesizable modules.
2024-05-02 15:06:46 -07:00
Richard Yan
a915451d03
wide dram support and enlarge queues
2024-04-28 01:28:33 -07:00
