Hansung Kim
4566f954ee
Update doc; move code out of copypaste block
2024-07-23 15:05:09 -07:00
Hansung Kim
37fd0c6200
Bump vortex
2024-07-19 16:39:32 -07:00
Hansung Kim
21baeae758
Separate read and write counter for smem
2024-07-02 14:52:58 -07:00
Hansung Kim
7aad800a2d
Fix module imports after rocket-chip bump
2024-06-27 17:17:27 -07:00
Hansung Kim
e1342e431c
Bump radiance
2024-06-26 14:28:31 -07:00
Hansung Kim
018167480d
Add access counter to smem banks
2024-06-26 14:28:31 -07:00
Hansung Kim
a66a8c1732
Remove NUM_FPU_BLOCKS=2 from radiance.mk
2024-06-26 14:28:31 -07:00
Richard Yan
74cd633246
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-20 01:45:18 -07:00
Richard Yan
5eb581c7e5
different sized gemminis
2024-06-20 01:45:14 -07:00
Hansung Kim
5a79d7ff79
Add new opcodes for tensor-core DMA
2024-06-12 09:52:59 -07:00
Richard Yan
5b4d34864f
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-12 02:24:20 -07:00
Richard Yan
19852693b7
dual core gemmini, unpeg gemmini size and smem width
2024-06-12 02:17:40 -07:00
Hansung Kim
1401c4a090
Separate out core id from tile id in TileParams
...
Create a new config key to distinguish number of cores from number of
total tiles (which can be different when there are Gemmini tiles).
It is important to give contiguous IDs for Vortex cores for the
cluter-wide barrier to work.
2024-06-11 17:13:51 -07:00
Hansung Kim
7ced63bd62
Remove clbus definition from RadianceCluster
...
Should be in conjunction with the rocket-chip change that defines clbus
in the base Cluster class.
2024-06-11 16:23:54 -07:00
Hansung Kim
a0bff40a87
Set correct static tileId for core and Gemmini tiles
...
Otherwise, in multiple cluster configs, tiles can have duplicate global
tileId which results in Diplomacy connection errors for interrupt nodes
(among other things).
2024-06-11 16:17:08 -07:00
Richard Yan
a8e35b1f5a
oopsie doopsie
2024-06-09 15:35:11 -07:00
Richard Yan
17756d5f53
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-06-09 15:26:07 -07:00
Richard Yan
3badd75473
framebuffer, shared memory key, etc
2024-06-09 15:05:31 -07:00
Hansung Kim
ca3fd8b515
Bump vortex with doc changes
2024-06-09 13:41:18 -07:00
Hansung Kim
98889ebad9
radiance.mk: Change back to NUM_CORES=2
2024-06-09 13:39:59 -07:00
Hansung Kim
3254ac3741
Doc changes
2024-06-09 13:39:53 -07:00
Hansung Kim
3e4a04351b
Enable GPR_DUPLICATED for simulation
2024-06-03 13:13:15 -07:00
Hansung Kim
c7e2cd2387
Bump vortex with dispatch_unit fix
2024-05-30 22:00:10 -07:00
Hansung Kim
503a3ff246
Bump vortex
2024-05-30 18:33:56 -07:00
Hansung Kim
3b08d5ca70
radiance.mk: Remove debug rules
2024-05-30 18:14:14 -07:00
Hansung Kim
091115bb90
Bump vortex
2024-05-29 17:06:27 -07:00
Hansung Kim
2c196bb9a0
Update generated dpu verilog for stalls
2024-05-29 16:22:24 -07:00
Hansung Kim
44bcca9319
radiance.mk: Differentiate verilog copy target by CONFIG
2024-05-29 16:21:40 -07:00
Hansung Kim
17886dc050
Implement proper stalls for dpu
2024-05-29 16:21:12 -07:00
Hansung Kim
ae573aeea1
radiance.mk: Copy over when content differs, not just newer
2024-05-29 15:04:33 -07:00
Hansung Kim
0f36e86f63
Change config to 1core/8warp/8thread
2024-05-29 13:36:03 -07:00
Hansung Kim
8e79e620cb
Bump vortex
2024-05-29 13:35:43 -07:00
Hansung Kim
d34c5836a8
Add chisel-generated verilog for dpu
2024-05-29 13:33:23 -07:00
Hansung Kim
4a43d0126d
Make dpu 2-stage
...
For debugging, need to revert.
2024-05-29 13:31:38 -07:00
Hansung Kim
8dd3994012
radiance.mk: Don't fail when fd not installed
2024-05-29 01:03:08 -07:00
Hansung Kim
98618d1483
radiance.mk: Add target that copies Vortex verilog sources
...
This works in conjunction with the common.mk fix that prevents
rebuilding Chipyard jar on every .sv file update.
2024-05-29 00:53:05 -07:00
Hansung Kim
40b27c9600
Fix test for DPU
2024-05-28 21:18:51 -07:00
Hansung Kim
793db0e29d
Add stall IO to dpu
2024-05-28 21:18:19 -07:00
Hansung Kim
907150e51c
Add accumulation to dpu
2024-05-28 18:40:47 -07:00
Hansung Kim
3b1ab4e10d
Write four-element dpu without accumulation
2024-05-28 18:27:56 -07:00
Hansung Kim
db889c5e22
Disable coalescer chiseltests
2024-05-28 16:43:02 -07:00
Hansung Kim
4dba0def01
Do proper recoding and boxing for FMA input
2024-05-28 16:41:44 -07:00
Hansung Kim
615815acf5
Add placeholder tensor core DPU module
2024-05-27 21:16:53 -07:00
Hansung Kim
387e05404e
Bump vortex
2024-05-27 18:31:51 -07:00
Hansung Kim
09d9d3c3f9
Bump vortex with multi-warp tensor core fix
2024-05-25 20:13:56 -07:00
Hansung Kim
114dd75f2f
Fix no-coalescer config by removing coreTagWidth from L1 config
...
coreTagWidth logic in WithVortexL1Banks doesn't work, because
VortexL1Key is defined before the CoalescerKey and therefore
WithVortexL1Banks fragment has no way of knowing if coalescer is
defined. Instead, figure out the core-side tag width within
VortexBankImp by querying the TL parameters.
The downside of this is that since VortexBankPassthrough's client node
no longer has a way of knowing the core tag width before the Diplomacy
phase, we need to set its sourceId bits as a fixed constant. A require
is in place to ensure no truncation of core-side's sourceId.
2024-05-25 15:08:45 -07:00
Hansung Kim
18e6a1f82d
Fix diplomacy import warning in coalescer
2024-05-25 12:41:57 -07:00
Hansung Kim
4b58958a8e
Bump vortex
2024-05-23 16:28:08 -07:00
Hansung Kim
047b5a33ee
Enable all-to-all unaligned smem by default
2024-05-16 20:11:06 -07:00
Hansung Kim
1bd4be301e
Fix double import error from diplomacy migration
2024-05-16 20:10:29 -07:00
