Hansung Kim
da54162241
tensor: Add FP16 parameter and expose to VX_core
2024-09-10 15:32:17 -07:00
Hansung Kim
fb973a51b6
core_wrapper: Only terminate when core 0 is finished; more slack time
2024-06-22 16:34:42 -07:00
Hansung Kim
86deaa8e07
Give some slack time for other cores to finish
2024-06-12 09:47:21 -07:00
Richard Yan
1833e8a176
Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl
2024-06-12 02:17:01 -07:00
Richard Yan
7947df8a6c
config change, move ucode
2024-06-12 02:15:08 -07:00
Hansung Kim
5218292b6f
core_wrapper: Use finished and !reset to determine termination
2024-06-11 16:28:05 -07:00
Richard Yan
67a13410fd
gate level sim changes
2024-06-09 15:15:01 -07:00
Richard Yan
d624b3e50a
store fencing, large smem, fix tensor core for firesim
2024-05-15 21:45:48 -07:00
Richard Yan
c9a3eaad79
accelerator cisc
2024-05-07 13:58:32 -07:00
Richard Yan
85213d2876
synthesizable design
2024-04-17 18:05:51 -07:00
Hansung Kim
7ae54bd280
Remove unused IO in core_wrapper
2024-04-13 17:13:39 -07:00
Richard Yan
41a79a03a4
parametrize memory interface in core wrapper and update config.vh
2024-04-09 19:55:06 -07:00
Hansung Kim
7f8abe99ff
Fix wrong multicore parametrization in wrapper
2024-03-17 18:23:09 -07:00
Hansung Kim
40e2888733
Connect core gbar signals in wrapper
2024-03-17 14:09:43 -07:00
Hansung Kim
010c4675ce
Fix undeclared mem_perf_if
2024-03-07 15:00:43 -08:00
Hansung Kim
4643edf3e9
Properly determine core finish
2024-01-26 14:23:52 -08:00
Hansung Kim
62171c0788
Change dmem/smem width to LSU lanes not core lanes
2024-01-04 01:34:24 -08:00
Hansung Kim
fd425f1cdf
Change smem bundles into flattened 1-D arrays
2024-01-04 00:52:56 -08:00
Hansung Kim
e6f6d4ea06
Change dmem bundles into flattened 1-D arrays
2024-01-04 00:37:59 -08:00
Hansung Kim
22f656fec1
Add ports for smem TL and connect to smem bus
2024-01-01 02:22:49 -08:00
Hansung Kim
b6cc0c285e
Remove unused tilelink ports in VX_core_wrapper
2024-01-01 01:09:55 -08:00
Hansung Kim
144521e19c
Expose smem ports at VX_core top
...
smem_unit stays inside the core, and the two separate buses to dcache
and smem are exposed at VX_core.
Currently core_wrapper ties req valid to 1'b0, stalling kernels that
reads from sharedmem.
2023-12-31 23:57:31 -08:00
Hansung Kim
99207c862c
Revert PutPartial -> PutFull spoofing
2023-11-19 17:48:38 -08:00
Hansung Kim
e2d4894343
Add missing valid bit check for write acks
2023-11-17 20:32:53 -08:00
Hansung Kim
bc71c126ef
Fix STORE HEAP trace print in verilog wrapper
2023-11-17 20:25:01 -08:00
Hansung Kim
faf5fe3838
Assert ready when write response is coming back
...
Since the core's response ready signal depends on response valid, but core does
not accept write ACKs, we need to manually assert ready when there is a valid
response coming in for a write regardless of the core's ready state (which would
be 0).
2023-11-17 19:08:32 -08:00
Hansung Kim
9651cc6bc5
Fix wrong dcache tag width in wrapper
...
Need to use DCACHE_NOSM_TAG_WIDTH instead of DCACHE_TAG_WIDTH; otherwise, the
`ASSIGN_VX_MEM_BUS_IF macro in VX_smem_unit.sv does assignment of packed structs
with different widths for the tag field, resulting in misaligned bit error.
This results in wrong memory addresses for the core requests.
2023-11-17 17:12:41 -08:00
Hansung Kim
e2d3d93dea
Properly initialize DCR in wrapper code
2023-11-16 17:59:57 -08:00
Hansung Kim
963c2765d9
Move force-include of gpu_pkg to non-cache modules
2023-11-15 22:02:44 -08:00
Hansung Kim
448a253af3
Add Verilog wrapper module for VX_core
2023-11-15 20:09:53 -08:00
