felsabbagh3
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dea271eb6b
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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469334f23e
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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6c52b3d09b
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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3b11e1d72f
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Cache Working on Mem Copy
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2020-03-08 01:55:15 -08:00 |
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felsabbagh3
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4ed62f1aad
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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felsabbagh3
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db11bf6990
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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felsabbagh3
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90d10f4b7d
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Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
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2c616d8201
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Got queue_ll to work by modifying when to update bypass
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2020-03-06 22:50:20 -08:00 |
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Blaise Tine
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abfd592fd2
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added unit_test
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2020-03-06 10:31:31 -05:00 |
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Blaise Tine
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730c36ef18
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added generic_queue_ll
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2020-03-05 10:43:15 -05:00 |
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Blaise Tine
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721d22ae86
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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2ed98a4764
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synthesis fixes
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2020-03-05 07:03:23 -05:00 |
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Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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7222cdd199
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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c257c0578e
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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a86a403ca9
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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aa1a0ee376
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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733d00aba9
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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e2e053ff7b
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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b150327ca9
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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8784b09b18
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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8c6284f627
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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f6cc05eaa2
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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