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wu-architecture
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287 Commits

Author SHA1 Message Date
Abraham Gonzalez
317e0db4fd Config finder make target (#1328) 
* Add config-finder make target

* Add recursive functionality

* Add config finder to CI

* Workaround bash argument limit failures
 2023-03-06 18:07:17 -08:00
Abraham Gonzalez
f7a39f80e7 Config finder make target (#1328) 
* Add config-finder make target

* Add recursive functionality

* Add config finder to CI

* Workaround bash argument limit failures
 2023-03-06 14:00:20 -08:00
joey0320
3a53dc60d0 Add ENABLE_VLSI_FLOW flag 2023-03-03 22:34:00 -08:00
abejgonzalez
fd62d9ec2d Fix sbt assembly (remove duplicate classes, fix conflicts) 2023-03-03 15:36:36 -08:00
abejgonzalez
df30b415f5 Remove SBT thin client | Build all with fat jars 2023-03-02 22:42:13 -08:00
joey0320
07b194e85a add disallowPackedArrays 2023-03-02 09:29:58 -08:00
joonho hwangbo
c0b270853b Remove Duplicate Compiler Flags (#1367) 
* Remove Duplicate Compiler Flags

* Cleanup & fixes for MultipleMMIO

* bump barstools

* Update common.mk

* Update common.mk

---------

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2023-03-01 23:44:05 -08:00
Abraham Gonzalez
632a7a9348 Merge pull request #1349 from ucb-bar/misc-improv 
Small build system improvements
 2023-02-16 11:40:55 -08:00
Abraham Gonzalez
df903f0cb6 Merge pull request #1342 from ucb-bar/remove-gen-collateral 
Remove gen-collateral when rebuilding
 2023-02-15 16:40:40 -08:00
abejgonzalez
959cca64d2 Fix make help 2023-02-15 14:26:33 -08:00
abejgonzalez
55950b61b9 Move sim_files creation after FIRTOOL | Have FIRTOOL delete collateral dir 2023-02-15 12:01:58 -08:00
joey0320
58a6e72528 rename OUT_DIR to GEN_COLLATERAL_DIR 2023-02-13 13:24:04 -08:00
joey0320
6cd46d3c73 fixes 2023-02-13 02:14:23 -08:00
joey0320
4d31ccf218 Remove gen-collateral when rebuilding 2023-02-12 20:36:09 -08:00
Harrison Liew
14dec6eb71 disallowPackedArrays still broken, but don't need it. Bump barstools. Remove redundanct conda reqs 2023-02-10 14:35:43 -08:00
Harrison Liew
e4b35f45fa Merge branch 'main' into new-hammer 2023-02-10 12:55:41 -08:00
abejgonzalez
d32b0575f4 Use order-only pre-req for output_dir | In run-binary-hex only hex-ify the bin if bin given args 2023-02-08 20:09:40 -08:00
Harrison Liew
2bfc6e1347 [skip ci] abandon sv2v, Genus happy with patched firtool 2023-02-08 19:00:26 -08:00
Harrison Liew
61d094e887 [skip ci] Add sv2v, sty. Fix Makefile rebuild. Using sv2v, but Yosys still fails. 2023-02-08 16:05:38 -08:00
abejgonzalez
efb4b7dcbf Fix barstools for 1.29.0 firtool 2023-02-06 12:32:36 -08:00
abejgonzalez
f51457cf39 More robust splitting of BB filelists | Missed pre-commit | Removed old conda.yaml 2023-02-06 12:31:39 -08:00
Harrison Liew
2680f552cf [skip ci] trying ENABLE_CUSTOM_FIRRTL_PASS=1 for Yosys, clarify init script for private tech plugins 2023-02-06 12:31:39 -08:00
joey0320
b02c44a0f3 Remove SRAM annotations when ENABLE_CUSTOM_FIRRTL_PASS is set 2023-02-06 12:29:29 -08:00
joey0320
9e8812d7fb Add python file to split top.bb.f & model.bb.f 2023-02-06 12:29:29 -08:00
Harrison Liew
22834faa1f top blackbox isolation hack, bump submodules 2023-02-06 12:29:29 -08:00
joey0320
045f3d7bc0 Fix common.mk && add makefile check as pre-commit hook 2023-01-14 15:38:43 -08:00
joey0320
c452999834 rename firtool->mfc | fix comments 2023-01-09 10:45:50 -08:00
joey0320
2269a70249 add back disable-annotation-* flags 2023-01-09 10:45:50 -08:00
joey0320
e8a5715206 update compile flags 2023-01-09 10:45:50 -08:00
joey0320
e8e0f3e902 Fix HARNESS_* to MODEL_* for consistence 2023-01-09 10:36:08 -08:00
joey0320
6da72d859b Low FIRRTL flow working 
Bump barstools to 06db605902
 2023-01-09 10:36:08 -08:00
joey0320
e91e1765bc rename stuff & put back split-mems.py 2023-01-09 10:36:04 -08:00
joey0320
80194c7dd6 wip 2023-01-09 10:34:27 -08:00
joey0320
744368d61f Misc fixes & comments 2023-01-09 10:34:27 -08:00
joey0320
b3dc1c6778 Delete split-mems-conf.py & use mems.conf generated from GenerateTopAndHarness 2023-01-09 10:34:27 -08:00
joonho hwangbo
a6f0259019 Update comment related to ENABLE_CUSTOM_FIRRTL_PASS 
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2023-01-09 10:34:27 -08:00
joey0320
053002b7af Add comments & misc fixes 2023-01-09 10:34:27 -08:00
joey0320
13ece01450 Support Chisel->SFC->Low FIRRTL->CFC->Verilog & Sim flow 2023-01-09 10:34:27 -08:00
joey0320
3f614e6749 WIP 2023-01-09 10:34:27 -08:00
joey0320
9035ccf824 Remove disallowPackedArray option from firtool compilation step 2023-01-09 10:34:27 -08:00
joey0320
7e745c2646 Fix FIRTOOL_MODEL_MOD_HRCHY_JSON to FIRTOOL_MDOEL_HRCHY_JSON 2023-01-09 10:34:27 -08:00
abejgonzalez
bd0b3e8f1d Update paths | Allow sed overrides 2023-01-09 10:33:41 -08:00
abejgonzalez
c472e22223 Update FPGA makefile | Reorg firtool args 2023-01-09 10:33:38 -08:00
abejgonzalez
9f2fd22cc0 Rename variables | Small fixes | Move out-srcs to new dir 2023-01-09 10:32:44 -08:00
abejgonzalez
a136bafabd Fix more CI 2023-01-09 10:27:49 -08:00
abejgonzalez
f9965d88b3 Fix .f's 2023-01-09 10:27:15 -08:00
abejgonzalez
f9b938ad55 Update all 2023-01-09 10:27:07 -08:00
abejgonzalez
e75b107cf3 Reorg + Cleanup 2023-01-09 10:26:22 -08:00
abejgonzalez
a384fa9d1d E2E RocketConfig compile in Verilator 2023-01-09 10:25:27 -08:00
abejgonzalez
ae05fe0de2 Closer [ci skip] 2023-01-09 10:24:46 -08:00