joonho hwangbo
a524adb1b9
Fix icenet-loopback clock and reset domain ( #1612 )
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* Fix
* Bump icenet
* revert icenet bump | fix harnessbinders
2023-10-06 08:34:15 -07:00
Jerry Zhao
adebd634b4
Fix Arty100T Verilog build ( #1608 )
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* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs
2023-09-27 13:03:37 +02:00
Jerry Zhao
7106200d9d
Fix HarnessClockInstantiatorEx doc reference
2023-09-20 11:46:42 -07:00
Jerry Zhao
9ab5067e35
Update docs on bringup sims
2023-09-20 11:44:43 -07:00
Jerry Zhao
57ee757016
Remove MultiClockHarnessAXIMem
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Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.
Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
2023-09-16 09:47:47 -07:00
abejgonzalez
284f276fbb
Remove Dromajo + documentation
2023-09-08 14:28:10 -07:00
Abraham Gonzalez
48dcce2204
Merge pull request #1588 from ucb-bar/cospike-integration
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Replace Dromajo FireSim bridge with Cospike
2023-09-05 11:58:07 -07:00
Jerry Zhao
bc10cdac35
Merge pull request #1595 from ucb-bar/bump-sifive-cache
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bump sifive cache
2023-09-05 09:48:28 -07:00
Jerry Zhao
8c55fef690
Merge pull request #1584 from ucb-bar/jerryz123-patch-1
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Clarify fragments in ChipLikeRocketConfigs.scala
2023-09-04 15:33:00 -07:00
joey0320
2c6a1c6580
bump sifive cache
2023-09-04 14:54:50 -07:00
abejgonzalez
5541582639
Bump Boom
2023-09-04 12:23:07 -07:00
abejgonzalez
8044b26dfe
Bump testchipip
2023-08-30 22:16:08 -07:00
abejgonzalez
44f042a152
Merge remote-tracking branch 'origin/main' into cospike-integration
2023-08-30 18:06:31 -07:00
abejgonzalez
a48746f113
Deprecate Dromajo in FireSim, use cospike
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Move Cospike to testchipip
2023-08-30 17:55:04 -07:00
abejgonzalez
c7f1fe220d
Enable precommit | Format files
2023-08-28 14:56:55 -07:00
Jerry Zhao
00cd8575ca
Clarify fragments in ChipLikeRocketConfigs.scala
2023-08-26 16:57:53 -07:00
Jerry Zhao
fae344e1c1
Merge pull request #1580 from ucb-bar/vcospike
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Support variable VLEN cosim
2023-08-22 17:51:03 -07:00
Jerry Zhao
886b6701a8
Support variable VLEN cosim
2023-08-22 14:55:05 -07:00
Jerry Zhao
5495d05aa0
Bump to latest rocket-chip
2023-08-22 11:28:57 -07:00
Jerry Zhao
ed96a11a26
Merge pull request #1576 from ucb-bar/rocket-async
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Fix asyncqueue depth in ChipLikeRocketConfig
2023-08-16 10:09:57 -07:00
Jerry Zhao
c9ed05057b
Merge pull request #1575 from ucb-bar/bumpspike
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Bump spike to latest
2023-08-15 17:02:07 -07:00
Jerry Zhao
453903dbc7
Fix asyncqueue depth in ChipLikeRocketConfig
2023-08-15 15:29:04 -07:00
Jerry Zhao
1655b12939
Bump spike to latest
2023-08-15 13:42:49 -07:00
joey0320
2b66c89769
bump testchipip
2023-08-15 11:49:18 -07:00
Jerry Zhao
c745cbc064
Merge pull request #1567 from ucb-bar/rcbump
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Bump rocket-chip
2023-07-31 16:34:46 -07:00
Jerry Zhao
57325448d3
Bump boom
2023-07-31 11:51:50 -07:00
Jerry Zhao
65ed3c162c
Bump testchipip/barstools
2023-07-31 10:15:56 -07:00
Jerry Zhao
f557730b98
Bump rocket-chip
2023-07-26 17:57:37 -07:00
Jerry Zhao
577b96ba8c
Merge pull request #1531 from ucb-bar/rcbump
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Bump to chisel3.6
2023-07-26 16:35:47 -07:00
Jerry Zhao
6716e99f46
Bump gemmini
2023-07-25 13:17:41 -07:00
Jerry Zhao
75c8a3250a
Bump gemmini/boom
2023-07-25 09:57:47 -07:00
Jerry Zhao
a612f401e2
Merge remote-tracking branch 'origin/main' into rcbump
2023-07-25 09:30:19 -07:00
Jerry Zhao
387b51ef95
Put ClockBinder Fragmenters in the correct clock domain
2023-07-20 10:12:40 -07:00
Jerry Zhao
dfb991770a
Fix FIFO-fixing
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Fragmenter infront of FIFO-fixer needs to track way too many source-Ids
2023-07-19 18:41:49 -07:00
Jerry Zhao
47faa5a605
Merge pull request #1530 from ucb-bar/bumpspike
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Bump spike | support M-mode only cosim
2023-07-14 11:26:53 -07:00
Jerry Zhao
4a1418dde2
Support m-mode only cospike
2023-07-12 18:33:50 -07:00
Jerry Zhao
fce7e4c5aa
Bump to latest spike
2023-07-12 18:33:49 -07:00
abejgonzalez
783084f0ca
Fix for modern CY
2023-07-12 16:24:04 -07:00
Sriram Sridhar
6f8041bf82
UPF Generation
2023-07-12 14:19:23 -07:00
Jerry Zhao
ef3409f87f
Merge remote-tracking branch 'origin/main' into rcbump
2023-07-09 23:31:16 -07:00
Jerry Zhao
8a931d9258
Merge branch 'main' into readd-better-peripherals
2023-07-09 18:23:30 -07:00
Jerry Zhao
16b7c14e4c
Bump testchipip
2023-07-09 15:22:04 -07:00
Jerry Zhao
984ea24650
Apply suggestions from code review
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Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com >
2023-07-05 14:57:10 -07:00
Jerry Zhao
fb31e53f78
Bump boom
2023-07-05 10:32:56 -07:00
Jerry Zhao
078bce1323
Bump to chisel3.6
2023-07-05 10:32:55 -07:00
Jerry Zhao
927d236d1f
Merge remote-tracking branch 'origin/main' into tetheredsim
2023-07-02 11:53:33 -07:00
joey0320
a88d69b603
Bump boom
2023-06-30 22:28:17 -07:00
Sagar Karandikar
a5ed6ea038
bump testchipip
2023-06-29 13:12:50 -07:00
-T.K.-
cbce5ffa56
FIX: fix SPI Flash base address
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Change to match the standardized memory map suggested [here](https://docs.google.com/presentation/d/18qrFsHImYO4OJEpl8oQ_g3m2dc6a2Q0LppnVxTX-19I/edit#slide=id.g1c27f282ad8_0_54 )
2023-06-20 15:20:19 -07:00
Jerry Zhao
879e13388b
Fix default WithSPIFlash tests
2023-06-20 10:24:48 -07:00
