joey0320
58a6e72528
rename OUT_DIR to GEN_COLLATERAL_DIR
2023-02-13 13:24:04 -08:00
joey0320
6cd46d3c73
fixes
2023-02-13 02:14:23 -08:00
Jerry Zhao
f0df5a9d83
Bump fpga-shells
2023-02-01 14:58:36 -08:00
Jerry Zhao
7780ed23bf
Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
2023-01-26 00:12:28 -08:00
abejgonzalez
c472e22223
Update FPGA makefile | Reorg firtool args
2023-01-09 10:33:38 -08:00
abejgonzalez
292cc753ce
Run pre-commit on all files
2022-12-21 15:59:46 -08:00
Abraham Gonzalez
8e851b0285
Merge pull request #1278 from Lorilandly/vc707fpga
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Add support for VC707 FPGA board changelog:added
2022-12-14 19:16:49 -08:00
Haoan Li
dab5720445
expose functional pins and ports
2022-12-13 16:53:31 +09:00
-T.K.-
1b7457d2fc
FIX: fix Arty FPGA reset signal ( #1257 )
2022-12-07 19:34:35 -08:00
Lori Li
0724431873
Clean up code
2022-11-30 16:56:09 +09:00
Lori Li
a2d1f16488
revert module imp && fix for 4gb ram
2022-11-30 03:51:56 +09:00
Haoan Li
37f2578f6c
Bump fpga-shells version
2022-11-24 16:18:03 +09:00
Haoan Li
fb793d7ee9
Add support for VC707 fpga board
2022-11-24 16:08:15 +09:00
Jerry Zhao
04e80a6984
Bump rocketchip to latest, chisel to 3.5.2
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Remove fork of BusTopologies from rocket-chip
Update generators/chipyard/src/main/scala/config/AbstractConfig.scala
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com >
2022-09-16 15:17:30 -07:00
Abraham Gonzalez
af78c9cadf
Remove extra spaces in FPGA makefile
2022-03-02 15:45:27 +01:00
James Dunn
8e59db02fd
Merge pull request #968 from duyhieubui/master
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Fixes UART portmap for Arty.
2021-10-13 13:25:10 -07:00
Jerry Zhao
f668ffdb03
Switch PRCI to HarnessBinder/IOBinders
2021-09-29 11:39:52 -07:00
Duy-Hieu Bui
d9858c1dc8
Fixes UART portmap for Arty.
2021-09-03 05:02:36 +07:00
Tingyuan LIANG
d06abdb419
Swap two arguments to resolve bug
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**Related issue**: N/A
**Type of change**: bug fix
**Impact**: other
**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](d4b3878e4f/xilinx/common/tcl/prologue.tcl
2021-08-12 23:22:41 +08:00
abejgonzalez
16cdc88c52
Small comment + org. fix | Remove extra mkdirs
2021-05-12 16:42:05 -07:00
abejgonzalez
2874c98802
Add sim_files.f to fpga
2021-05-06 22:11:58 -07:00
Abraham Gonzalez
985faa4c8e
Small comment updates + cleanup
2021-04-03 12:55:27 -07:00
Abraham Gonzalez
be13781a1c
Set both MBUS/PBUS in configs | Add simple check for correct clocks
2021-04-02 16:43:59 -07:00
Abraham Gonzalez
5a41c5d9ac
Use multi-clock config. frags to determine VCU118 clk freq
2021-04-01 16:21:44 -07:00
Abraham Gonzalez
f334d5799f
Support 30MiB payloads - VCU118 FPGA
2021-04-01 16:21:16 -07:00
Jerry Zhao
ed2bfa8249
Don't pass JTAG oe signal off-chip ( #832 )
2021-03-24 01:08:46 -07:00
abejgonzalez
09ef82cabf
Update harnessClk/Rst naming to buildtop | Small docs cleanup
2021-03-22 13:11:12 -07:00
abejgonzalez
9957538d38
Enable support for pullup R's on GPIOs
2021-02-25 13:54:53 -08:00
abejgonzalez
4d3ff26a73
Bump testchipip
2021-01-04 15:36:00 -08:00
abejgonzalez
5099a96a7b
Bump fpga-shells (to sifive/master)
2020-12-28 16:09:34 -08:00
abejgonzalez
b797077334
Fix Arty documentation link
2020-12-27 22:00:06 -08:00
abejgonzalez
f1fdab5bd3
Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem
2020-11-23 16:58:34 -08:00
abejgonzalez
8f6de22e72
Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
2020-11-23 16:30:39 -08:00
abejgonzalez
661a7701a7
Share DigitalTop/ChipyardSystem | Fix small naming compile error
2020-11-23 15:46:03 -08:00
James Dunn
95e8365105
Small change to Arty reset binder name, per Jerry's PR comment.
2020-11-18 16:53:37 -08:00
abejgonzalez
d94a8efd43
Fix TLMemPort comment | Use Option instead of NoSimulator
2020-11-15 15:44:38 -08:00
abejgonzalez
c8add488ad
Reduce BOOM default freq. (play it safe)
2020-11-15 14:31:14 -08:00
abejgonzalez
f8bd8eaa27
Small fix to run_impl_bitstream
2020-11-12 16:24:10 -08:00
abejgonzalez
1b4826ad82
Generalize debug-bitstream
2020-11-12 16:20:22 -08:00
abejgonzalez
d4d989ce0f
Rename make target to bitstream | Delete unused make stuff / tcl
2020-11-12 15:41:05 -08:00
abejgonzalez
55f19f79d3
Address fpga srcs
2020-11-12 15:39:29 -08:00
abejgonzalez
7ca3be236c
Bump bringup VCU118 | Ignore HTIF if no-debug module
2020-11-12 11:47:16 -08:00
abejgonzalez
082b230452
Add missing file
2020-11-08 17:51:21 -08:00
abejgonzalez
244205e2b4
Separate new sys_clk and ddr2 from TSI
2020-11-08 17:49:32 -08:00
Abraham Gonzalez
5a4cad0172
Merge pull request #6 from ucb-bar/local-fpga-support-docs
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Local fpga support docs
2020-11-06 21:03:15 -08:00
abejgonzalez
c5e8fecb5c
Small renaming and cleanup
2020-11-06 21:00:18 -08:00
Abraham Gonzalez
9144e3c706
Fix pin mappings for TSI DDR
2020-11-06 20:51:11 -08:00
James Dunn
98fcea7b57
Adding initial Arty documentation; will be expanded further.
2020-11-06 17:25:05 -08:00
abejgonzalez
7baa1341ee
Use 2nd system clock for TSI DDR | Small cleanups
2020-11-06 16:34:45 -08:00
abejgonzalez
6aae66c54f
Add TSI Host Widget
2020-11-06 15:50:28 -08:00
