Commit Graph

4998 Commits

Author SHA1 Message Date
Angie Wang
5574354f55 Fft changes (#17)
* modified CustomBundle to also apply on Int

* programmatic bundle should take T <: Data instead of Data

* turns out indexedElements doesn't synthesize

* had to change a bunch of files to get clk/pads compiling again with recent firrtl mods

* modified CustomBundle to also apply on Int

* programmatic bundle should take T <: Data instead of Data

* turns out indexedElements doesn't synthesize

* had to change a bunch of files to get clk/pads compiling again with recent firrtl mods

* clk phases should be less than divby amount

* make clkconstraint error more descriptive

* don't make custom*bundle final

* nevermind. bundles need to be final.

* turns out making the bundle non-final was ok...

* removed infertypes from clksrctransform. seems like it doesn't work @ low firrtl?
2017-04-02 03:49:49 -07:00
Ben Keller
25bf3f7e01 Update README with workaround for dependency issues 2017-03-24 10:16:39 -07:00
Ben Keller
27095a4450 Revert "Publish firrtl locally first, to make Chisel happy"
This reverts commit 5491173a0a.
2017-03-24 10:06:01 -07:00
Ben Keller
5491173a0a Publish firrtl locally first, to make Chisel happy 2017-03-23 17:27:49 -07:00
Stevo
f4a8715fa4 Combine generates, make it a trait (#11)
* [stevo]: combine generates, make it a trait

* [stevo]: add Generator ala rocket-chip, some other cleanup

* [stevo]: remove Generator, since that generates firrtl...

* [stevo]: still debugging

* [stevo]: okay i think it works now

* [stevo]: oops

* Refactor new generate code. Mostly just style stuff.
2017-03-22 14:37:26 -07:00
chick
2d7806ca79 I would like to take the scalatest version here back to 2.2.5 because it causes problems with IntelliJ right now.
I don't see any specific features of 3.0.0 that are being used here.
2017-03-16 11:48:53 -07:00
Adam Izraelevitz
35b325dc81 Update README.md with example invocation (#16) 2017-03-15 12:16:22 -07:00
Edward Wang
d039935642 Typo 2017-03-15 00:28:30 -07:00
Angie Wang
f7056f3529 Fft changes (#15)
* modified CustomBundle to also apply on Int

* programmatic bundle should take T <: Data instead of Data

* turns out indexedElements doesn't synthesize

* had to change a bunch of files to get clk/pads compiling again with recent firrtl mods
2017-03-14 23:59:57 -07:00
edwardcwang
164bf2152c RegInit is no longer in util (#14) 2017-03-14 23:24:31 -07:00
Adam Izraelevitz
4745d29912 Fix transforms for firrtl/#459 issue. (#13) 2017-03-14 23:00:49 -07:00
Adam Izraelevitz
e8dc1035bf Fix for firrtl issue 459, reworking annotation API 2017-03-13 11:08:58 -07:00
Angie Wang
f1c437f830 Add Pads + other utilities (#7)
[stevo]: adds a bunch of pad frame commits, as well as beginning work on clocking annotations and constraints


* start add io pads pass

* save progress adding yaml pad info

* saving some semi-presentable work -- parses yaml for pad templates and associates templates with ports

* added black boxes to the module; still need to hook up

* added supply pad yaml example; added option to not include pad for an IO, blackboxed that cat + bit extraction functions

* rewrite createbbs and some other parts of the transform

* finally got blackboxhelper to work -- seems there was a typo in the firrtl pass (?) have not connected them up properly in the padframe

* finished first version of pad transform; need to add bells and whistles + special case stuff

* made a bunch of changes in firrtl to shorthand things

* done with padframe for signals

* started major refactoring; first of pad yaml stuff

* forgot to update verilogTemplate -> verilog

* rename ParsePadYaml -> ChipPadsYaml; moved some stuff

* separated out stuff that describes pads i.e. direction, type, side

* forgot to update import for yamlhelpers

* trying to make the process of creating annotations more structured

* saving annotation helpers but prob better to switch to yaml

* saving changes -- reworking annotations

* fixing some bugs; properly annotated ports with pads

* annotate supply pads

* lesson (re)learned. cleaned up constants

* finished adding supply pads to pad frame; still need to generate io file

* also committing updated transform; still without io file

* big typo was causing pad verilog files not to be generated

* verilator passes with transform; had to fix verilog bb typo

* added unused pads; added more thorough tests + did visual inspection of output; made some port types more explicit

* renamed files/classes to be clearer

* started creating pad io template

* update spec so that transform order matters

* get rid of logger

* went around in circles with blackboxhelper + way to annotate

* finished adding + testing pad.io creation

* starting clkgen pass -- made model for asynchronously reset clk divider + wrappers for programmatic bundling

* temporarily locating albert's utility functions here

* saving work on clk constraints

* redid input config passing -- pass in tech directory instead; seems like getting clk sink, src, and relationship works

* not done; need to pause to do tapeout-y things. the clk gen pass gets all the clks and their sources, but i need to build a proper graph to handle clks coming out of muxes
2017-03-05 18:50:56 -08:00
Colin Schmidt
e09cbe5b7e Create readme
add a readme with a single pass some could write
2017-02-22 11:54:54 -08:00
Colin Schmidt
43f1a699ad Move passes from pfpmp to barstools. (#5)
* Move passes from pfpmp to barstools.

* add an app that does both the harness and top generation

This reduces the number of firrtl.compile calls

* Add the ability to read annotations file

This helps with chisel annotation integration
2017-02-21 11:11:33 -08:00
Angie Wang
d86dea58cf Tapeout (#4)
* remove outdated files

* pulled resetinverter from dsptools + setup repo

* fix some package names, misc. dsptools dependencies, typo in build.sbt, + circuitstate in resetinverter pass

* add more comprehensive gitignore + license back in

* create directory structure to match package structure

* change package names to barstools.tapeout

* settled on barstools.tapeout.transforms package

* make directory + build structure more amenable for multiple sub projects
2017-02-17 11:58:05 -08:00
Howard Mao
9987d8dbcd fix deprecation warnings 2017-02-08 11:29:31 -08:00
Howard Mao
adb8c80ab3 change up gitignore rules 2017-02-07 17:37:26 -08:00
Howard Mao
9ed41fc3dc fully switch to chisel3 2017-02-07 17:33:38 -08:00
Howard Mao
41f439a2c3 fix submodule URLs 2017-01-17 11:13:02 -08:00
Howard Mao
2ca0523c93 bumpd rocket-chip for fesvr change 2017-01-17 10:57:32 -08:00
Chick Markley
e21e50dd91 Merge pull request #2 from ucb-bar/option-alter-quibble
Change spec to show a better way to change options
2016-12-14 11:07:58 -08:00
Howard Mao
9215c82f14 update testchipip 2016-12-07 13:21:00 -08:00
Howard Mao
51b710e437 switch over to the correct branch of testchipip 2016-11-11 09:55:05 -08:00
Howard Mao
264befa5f3 bump testchipip again 2016-11-10 22:16:05 -08:00
Howard Mao
be3121b5f5 bump testchipip 2016-11-09 14:49:33 -08:00
Howard Mao
2398bb8f47 workaround chisel imports bug 2016-11-09 14:48:18 -08:00
Howard Mao
3949088d02 update submodules 2016-11-08 12:31:55 -08:00
Howard Mao
d22f0cab68 split verilator compilation into phases 2016-10-27 16:57:00 -07:00
Howard Mao
d87c8159a0 add part about running tests to README 2016-10-27 11:27:08 -07:00
Howard Mao
85c20ce236 update README for PWM changes 2016-10-27 11:04:21 -07:00
chick
4b6110f0f6 Change spec to show a better way to change options 2016-10-27 10:25:58 -07:00
Howard Mao
137e92f7a3 add section to README about adding submodules 2016-10-26 18:34:10 -07:00
Howard Mao
310db2c579 add tests for PWM 2016-10-26 11:56:59 -07:00
Howard Mao
905c9a14f6 have TL and AXI based PWM controllers 2016-10-26 11:53:13 -07:00
Howard Mao
a9e741fbce bump testchipip 2016-10-26 09:58:43 -07:00
Howard Mao
694884125a add README 2016-10-25 14:29:59 -07:00
Chick Markley
a1c7742a57 Add ExecutionOptionsManager
Taken from https://github.com/ucb-bar/firrtl
2016-10-25 11:46:35 -07:00
Howard Mao
6c115b4234 add verilator simulation 2016-10-25 11:38:00 -07:00
Howard Mao
9a09850dd2 document PWM example better 2016-10-25 11:36:11 -07:00
Jack
52e8b6b04a Add *.swp to .gitignore 2016-10-24 20:56:34 -07:00
Jack
08855aaa64 Add BSD License 2016-10-24 19:49:10 -07:00
Jack Koenig
618d6b5db3 Initial commit 2016-10-24 19:46:38 -07:00
Howard Mao
964992cb12 use TestDriver.v from rocket-chip instead of one from testchipip 2016-10-24 17:04:17 -07:00
Howard Mao
9a6f0f57e5 add vsim clean rule 2016-10-21 21:08:34 -07:00
Howard Mao
f6993880dd separate PWM and basic example into separate packages 2016-10-21 21:06:40 -07:00
Howard Mao
3b03ac15e0 add PWM example 2016-10-21 17:05:06 -07:00
Howard Mao
7074420aba initial commit 2016-10-21 16:03:26 -07:00