Commit Graph

102 Commits

Author SHA1 Message Date
abejgonzalez
999ae05bfe Address some docs, build.sbt, .gitmodules 2020-11-12 15:31:34 -08:00
abejgonzalez
7ca3be236c Bump bringup VCU118 | Ignore HTIF if no-debug module 2020-11-12 11:47:16 -08:00
abejgonzalez
fc8c5e4b30 Use HTTPS for submodules 2020-11-04 18:02:49 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
abejgonzalez
341a6cc48d Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp 2020-10-13 16:23:41 -07:00
abejgonzalez
5bbd865447 Add MMC Device section to the DTS 2020-10-13 16:18:00 -07:00
James Dunn
a8834c7766 First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build. 2020-09-02 12:48:44 -07:00
Zitao Fang
02a951703b Initialize riscv-sodor 2020-07-02 00:54:49 -07:00
abejgonzalez
ca3c557fe2 [dromajo] change dromajo url | small cleanup 2020-05-16 13:43:14 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
Abraham Gonzalez
d0bec3fba7 Ariane Integration (#448)
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile

* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore

* [firesim] bump

* [ci] add midas ariane tests

* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments

* [ci] remove references to local verilator install

* [verilator] update flags

* [verilator] minimal set of flags for ariane

* [ariane] bump ariane to master

* [ci] revert to 4.016 verilator

* [ci] install verilator to ci server | misc compile fixes

* [ci/make] add longer ci timeout | update when assert is added in verilator sim

* [firesim] bump for misc. updates

* [make/ci] cleanup makefile and remove firesim tests of it

* [docs/firesim] bump and clean docs

* [firesim] bump

* [ci] use remote verilator for midas tests

* [misc] cleanup built.sbt more

* [firesim] bump

* [misc] bump build.sbt patch for tutorials

* [firesim/ci] cleanup and bump firesim
2020-03-09 18:06:41 -07:00
Howard Mao
24fe57d447 use blackboxed SimDRAM instead of SimAXIMem 2020-03-02 20:49:20 -08:00
Nathan Pemberton
ccd6ecd418 Marhsal in chipyard (#415)
* Move firemarshal into chipyard (was in firesim)
2020-02-09 17:58:56 -08:00
Albert Ou
7059ac3f0f toolchains: Add libgloss replacement 2019-12-21 12:11:49 -08:00
alonamid
56770a1a4c Gemmini Integration (#356)
* gemmini submodule

* fix build.sbt

* firechip gemmini config

* bump gemmini

* bump gemmini

* bump gemmini

* fix hwacha typo

* start gemmini docs

* bump gemmini

* gemmini docs

* Update Gemmini RST. Add quick-build instructions to Gemmini RST

* start gemmini CI

* bump gemmini

* gemmini CI fixes

* bump gemmini

* fix simulator name in gemmini CI

* cleanup gemmini CI

* bump esp-isa-sim to include gemmini

* update gemmini docs

* [ci skip] fix gemmini docs typos

* Update Gemmini.rst

Add instructions on building Gemmini programs, or writing your own programs.

* Changed order of VCS and Verilator in Gemmini docs

* Remove "make your own tests" from Gemmini README

* bump gemmini

* try to fix midasexamples CI
2019-12-14 01:36:42 -08:00
Abraham Gonzalez
4ce531c531 add coremark and spec firemarshal workloads 2019-11-05 07:04:07 +00:00
Howard Mao
05af2f9a9c Fix tracegen target and add to CI 2019-10-21 09:55:40 -07:00
Nathan Pemberton
54d683114c Merge remote-tracking branch 'origin/dev' into addMarshal 2019-10-06 18:44:41 -04:00
John Wright
b31a06b01d Merge pull request #263 from ucb-bar/dev-asap7-demo
Bugfixes for ASAP7 demo:
* Reverts to Innovus 18.1
* Fixes GDS hacking scripts
2019-10-06 14:43:03 -07:00
Nathan Pemberton
8e8ce09ce9 Move qemu to chipyard from firesim 2019-10-04 19:04:08 -04:00
Harrison Liew
fcd48ad262 fix power straps 2019-10-03 19:36:00 -07:00
Albert Ou
2dc8c7c143 sha3: Update submodule URL
The original URL should still redirect.
2019-10-03 20:40:12 +00:00
Albert Ou
361a9bf1d8 toolchains: Flatten esp-tools submodule 2019-10-02 13:16:01 -07:00
Albert Ou
b4ed5eb61b toolchains: Optionally build riscv-openocd with a separate script 2019-10-02 13:16:01 -07:00
Albert Ou
2f1e5e994b toolchains: Flatten riscv-tools submodule
This allows individual components to be better maintained following the
deprecation of riscv-tools.  Eliminate non-essential submodules.

build-static-libfesvr.sh is no longer necessary since libfesvr.a is
built as part of the riscv-isa-sim build.

For simplicity, only riscv-gnu-toolchain is now pre-built instead of the
entirety of riscv-tools.
2019-10-02 13:14:05 -07:00
Harrison Liew
6179a91a29 some plumbing but still need to remove sram generator target for asap7 2019-09-19 22:50:05 -07:00
Howard Mao
2eeda43b93 make firrtl-interpreter a submodule instead of depending on external snapshot 2019-09-12 00:19:55 +08:00
Colin Schmidt
8e343dee04 Fix sha3 build-system dependency 2019-09-01 07:11:52 -07:00
Colin Schmidt
a494f88af0 Add sha3 repo and config, bump tools for xcustom fix 2019-08-25 08:22:41 -07:00
Paul Rigge
ee75c03875 Add dsptools. 2019-08-02 15:09:22 -07:00
abejgonzalez
87195152ab added .git to end of hammer-cad-plugins 2019-07-24 13:24:32 -07:00
Abraham Gonzalez
ce0806a371 Switch submodules to https 2019-07-24 10:51:40 -07:00
alonamid
a759d64926 Merge remote-tracking branch 'origin/dev' into toolchains2 2019-07-19 01:10:50 +00:00
alonamid
121c572d72 pr comments 2019-07-19 00:54:34 +00:00
alonamid
56488ab142 replace riscv-tools with rocket-tools 2019-07-16 12:10:17 -07:00
Jerry Zhao
6e790abdee Add hammer-cad-plugins submodule 2019-07-15 16:08:10 -07:00
Jerry Zhao
37241af1fc Add initial VLSI flow scripts 2019-07-10 16:08:06 -07:00
Howard Mao
65df55cf9d add InclusiveCache 2019-07-02 16:58:08 -07:00
David Biancolin
8700ff05e5 Merge remote-tracking branch 'origin/master' into firesim-integration 2019-06-28 04:53:18 +00:00
Bastian Koppelmann
5ef1d449aa gitmodules: now only use https instead of ssh
git submodule init --recursive --init would result in a public key error

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-05-31 17:30:10 +02:00
David Biancolin
c0d4e848ba WIP 2019-05-27 22:53:05 +00:00
Jerry Zhao
e0d1ba285d Add Hwacha config to example project 2019-04-23 16:20:23 -07:00
abejgonzalez
e9ed53424b add sifive blocks | add rebar configs for boom 2019-04-19 21:06:32 -07:00
abejgonzalez
d80acd8cf8 added boom and torture | added csmith 2019-04-15 10:17:42 -07:00
alonamid
6ccb3defc1 add toolchains 2019-03-12 14:30:38 -07:00
alonamid
2e7791a57d add chisel and firrtl submodules 2019-03-12 14:30:38 -07:00
alonamid
2def0dfea7 change dir structure 2019-03-12 14:30:38 -07:00
Paul Rigge
0de9d396b4 Update gitmodule url to use https
The .git suffix was dropped and git@ was used instead of https://

Update to be consistent with other submodules.
2019-02-19 10:48:23 -08:00
John Wright
acd76e5410 Adding barstools to separate the top from harness and to generate the
memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00