Jerry Zhao
309cbe9792
Merge pull request #1880 from ucb-bar/classpath_fixes
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Fix classpath_cache bug
2024-05-16 15:12:07 -07:00
Jerry Zhao
3cf3d815dc
Rename fpga_platforms to chipyard_fpga
2024-05-16 09:53:48 -07:00
Jerry Zhao
39092e9b00
Switch RTL-sim/FPGA/VLSI flows to chisel6
2024-05-13 12:48:06 -07:00
Jerry Zhao
0ccd032a73
Remove references to legacy softcore-based bringup
2024-01-29 07:57:36 -08:00
Jerry Zhao
7c13574769
Rename cache/blocks submodules to match new chipsalliance ownership
2024-01-05 10:42:00 -08:00
-T.K.-
e078fcba49
REFACTOR: rename arty35t explicitly
2023-12-04 01:54:59 -08:00
Vladimir Milovanović
3d96cf5bc9
Adds initial Nexys Video board support.
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Co-authored-by: pznikola <p.z.nikola@etf.rs >
2023-10-05 23:01:29 +02:00
Jerry Zhao
66e4448008
Merge remote-tracking branch 'origin/main' into bringup2
2023-02-28 16:19:14 -08:00
joey0320
8e87a450b6
fpga makefile clean fix
2023-02-22 10:19:05 -08:00
joey0320
32dfc6fbf0
fixes
2023-02-21 21:52:03 -08:00
Abraham Gonzalez
632a7a9348
Merge pull request #1349 from ucb-bar/misc-improv
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Small build system improvements
2023-02-16 11:40:55 -08:00
abejgonzalez
85fe061244
Use EICG_wrapper model as addResource/Path | Fix Makefile parsing
2023-02-15 14:19:55 -08:00
abejgonzalez
55950b61b9
Move sim_files creation after FIRTOOL | Have FIRTOOL delete collateral dir
2023-02-15 12:01:58 -08:00
Jerry Zhao
61cc18749a
Fix more bugs with arty100t
2023-02-14 17:15:44 -08:00
Jerry Zhao
85fa9d1120
Add ARTY100t bringup + TSI-over-UART
2023-02-14 15:01:52 -08:00
joey0320
58a6e72528
rename OUT_DIR to GEN_COLLATERAL_DIR
2023-02-13 13:24:04 -08:00
joey0320
6cd46d3c73
fixes
2023-02-13 02:14:23 -08:00
abejgonzalez
c472e22223
Update FPGA makefile | Reorg firtool args
2023-01-09 10:33:38 -08:00
Haoan Li
37f2578f6c
Bump fpga-shells version
2022-11-24 16:18:03 +09:00
Haoan Li
fb793d7ee9
Add support for VC707 fpga board
2022-11-24 16:08:15 +09:00
Abraham Gonzalez
af78c9cadf
Remove extra spaces in FPGA makefile
2022-03-02 15:45:27 +01:00
Tingyuan LIANG
d06abdb419
Swap two arguments to resolve bug
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**Related issue**: N/A
**Type of change**: bug fix
**Impact**: other
**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](d4b3878e4f/xilinx/common/tcl/prologue.tcl
2021-08-12 23:22:41 +08:00
abejgonzalez
16cdc88c52
Small comment + org. fix | Remove extra mkdirs
2021-05-12 16:42:05 -07:00
abejgonzalez
2874c98802
Add sim_files.f to fpga
2021-05-06 22:11:58 -07:00
abejgonzalez
1b4826ad82
Generalize debug-bitstream
2020-11-12 16:20:22 -08:00
abejgonzalez
d4d989ce0f
Rename make target to bitstream | Delete unused make stuff / tcl
2020-11-12 15:41:05 -08:00
abejgonzalez
a281869041
Fix Arty merge and errors from CY bump
2020-11-05 15:04:44 -08:00
abejgonzalez
356fa70c3c
Update fpga-shells submodule | Fix Arty Makefile lines
2020-11-05 11:16:17 -08:00
Abraham Gonzalez
0eca51ba4d
Reorganize into bringup/simple | Bump sifive-blocks
2020-10-27 12:57:34 -07:00
Abraham Gonzalez
db73cab164
Add BootROM | Fix ResetWrangler for DDR | Add scripts
2020-10-20 21:20:11 -07:00
Abraham Gonzalez
dd358f45ab
UART Working... Bumped to newer fpga-shells
2020-10-19 11:29:25 -07:00
abejgonzalez
7f387a254b
Working up until the MMC attachment
2020-10-14 23:09:49 -07:00
abejgonzalez
dcac9b79df
Basic working with UART
2020-10-14 16:15:10 -07:00
abejgonzalez
e98a0f172f
Connected UART nicely
2020-09-11 16:55:25 -07:00
abejgonzalez
56eead4053
NOT WORKING: VCU118 Commit
2020-09-08 17:04:56 -07:00
abejgonzalez
c49eef3224
Small cleanup to CY DigitalTop | Move E300 configs to unique folder
2020-09-07 15:26:30 -07:00
abejgonzalez
a8083aa570
First pass at fpga-shells with IOBinders
2020-09-07 11:48:27 -07:00
abejgonzalez
1fa1b6d57f
Small makefile cleanup
2020-09-04 19:03:26 -07:00
abejgonzalez
8eb807a2fd
Use DigitalTop in Platform | Use Chipyard BootRom
2020-09-04 18:56:32 -07:00
James Dunn
990362933d
Simple makefile variable fix to allow make mcs
2020-09-04 14:16:42 -07:00
abejgonzalez
5a885fdcfd
Delete old makefiles | Full switch to CY make system
2020-09-03 21:28:05 -07:00
abejgonzalez
0656c5da4f
First pass on using CY make system
2020-09-03 20:29:19 -07:00
