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d60dacf6ea2cbcf4dc9c174ec90b514fce4dbf3a
Commit Graph

92 Commits

Author SHA1 Message Date
Hansung Kim
d60dacf6ea Merge remote-tracking branch 'upstream/main' into graphics 2023-07-22 14:45:48 -07:00
Jerry Zhao
a486194d3d Merge branch 'main' into shuttle 2023-06-13 11:01:19 -07:00
Jerry Zhao
22889212db Add barf submodule 2023-06-12 16:46:39 -07:00
Jerry Zhao
4328041c25 Add shuttle core 2023-06-08 14:37:25 -07:00
Jerry Zhao
059f88a80d Add embench build support 2023-05-17 11:20:46 -07:00
Hansung Kim
c9762296ca Merge remote-tracking branch 'upstream/main' into graphics 2023-05-05 14:40:55 -07:00
Jerry Zhao
df2e5ad9dc Bump to latest rocket-chip/chisel3.5.6 2023-03-28 16:48:27 -07:00
Hansung Kim
37dfdc0867 Merge remote-tracking branch 'upstream/main' into graphics 2023-03-25 12:30:51 -07:00
Harrison Liew
9ef3001ce1 Remove Cadence & Synopsys plugins (#1410) 
* remove Cadence & Synopsys plugins from docs and scripts

* update conda-locks
 2023-03-21 09:34:38 -07:00
Hansung Kim
83836d77c5 Merge remote-tracking branch 'upstream/main' into graphics 2023-03-08 13:58:50 -08:00
abejgonzalez
e744f7a20b Remove chisel-testers submodule 2023-03-03 16:50:05 -08:00
Hansung Kim
1c8da2ab7e Update rocket-chip module to 'graphics' 2023-02-19 22:05:42 -08:00
Harrison Liew
22fda3a6a7 initial migration to new Hammer 2023-02-06 12:29:29 -08:00
joonho hwangbo
33f5040b5d Integrate Mempress memory tester (#1253) 2022-10-17 18:41:39 -07:00
Jerry Zhao
af0cef485a Initial integration 2022-09-22 11:49:28 -07:00
Abraham Gonzalez
d7990e5639 Merge remote-tracking branch 'origin/main' into conda 2022-09-03 14:31:24 +00:00
Abraham Gonzalez
88ff36852d Build Spike/Pk/Tests/Libgloss from src 2022-08-29 22:52:21 +00:00
Abraham Gonzalez
58529f0ae0 Update reqs | Remove toolchains 2022-08-29 17:16:48 +00:00
Abraham Gonzalez
3c2bbd4bfd Address PR comments 2022-08-23 00:58:30 +00:00
abejgonzalez
1de35a6af4 Use conda + Update initial setup docs 2022-08-23 00:44:21 +00:00
michael-etzkorn
439ba9731e Update SiFive submodules to CHIPS fork 2022-08-14 12:21:45 -05:00
Jerry Zhao
f6d8beed75 Don't shallow clone submodules (revert #1064) 2022-03-18 12:21:24 -07:00
Jerry Zhao
349664d9e3 Switch to shallow clone for all submodules 2022-02-15 16:31:52 -08:00
abejgonzalez
ffbd436ba7 Merge remote-tracking branch 'origin/dev' into chisel-3.5-published 2022-01-31 10:54:43 -08:00
Animesh Agrawal
1b18b0b9c8 Rename fft generator submodule for consistency 2022-01-24 16:14:00 -08:00
Animesh Agrawal
beaf37f30e Use https for submodule path instead of ssh 2022-01-24 16:14:00 -08:00
Animesh Agrawal
c0f5c77520 Added FFT Generator integration 2022-01-24 16:14:00 -08:00
abejgonzalez
cd0d194ba6 Update rocketchip 2022-01-17 16:12:22 -08:00
abejgonzalez
70202eb9df Use temp. rocket-chip to get past elaboration 2022-01-17 15:19:00 -08:00
David Biancolin
6f8a199cf0 Remove chisel3, firrtl. firrt-intp, treadle submodules 2021-12-07 04:58:54 +00:00
Ella Schwarz
665ff79bb2 List supported configs 
Address PR comments
 2021-11-21 19:27:38 -08:00
Ella Schwarz
bb7d4eb5ec Add ibex-wrapper module 2021-11-21 19:27:38 -08:00
chick
6677616e12 - Add submodules 
- api-config-chipsalliance
  - rocket-dsp-utils
- update check-commit.sh to include rocket-dsp-utils
- changes to build.sbt
  - change rocket-dsptools to rocket-dp-utils
  - add api-config-chipsalliance
 2021-06-08 13:05:53 -07:00
Abraham Gonzalez
d1d7bb8f52 Merge pull request #747 from ucb-bar/local-fpga-support 
Local FPGA Support - Arty/VCU118
 2021-01-08 17:51:57 -08:00
abejgonzalez
5505aef30f Bump sifive-blocks 2021-01-08 10:56:30 -08:00
abejgonzalez
2e1aba653a Bump chisel-testers back to freechipsproject 2020-12-29 11:04:07 -08:00
abejgonzalez
5099a96a7b Bump fpga-shells (to sifive/master) 2020-12-28 16:09:34 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
abejgonzalez
d4d483c081 Bump BOOM | Use ucb-bar fork chisel-testers 2020-12-11 10:19:02 -08:00
abejgonzalez
571e7517eb Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral 2020-11-19 20:06:28 -08:00
abejgonzalez
999ae05bfe Address some docs, build.sbt, .gitmodules 2020-11-12 15:31:34 -08:00
abejgonzalez
7ca3be236c Bump bringup VCU118 | Ignore HTIF if no-debug module 2020-11-12 11:47:16 -08:00
abejgonzalez
fc8c5e4b30 Use HTTPS for submodules 2020-11-04 18:02:49 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
abejgonzalez
341a6cc48d Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp 2020-10-13 16:23:41 -07:00
abejgonzalez
5bbd865447 Add MMC Device section to the DTS 2020-10-13 16:18:00 -07:00
James Dunn
a8834c7766 First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build. 2020-09-02 12:48:44 -07:00
Zitao Fang
02a951703b Initialize riscv-sodor 2020-07-02 00:54:49 -07:00
abejgonzalez
ca3c557fe2 [dromajo] change dromajo url | small cleanup 2020-05-16 13:43:14 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505) 
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
 2020-05-16 12:22:30 -07:00