felsabbagh3
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8b81989bfd
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Before way logic change
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2019-11-08 18:16:40 -05:00 |
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Lyons, Ethan Tyler
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b0f685c2e2
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Add files via upload
ICache_In_Place
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2019-11-08 10:55:08 -05:00 |
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felsabbagh3
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bbb2373919
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Intrinsics: tests for TMC+Control Divergence
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2019-11-01 21:53:37 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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b3f464dd89
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Barriers impl + tested
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2019-10-22 01:47:39 -04:00 |
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felsabbagh3
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31d3d51392
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WSPAWN imp + tested
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2019-10-21 23:35:53 -04:00 |
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felsabbagh3
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85004899bd
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added reset to ws
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2019-10-21 12:03:07 -04:00 |
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felsabbagh3
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bab1852a99
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Added Split/Join - not tested
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2019-10-21 03:03:15 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
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629ed3f8f9
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Before ISA2.0
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2019-10-18 04:15:34 -04:00 |
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felsabbagh3
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559c64cb36
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Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
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505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
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b08297eafb
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minor
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2019-10-17 11:04:06 -04:00 |
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felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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1b25b10644
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Full Evaluation Attempt 1
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2019-09-11 01:39:00 -04:00 |
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felsabbagh3
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8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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felsabbagh3
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ad45758a35
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Before Fetch->FE
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2019-09-08 18:09:11 -04:00 |
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felsabbagh3
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c310e7381f
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Icache interface
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2019-09-08 17:36:09 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
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2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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felsabbagh3
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b216da5a6a
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ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
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d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
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96dac5e1ce
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Warp + Context Aware Design - Global Stalling
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2019-05-08 16:32:49 -07:00 |
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felsabbagh3
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a6c13bc38c
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Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
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79356c7ab1
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Changed hierarchy + Identified private + public modules
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2019-05-07 23:45:05 -07:00 |
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felsabbagh3
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191ed73415
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Less expensive but slower fetch logic
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2019-05-05 22:55:47 -04:00 |
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felsabbagh3
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8c2ae97510
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1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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4aac33b298
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Using verilog For-loops + Passing all tests
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2019-03-30 22:55:13 -04:00 |
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felsabbagh3
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52a839f84d
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Using verilog For-loops + Passing all tests
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2019-03-30 22:14:44 -04:00 |
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felsabbagh3
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99a0792a0c
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Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
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d02c3d25b7
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sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
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68f3ba84e5
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Added HW threads - Infinite loop + fixed valid
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2019-03-27 03:53:59 -04:00 |
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felsabbagh3
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9b42e79dcf
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Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
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01d142c6e6
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rtl passing all tests
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2019-03-22 02:44:53 -04:00 |
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felsabbagh3
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d08d389177
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Started on rtl (Finished till decode)
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2019-03-21 02:23:10 -04:00 |
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