wgulian3
f126a23114
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
wgulian3
123fb17723
Remove VX_define.h and *_synth and runtime/config.h
2020-03-26 04:07:17 -04:00
Blaise Tine
07c52d8729
code refactoring
2020-03-26 03:20:46 -04:00
Blaise Tine
bf3d1fb5a2
code refactoring
2020-03-26 01:41:01 -04:00
felsabbagh3
5372c07b01
Fixed most of the cache issues, mat_add left
2020-03-22 15:59:45 -07:00
felsabbagh3
82ea79c680
Fix for Single-Threaded
2020-03-22 14:44:46 -07:00
wgulian3
10ebfd7e24
Add threaded -O3 build mode
2020-03-21 17:23:40 -04:00
wgulian3
f565d47844
revert saxpy change and fix stage_1_cycles not working
2020-03-20 04:49:02 -04:00
wgulian3
5b3df797a4
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
felsabbagh3
ff2fc5fa43
Fixed no L3 Verilator issues
2020-03-13 15:11:20 -07:00
felsabbagh3
0f5528a229
Removed L3 for synthesis
2020-03-13 15:01:46 -07:00
wgulian3
07ed4085ae
Add power analysis Make target
2020-03-12 13:14:50 -04:00
wgulian3
c5fe43724e
replace procedural continuous assignments and force MLAB inference for generic_queue_ll
2020-03-10 17:46:48 -04:00
wgulian3
a931b588c2
minor tweaks to appease quartus
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re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
2020-03-10 12:15:30 -04:00
felsabbagh3
ca62e57a0d
L3 and CLUSTRING WORKS
2020-03-10 02:41:47 -07:00
felsabbagh3
dea271eb6b
Fixed Stall Pipeline Logic
2020-03-09 22:08:46 -07:00
felsabbagh3
469334f23e
MULTICORE WITH L2 WORKING
2020-03-09 01:17:11 -07:00
felsabbagh3
24f20a2da4
Added Vortex SOC
2020-03-08 15:24:21 -07:00
felsabbagh3
6c52b3d09b
Added Shared Memory
2020-03-08 15:00:53 -07:00
felsabbagh3
ec1aad1591
Icache stage mods + removed shared memory
2020-03-08 14:04:55 -07:00
felsabbagh3
f315a8a44d
Icache working
2020-03-08 13:59:35 -07:00
felsabbagh3
3b11e1d72f
Cache Working on Mem Copy
2020-03-08 01:55:15 -08:00
felsabbagh3
4ed62f1aad
Fixed all Cache Warnings
2020-03-07 14:34:05 -08:00
Blaise Tine
ddafe96ca6
fixed write logic in generic_queue_ll
2020-03-07 06:56:11 -05:00
felsabbagh3
db11bf6990
Made the cache module configurable for multi-instantiation
2020-03-07 00:49:40 -08:00
felsabbagh3
90d10f4b7d
Added Lower Level Cache Hit Queue
2020-03-06 23:04:42 -08:00
felsabbagh3
2c616d8201
Got queue_ll to work by modifying when to update bypass
2020-03-06 22:50:20 -08:00
Blaise Tine
abfd592fd2
added unit_test
2020-03-06 10:31:31 -05:00
Blaise Tine
730c36ef18
added generic_queue_ll
2020-03-05 10:43:15 -05:00
Blaise Tine
721d22ae86
synthesis fixes
2020-03-05 09:11:43 -05:00
Blaise Tine
2ed98a4764
synthesis fixes
2020-03-05 07:03:23 -05:00
Blaise Tine
369c2c625c
synthesis fixes
2020-03-05 06:58:51 -05:00
felsabbagh3
7222cdd199
Added Snoop Invalidate/Writeback Req type
2020-03-05 01:30:16 -08:00
felsabbagh3
c257c0578e
Added fill_invalidator
2020-03-04 23:55:02 -08:00
felsabbagh3
a86a403ca9
New Cache Design Passing All Tests
2020-03-04 23:24:32 -08:00
felsabbagh3
aa1a0ee376
Passing some cases
2020-03-04 04:05:54 -08:00
felsabbagh3
d8e25045be
Added All Interfaces
2020-03-03 22:48:49 -08:00
felsabbagh3
01ae6ffafe
Added Core Interface
2020-03-03 22:14:56 -08:00
felsabbagh3
58db00f555
Fixed some other timing issues
2020-03-03 21:15:44 -08:00
felsabbagh3
25b6dbdfa8
Fixed incorrect valid and'ing in execute
2020-03-03 20:57:20 -08:00
felsabbagh3
733d00aba9
Finished cache, dram imp + interfaces left
2020-03-03 19:42:33 -08:00
felsabbagh3
e2e053ff7b
Fixed miss reserv to support ST->LD sequences
2020-03-03 17:04:39 -08:00
felsabbagh3
b150327ca9
Before fixing miss rsrv for ST->LD sequences
2020-03-03 16:57:05 -08:00
felsabbagh3
8784b09b18
Finished st0
2020-03-03 02:49:30 -08:00
felsabbagh3
8c6284f627
Connected cache to bank
2020-03-02 23:24:17 -08:00
felsabbagh3
f6cc05eaa2
Everything except bank internals
2020-03-02 23:08:54 -08:00
felsabbagh3
d78338c7d4
Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
2020-03-01 22:27:18 -08:00
felsabbagh3
f98f5c414d
+Added icache stage -- 3rd case of AUIPC os broken?
2020-03-01 18:01:02 -08:00
wgulian3
ca61801199
Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
2020-02-22 20:16:13 -05:00
wgulian3
a099cb25cf
Update multiply for not SYN_FUNC
2020-02-21 23:20:04 -05:00
