6 Commits

Author	SHA1	Message	Date
CGH0S7	7ae5ee8c39	SystemVerilog Module Complete	2025-01-01 23:19:43 +08:00
CGH0S7	c5eba63085	Fix bugs in Sicore	2024-12-31 09:28:33 +08:00
CGH0S7	b4cb98d8a9	Add single cycle edition	2024-12-31 01:30:15 +08:00
CGH0S7	de44f7d8d3	Try to rebuild the core	2024-12-30 20:09:10 +08:00
CGH0S7	e8e6b6ddb3	Still need to fix	2024-12-30 00:36:45 +08:00
CGH0S7	66cda81233	Core Opimized	2024-12-28 08:39:07 +08:00