James Dunn
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95e8365105
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Small change to Arty reset binder name, per Jerry's PR comment.
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2020-11-18 16:53:37 -08:00 |
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abejgonzalez
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d94a8efd43
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Fix TLMemPort comment | Use Option instead of NoSimulator
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2020-11-15 15:44:38 -08:00 |
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abejgonzalez
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c8add488ad
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Reduce BOOM default freq. (play it safe)
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2020-11-15 14:31:14 -08:00 |
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abejgonzalez
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f8bd8eaa27
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Small fix to run_impl_bitstream
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2020-11-12 16:24:10 -08:00 |
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abejgonzalez
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1b4826ad82
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Generalize debug-bitstream
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2020-11-12 16:20:22 -08:00 |
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abejgonzalez
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d4d989ce0f
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Rename make target to bitstream | Delete unused make stuff / tcl
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2020-11-12 15:41:05 -08:00 |
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abejgonzalez
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55f19f79d3
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Address fpga srcs
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2020-11-12 15:39:29 -08:00 |
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abejgonzalez
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7ca3be236c
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Bump bringup VCU118 | Ignore HTIF if no-debug module
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2020-11-12 11:47:16 -08:00 |
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abejgonzalez
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082b230452
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Add missing file
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2020-11-08 17:51:21 -08:00 |
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abejgonzalez
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244205e2b4
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Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:49:32 -08:00 |
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Abraham Gonzalez
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5a4cad0172
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Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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abejgonzalez
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c5e8fecb5c
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Small renaming and cleanup
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2020-11-06 21:00:18 -08:00 |
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Abraham Gonzalez
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9144e3c706
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Fix pin mappings for TSI DDR
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2020-11-06 20:51:11 -08:00 |
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James Dunn
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98fcea7b57
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Adding initial Arty documentation; will be expanded further.
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2020-11-06 17:25:05 -08:00 |
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abejgonzalez
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7baa1341ee
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Use 2nd system clock for TSI DDR | Small cleanups
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2020-11-06 16:34:45 -08:00 |
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abejgonzalez
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6aae66c54f
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Add TSI Host Widget
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2020-11-06 15:50:28 -08:00 |
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Abraham Gonzalez
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b0eed5075f
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[temp] start integrating tsi host widget
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2020-11-06 10:57:55 -08:00 |
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abejgonzalez
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c721d897f3
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Point to SiFive license | Add require on Arty
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2020-11-06 10:18:10 -08:00 |
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abejgonzalez
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84508bee6e
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More FPGA prototyping docs
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2020-11-05 21:51:25 -08:00 |
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abejgonzalez
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313fa4f129
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Merge branch 'local-fpga-support' into local-fpga-support-docs
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2020-11-05 21:24:03 -08:00 |
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abejgonzalez
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b0fc0457aa
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Use Chipyard configs as base (Arty)
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2020-11-05 20:46:03 -08:00 |
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abejgonzalez
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9a5b67bf8c
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Use Chipyard configs as a base (VCU118)
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2020-11-05 20:30:49 -08:00 |
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abejgonzalez
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255e88fe8f
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Initial outline of FPGA prototyping docs
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2020-11-05 17:06:34 -08:00 |
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abejgonzalez
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083f34ab23
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Revert Chipyard system | Create new VCU118 Chipyard system
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2020-11-05 15:44:54 -08:00 |
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abejgonzalez
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a281869041
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Fix Arty merge and errors from CY bump
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2020-11-05 15:04:44 -08:00 |
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abejgonzalez
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a7ab0dab59
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Updated VCU118 | Bumped naming on Arty
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2020-11-05 13:59:10 -08:00 |
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abejgonzalez
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356fa70c3c
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Update fpga-shells submodule | Fix Arty Makefile lines
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2020-11-05 11:16:17 -08:00 |
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abejgonzalez
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3994bcecdf
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Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
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2020-11-05 11:08:36 -08:00 |
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Abraham Gonzalez
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0eca51ba4d
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Reorganize into bringup/simple | Bump sifive-blocks
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2020-10-27 12:57:34 -07:00 |
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Abraham Gonzalez
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3c42e2cae7
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Fixed BootROM | Updated HarnessBinders
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2020-10-26 18:15:58 -07:00 |
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Abraham Gonzalez
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db73cab164
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Add BootROM | Fix ResetWrangler for DDR | Add scripts
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2020-10-20 21:20:11 -07:00 |
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Abraham Gonzalez
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dd358f45ab
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UART Working... Bumped to newer fpga-shells
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2020-10-19 11:29:25 -07:00 |
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abejgonzalez
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9ba4918cb8
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Inject MMCDevice into TLSPI Node
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2020-10-15 11:46:42 -07:00 |
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abejgonzalez
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7f387a254b
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Working up until the MMC attachment
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2020-10-14 23:09:49 -07:00 |
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abejgonzalez
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dcac9b79df
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Basic working with UART
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2020-10-14 16:15:10 -07:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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abejgonzalez
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5bbd865447
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Add MMC Device section to the DTS
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2020-10-13 16:18:00 -07:00 |
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abejgonzalez
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8257775e96
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Connect DDR from harness
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2020-10-12 21:50:50 -07:00 |
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James Dunn
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895dcd6831
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referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue.
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2020-10-11 11:12:33 -07:00 |
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James Dunn
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dca56cd858
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Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.
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2020-10-10 19:55:02 -07:00 |
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James Dunn
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54acfe71fc
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Some HarnessBinder testing with Jerry's debug suggestions.
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2020-10-10 13:45:27 -07:00 |
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dunn
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7d1a1539e6
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Initial pass at HarnessBinders for Arty.
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2020-10-09 23:17:36 -07:00 |
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dunn
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252f9c6a12
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Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
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2020-10-07 11:55:16 -07:00 |
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James Dunn
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afc085a5f4
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Removed AON block from E300 design. Debug over JTAG still functioning.
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2020-10-04 18:13:47 -07:00 |
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James Dunn
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9135cda959
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Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
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2020-09-17 13:43:28 -07:00 |
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abejgonzalez
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f1b40d51af
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Connected clocks | Exposed Master TL port
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2020-09-15 12:58:58 -07:00 |
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abejgonzalez
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72c0f4b3d3
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Add GPIO Overlay
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2020-09-13 16:37:20 -07:00 |
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abejgonzalez
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69bf39bf13
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Added more overlays | Closer to bringup platform
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2020-09-12 18:18:13 -07:00 |
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abejgonzalez
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382e5f1ae8
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Add forgotten file
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2020-09-11 17:02:22 -07:00 |
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abejgonzalez
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e98a0f172f
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Connected UART nicely
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2020-09-11 16:55:25 -07:00 |
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