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1090 Commits

Author SHA1 Message Date
Jerry Zhao
6445233d8d Merge pull request #1657 from ucb-bar/artygpio 
Add Bringup on Arty100T config, using PMOD-gpio for ser-tl
 2023-11-19 13:45:18 -08:00
Jerry Zhao
1e2667e0bc Add LLC bufExterior comment 2023-11-16 22:06:34 -08:00
Jerry Zhao
ab4c4d809c Add LLC exterior buffer cfg fragment 2023-11-16 22:05:38 -08:00
Jerry Zhao
7c832415a8 Add cfg fragment to insert LLC interior buffers 2023-11-16 02:59:26 -08:00
Abraham Gonzalez
4132296831 Update TargetConfigs.scala 2023-11-15 16:49:19 -08:00
Jerry Zhao
b50d10418c Add RocketBoundaryBuffers fragment 2023-11-14 23:38:29 -08:00
Jerry Zhao
c90d054bb0 Merge pull request #1660 from ucb-bar/memsys_cfg 
Move memory system configs to a separate configs file
 2023-11-14 01:49:51 -08:00
Jerry Zhao
4495c611a8 Move memory system configs to a separate configs file 2023-11-12 12:30:24 -08:00
Jerry Zhao
f0edd18c32 Merge pull request #1636 from ucb-bar/flatchiptop_harness 
Support using HarnessBinders without IOBinders
 2023-11-09 22:18:34 -08:00
Jerry Zhao
1d6ebb230b Add Bringup on Arty100T config, using PMOD-gpio for ser-tl 2023-11-08 20:06:44 -08:00
Ethan Wu
70e78cb523 Fix IO direction for host Serial-TL port 
`cloneType` is a Chisel-internal method, use `chiselTypeOf` to construct
an IO of the same type and direction.
 2023-11-06 21:27:32 -08:00
abejgonzalez
cae6a8602a Merge remote-tracking branch 'origin/main' into caliptra-aes 2023-11-05 16:43:04 -08:00
abejgonzalez
19fda05fba Revert GCD BB changes | Move GCD to 0x4000 to not conflict w/ bootrom 2023-11-03 14:52:01 -07:00
Abraham Gonzalez
d7f78ba2e4 Merge branch 'main' into bb-fixes 2023-11-03 11:46:49 -07:00
Abraham Gonzalez
9d917d65d0 Merge branch 'main' into caliptra-aes 2023-11-02 21:09:16 -07:00
abejgonzalez
7525b9fd04 Fix CI | Fix Verilator compile 2023-11-02 17:27:42 -07:00
abejgonzalez
0c1ca5750e Add fixes | Bump to 256b SBUS 2023-11-02 17:09:00 -07:00
Jerry Zhao
2ac2cb38b4 Merge remote-tracking branch 'origin/main' into change-reset-vector 2023-11-02 12:40:51 -07:00
abejgonzalez
10b5fbc21a Add Caliptra AES256 ECB engine as RoCC accelerator 2023-11-02 12:01:38 -07:00
abejgonzalez
42eb570fd8 BUGGY COMMIT: Shows MFC issue with multiple same bb paths 2023-11-01 12:17:03 -07:00
-T.K.-
d96629c6f1 ADD: bump testchipip 2023-11-01 11:45:50 -07:00
Jerry Zhao
ac271dc3eb Merge pull request #1603 from ucb-bar/jerryz123-patch-3 
Add NarrowRocketCache config fragment
 2023-10-31 14:48:48 -07:00
Jerry Zhao
88a33be7e5 Respect DontTouchChipTopPorts key 2023-10-31 08:32:03 -07:00
Jerry Zhao
3fa3d745b9 Support breaking out ChipTop I/O out of the expected bundle type 2023-10-30 21:25:11 -07:00
Jerry Zhao
a5597fd32f Support using HarnessBinders without IOBinders 2023-10-25 11:49:16 -07:00
Jerry Zhao
6bd2e9dddb [ci skip] Re-add suggestName for axi4 mmio mem 2023-10-13 17:36:41 -07:00
Jerry Zhao
deab3b11b6 Fix UARTAdapter div bits 2023-10-12 15:37:03 -07:00
Jerry Zhao
3cbcf6b6e8 Fix TSIBridge loadmem param 2023-10-11 15:01:39 -07:00
Jerry Zhao
894ee63061 Make chipParameters not private 2023-10-11 14:59:49 -07:00
Jerry Zhao
8ecd7bfa89 Merge remote-tracking branch 'origin/main' into port_api 2023-10-09 11:18:00 -07:00
Jerry Zhao
8d11dde7cb Fix UARTPort freqMHz 2023-10-07 00:27:15 -07:00
Jerry Zhao
b949324d5a Fix FireSim UARTBridge 2023-10-06 17:55:14 -07:00
Jerry Zhao
a4cb114657 Fix UARTAdapter divisor 2023-10-06 17:00:06 -07:00
joonho hwangbo
a524adb1b9 Fix icenet-loopback clock and reset domain (#1612) 
* Fix

* Bump icenet

* revert icenet bump | fix harnessbinders
 2023-10-06 08:34:15 -07:00
Jerry Zhao
e6203bb25c Fix fsim supernode memmodel 2023-10-05 23:56:29 -07:00
Jerry Zhao
8fb4ba5675 Fix UARTPort freqMHz 2023-10-05 21:03:34 -07:00
Jerry Zhao
eb3a0aecf4 Add PortAPI between IO and Harness blocks 2023-10-05 15:02:56 -07:00
-T.K.-
8fa8be5669 ADD: bump testchipip 2023-09-27 10:54:57 -07:00
Jerry Zhao
adebd634b4 Fix Arty100T Verilog build (#1608) 
* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs
 2023-09-27 13:03:37 +02:00
-T.K.-
f3c7ecf8ba REFACTOR: change bootaddr and reset vector address 2023-09-23 19:17:54 -07:00
Jerry Zhao
8c3a586c73 Add NarrowRocketCache config fragment 
For configs with wide SBUS, a narrow rocket cache is easier to PD, and does not incur any performance loss usually
 2023-09-20 15:53:13 -07:00
Jerry Zhao
7106200d9d Fix HarnessClockInstantiatorEx doc reference 2023-09-20 11:46:42 -07:00
Jerry Zhao
9ab5067e35 Update docs on bringup sims 2023-09-20 11:44:43 -07:00
Jerry Zhao
57ee757016 Remove MultiClockHarnessAXIMem 
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.

Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
 2023-09-16 09:47:47 -07:00
abejgonzalez
284f276fbb Remove Dromajo + documentation 2023-09-08 14:28:10 -07:00
Abraham Gonzalez
48dcce2204 Merge pull request #1588 from ucb-bar/cospike-integration 
Replace Dromajo FireSim bridge with Cospike
 2023-09-05 11:58:07 -07:00
Jerry Zhao
bc10cdac35 Merge pull request #1595 from ucb-bar/bump-sifive-cache 
bump sifive cache
 2023-09-05 09:48:28 -07:00
Jerry Zhao
8c55fef690 Merge pull request #1584 from ucb-bar/jerryz123-patch-1 
Clarify fragments in ChipLikeRocketConfigs.scala
 2023-09-04 15:33:00 -07:00
joey0320
2c6a1c6580 bump sifive cache 2023-09-04 14:54:50 -07:00
abejgonzalez
5541582639 Bump Boom 2023-09-04 12:23:07 -07:00