felsabbagh3
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9bf186fc77
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minor
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2019-10-17 11:51:11 -04:00 |
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felsabbagh3
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e8a43fa7a9
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minor
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2019-10-17 11:44:19 -04:00 |
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felsabbagh3
|
10fbb53c38
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minor
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2019-10-17 11:29:40 -04:00 |
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felsabbagh3
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33e20a2d80
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minor
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2019-10-17 11:25:29 -04:00 |
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felsabbagh3
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b08297eafb
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minor
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2019-10-17 11:04:06 -04:00 |
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felsabbagh3
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7fd5312b67
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minor
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2019-10-17 10:50:36 -04:00 |
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felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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felsabbagh3
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22f02820cf
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GPR back-end with mem
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2019-10-14 19:10:47 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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Lingjun Zhu
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f28cd286e6
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Implemented the GPR model with the CLN28HPC memory block
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2019-10-13 20:27:28 -04:00 |
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Lingjun Zhu
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d5dad1c442
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Updated the two-port GPR model
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2019-10-13 19:52:14 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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fb3bc60189
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Finalized GPR with 3-Port Structure
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2019-09-11 14:53:32 -04:00 |
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felsabbagh3
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1b25b10644
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Full Evaluation Attempt 1
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2019-09-11 01:39:00 -04:00 |
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felsabbagh3
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3c3a443bd5
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New RF with Evaluation
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2019-09-11 01:04:23 -04:00 |
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felsabbagh3
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8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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felsabbagh3
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4e8da1811a
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New GPR structure - Clone or WSPAWN
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2019-09-09 22:17:20 -04:00 |
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felsabbagh3
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1882147370
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GPR Wrapper Interface Done
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2019-09-09 14:04:07 -04:00 |
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felsabbagh3
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bce9bc443c
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GPR Wrapper in Decode
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2019-09-09 01:03:13 -04:00 |
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felsabbagh3
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ecf81336db
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Finished FE and BE high-level
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2019-09-08 19:28:53 -04:00 |
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felsabbagh3
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981bf0afe5
|
FE Done
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2019-09-08 18:36:47 -04:00 |
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felsabbagh3
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ad45758a35
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Before Fetch->FE
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2019-09-08 18:09:11 -04:00 |
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felsabbagh3
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c310e7381f
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Icache interface
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2019-09-08 17:36:09 -04:00 |
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felsabbagh3
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5e6804703f
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Decode in FE
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2019-09-08 17:24:51 -04:00 |
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felsabbagh3
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ac9b06bf7d
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Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
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2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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Hyesoon Kim
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6b3b124a30
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fix typo of std=c++11
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2019-06-12 07:32:20 -04:00 |
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felsabbagh3
|
9cd8ee8579
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Added std=c++11
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2019-06-11 23:21:48 -07:00 |
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felsabbagh3
|
1105261bbb
|
Updated Quartus paths
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2019-06-11 21:16:50 -07:00 |
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felsabbagh3
|
b216da5a6a
|
ram stdint + Quartus Files
|
2019-06-11 21:13:30 -07:00 |
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felsabbagh3
|
d7afef04a9
|
Sim Work miss
|
2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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8995267cd3
|
Added barriers
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2019-05-17 08:34:00 +04:00 |
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felsabbagh3
|
48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
|
96dac5e1ce
|
Warp + Context Aware Design - Global Stalling
|
2019-05-08 16:32:49 -07:00 |
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felsabbagh3
|
a6c13bc38c
|
Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
|
79356c7ab1
|
Changed hierarchy + Identified private + public modules
|
2019-05-07 23:45:05 -07:00 |
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felsabbagh3
|
191ed73415
|
Less expensive but slower fetch logic
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2019-05-05 22:55:47 -04:00 |
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felsabbagh3
|
f21eaec79f
|
Provisioned SM
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2019-04-05 19:25:54 -04:00 |
|
felsabbagh3
|
166b9ae48d
|
Before Scratchpad
|
2019-04-05 17:56:05 -04:00 |
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felsabbagh3
|
719ed25213
|
Cleanup
|
2019-03-31 16:30:37 -04:00 |
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felsabbagh3
|
8c2ae97510
|
1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
|
2019-03-31 05:02:55 -04:00 |
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felsabbagh3
|
4aac33b298
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:55:13 -04:00 |
|
felsabbagh3
|
52a839f84d
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:14:44 -04:00 |
|
felsabbagh3
|
a3a3b21de7
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:09:03 -04:00 |
|
felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
|
2019-03-30 03:54:20 -04:00 |
|
felsabbagh3
|
d02c3d25b7
|
sync
|
2019-03-27 13:52:13 -04:00 |
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felsabbagh3
|
68f3ba84e5
|
Added HW threads - Infinite loop + fixed valid
|
2019-03-27 03:53:59 -04:00 |
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