Jerry Zhao
4d928c3c14
Rename timeout_cycles to TIMEOUT_CYCLES to match convention
2023-12-18 13:47:48 -08:00
Nayiri
42622919cd
fixing macro paths for yosys with circt generated verilog [skip ci]
2023-12-14 18:02:32 -08:00
abejgonzalez
088e9ea45a
Remove references to ENABLE_YOSYS
2023-12-13 10:07:14 -08:00
Nayiri
700057d9eb
changed chiptop dut name, set FSDB=1 when needed
2023-11-13 13:33:24 -08:00
Jerry Zhao
77ee5906e2
[vlsi][ci skip] Fix INPUT_CONFS override in tutorial.mk
2023-10-19 11:19:56 -07:00
Jerry Zhao
e148a32e6b
Merge pull request #1514 from ucb-bar/klayout-docs
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KLayout section of Sky130+OpenROAD tutorial
2023-09-05 11:41:09 -07:00
abejgonzalez
c7f1fe220d
Enable precommit | Format files
2023-08-28 14:56:55 -07:00
Jerry Zhao
6f90102770
Merge branch 'main' into klayout-docs
2023-07-10 09:21:18 -07:00
Nayiri K
222059941e
renamed clock_clock to clock_uncore_clock
2023-06-30 15:04:38 -07:00
Nayiri K
dcaca02e14
small fixes for sim yaml generation
2023-06-30 15:04:04 -07:00
Nayiri K
5f54876de2
PREPROC_DEFINES renamed to SIM_PREPROC_DEFINES
2023-06-29 13:40:44 -07:00
Nayiri K
20d6bf059f
changing clock name from clock_clock to clock_uncore_clock
2023-06-23 13:13:56 -07:00
nayiri-k
1de26550e4
small fix for #1508
2023-06-14 11:47:04 -07:00
nayiri-k
c7923d8899
use klayout for sky130-openroad tutorial, update conda install directions so that openroad/klayout installs don't fail
2023-06-08 14:56:42 -07:00
Abraham Gonzalez
c1ad70c10f
Merge pull request #1375 from ucb-bar/use-fat-jar
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Use fat jar's to remove SBT invocations
2023-05-26 17:03:42 -07:00
abejgonzalez
b65d8ef6c6
Have global location to store jar files (avoid issue with sbt assembly caching)
2023-05-26 13:14:06 -07:00
Jerry Zhao
4da1dea50f
Support multi-binary-run in RTL sim
2023-05-24 16:48:18 -07:00
abejgonzalez
2997cddc0e
Merge remote-tracking branch 'origin/main' into bump-verilator
2023-05-09 13:27:13 -07:00
joey0320
a5bf60c0f1
oops
2023-04-29 21:32:00 -07:00
joey0320
3f80507ce4
rm split-bb-files.py
2023-04-29 18:21:48 -07:00
joey0320
9ce0467bd3
fixes
2023-04-20 14:26:38 -07:00
Harrison Liew
9ef3001ce1
Remove Cadence & Synopsys plugins ( #1410 )
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* remove Cadence & Synopsys plugins from docs and scripts
* update conda-locks
2023-03-21 09:34:38 -07:00
abejgonzalez
dc0c6e62f1
Merge remote-tracking branch 'origin/main' into bump-verilator
2023-03-14 14:20:10 -07:00
Nayiri K
454d619dfc
improved tutorial makefile [skip ci]
2023-03-13 22:50:43 -07:00
abejgonzalez
95349755b5
Support TestDriver.v as top
2023-03-13 11:11:23 -07:00
Nayiri Krzysztofowicz
dd7e221a45
changing tutorial VLSI_TOP to RocketTile to save time
2023-03-12 19:04:14 -07:00
Nayiri Krzysztofowicz
3b1530402f
Merge branch 'vlsi-tutorial' of https://github.com/ucb-bar/chipyard into openroad
2023-03-12 12:29:07 -07:00
Nayiri K
180f52ed35
bumping hammer-cadence-plugins
2023-03-10 23:20:40 -08:00
Nayiri K
0f326ae980
floorplan for openroad flow is different from commercial flow bc of srams
2023-03-10 23:18:20 -08:00
Nayiri Krzysztofowicz
47f84e97b4
Merge branch 'main' of https://github.com/ucb-bar/chipyard into vlsi-tutorial
2023-03-10 15:59:13 -08:00
Nayiri K
39260ac02e
Merge branch 'openroad' of https://github.com/ucb-bar/chipyard into openroad
2023-03-10 15:20:10 -08:00
Nayiri K
6dba66f56c
updated tutorial configuration files [skip ci]
2023-03-10 15:19:47 -08:00
Harrison Liew
a8c9c8271e
Merge pull request #1369 from ucb-bar/sim-syn-par-fix
2023-03-10 15:09:58 -08:00
Nayiri K
81e11ee8e0
updating macro paths for asap7 tutorial to match new SRAM paths after rocket/chisel bump
2023-03-10 15:09:15 -08:00
Nayiri K
d5f1dd9bcb
changed key from openram to sram22
2023-03-09 11:34:34 -08:00
Harrison Liew
0883993000
model and top reference common modules, need to filter them out from sim to avoid module collisions
2023-03-08 16:11:01 -08:00
Nayiri K
1b7a424c69
adding ENABLE_YOSYS_FLOW to tutorial makefile
2023-03-08 11:40:21 -08:00
joey0320
fd8a49100c
update ENABLE_VLSI_FLOW to ENABLE_YOSYS_FLOW
2023-03-08 09:25:16 -08:00
joey0320
02fd30b2f8
Fix makefile
2023-03-06 18:26:03 -08:00
Harrison Liew
54c55875e1
hierarchical flows should all fall under TOP suffix instead of VLSI_TOP which will change
2023-03-03 14:50:57 -08:00
Harrison Liew
89929cbb6e
cat VLSI_RTL
2023-02-28 13:10:49 -08:00
Harrison Liew
c1e8b20234
add SIM_FILE_REQS
2023-02-27 15:24:00 -08:00
Harrison Liew
a681bedae0
fix top/model separation for rtl vs. post-syn/par sim
2023-02-24 20:37:36 -08:00
Harrison Liew
7566eae213
fix & clarify hierarchical flows
2023-02-24 14:56:28 -08:00
joey0320
a9209c4aaa
Fix TestDriver.v missing from gen-collateral after recompiling
2023-02-21 21:52:03 -08:00
Abraham Gonzalez
632a7a9348
Merge pull request #1349 from ucb-bar/misc-improv
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Small build system improvements
2023-02-16 11:40:55 -08:00
Sagar Karandikar
97f576da2a
Same as Makefile
2023-02-15 18:26:30 -08:00
Sagar Karandikar
86abfd1e73
Same as fix for Makefile
2023-02-15 18:25:22 -08:00
Sagar Karandikar
0c4cfc8742
Fix input files list emission to avoid bash "too many arguments" error
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This makes the expansion of "cat $(VLSI_RTL)" happen as a child of the shell that runs the for loop.
The existing version will sometimes produce a bash "too many arguments" error because the $(shell cat $(VLSI_RTL)) is expanded first and then passed as a giant command to bash.
2023-02-15 17:57:26 -08:00
abejgonzalez
85fe061244
Use EICG_wrapper model as addResource/Path | Fix Makefile parsing
2023-02-15 14:19:55 -08:00
