Jerry Zhao
f4739be632
Update multi-chip API for harnesses
2023-05-15 00:03:22 -07:00
Jerry Zhao
2077e4304d
Explicitly provide refClockFreqMHz to harnessClockInstantiator
2023-05-13 11:18:03 -07:00
Jerry Zhao
b8e95e0305
Rename implicit clock/reset to referenceclock/reset
2023-05-12 15:11:44 -07:00
Jerry Zhao
607c2b5a73
Unify multi-node btw chipyard/firechip | unify harness clocking
2023-05-12 08:41:34 -07:00
Jerry Zhao
64ad77bbcf
Make FPGA flows use the harnessClockInstantiator
2023-05-11 15:04:04 -07:00
Jerry Zhao
eced8e63d9
Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
2023-05-08 18:19:18 -07:00
Jerry Zhao
ac281daa78
Move TestHarness to chipyard.harness, make chipyard/harness directory
2023-05-08 08:00:56 -07:00
Jerry Zhao
5f076b184d
Flip serial_tl_clock to be generated off-chip
2023-05-07 22:22:36 -07:00
Jerry Zhao
e93bc3bed7
Fix Arty FPGA reset harness binder
2023-04-01 13:53:56 -07:00
Jerry Zhao
6abf970ccb
Fix ArtyJTAG matching
2023-04-01 10:23:22 -07:00
Jerry Zhao
df2e5ad9dc
Bump to latest rocket-chip/chisel3.5.6
2023-03-28 16:48:27 -07:00
Jerry Zhao
66e4448008
Merge remote-tracking branch 'origin/main' into bringup2
2023-02-28 16:19:14 -08:00
Jerry Zhao
2a4c5e6f88
Bump testchipip
2023-02-28 16:16:04 -08:00
joey0320
8e87a450b6
fpga makefile clean fix
2023-02-22 10:19:05 -08:00
joey0320
32dfc6fbf0
fixes
2023-02-21 21:52:03 -08:00
Abraham Gonzalez
632a7a9348
Merge pull request #1349 from ucb-bar/misc-improv
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Small build system improvements
2023-02-16 11:40:55 -08:00
Jerry Zhao
a50e7d3117
Add more arty100t configs with configurable TSI-UART baudrate
2023-02-15 21:45:09 -08:00
Jerry Zhao
fe51a1c7ce
Remove arty100t IOBinders file
2023-02-15 14:24:22 -08:00
abejgonzalez
85fe061244
Use EICG_wrapper model as addResource/Path | Fix Makefile parsing
2023-02-15 14:19:55 -08:00
abejgonzalez
55950b61b9
Move sim_files creation after FIRTOOL | Have FIRTOOL delete collateral dir
2023-02-15 12:01:58 -08:00
Jerry Zhao
ec6bb45674
Block Arty100T DDR during reset
2023-02-15 11:15:48 -08:00
Jerry Zhao
61cc18749a
Fix more bugs with arty100t
2023-02-14 17:15:44 -08:00
Jerry Zhao
85fa9d1120
Add ARTY100t bringup + TSI-over-UART
2023-02-14 15:01:52 -08:00
joey0320
58a6e72528
rename OUT_DIR to GEN_COLLATERAL_DIR
2023-02-13 13:24:04 -08:00
joey0320
6cd46d3c73
fixes
2023-02-13 02:14:23 -08:00
Jerry Zhao
f0df5a9d83
Bump fpga-shells
2023-02-01 14:58:36 -08:00
Jerry Zhao
7780ed23bf
Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
2023-01-26 00:12:28 -08:00
abejgonzalez
c472e22223
Update FPGA makefile | Reorg firtool args
2023-01-09 10:33:38 -08:00
abejgonzalez
292cc753ce
Run pre-commit on all files
2022-12-21 15:59:46 -08:00
Abraham Gonzalez
8e851b0285
Merge pull request #1278 from Lorilandly/vc707fpga
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Add support for VC707 FPGA board changelog:added
2022-12-14 19:16:49 -08:00
Haoan Li
dab5720445
expose functional pins and ports
2022-12-13 16:53:31 +09:00
-T.K.-
1b7457d2fc
FIX: fix Arty FPGA reset signal ( #1257 )
2022-12-07 19:34:35 -08:00
Lori Li
0724431873
Clean up code
2022-11-30 16:56:09 +09:00
Lori Li
a2d1f16488
revert module imp && fix for 4gb ram
2022-11-30 03:51:56 +09:00
Haoan Li
37f2578f6c
Bump fpga-shells version
2022-11-24 16:18:03 +09:00
Haoan Li
fb793d7ee9
Add support for VC707 fpga board
2022-11-24 16:08:15 +09:00
Jerry Zhao
04e80a6984
Bump rocketchip to latest, chisel to 3.5.2
...
Remove fork of BusTopologies from rocket-chip
Update generators/chipyard/src/main/scala/config/AbstractConfig.scala
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com >
2022-09-16 15:17:30 -07:00
Abraham Gonzalez
af78c9cadf
Remove extra spaces in FPGA makefile
2022-03-02 15:45:27 +01:00
James Dunn
8e59db02fd
Merge pull request #968 from duyhieubui/master
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Fixes UART portmap for Arty.
2021-10-13 13:25:10 -07:00
Jerry Zhao
f668ffdb03
Switch PRCI to HarnessBinder/IOBinders
2021-09-29 11:39:52 -07:00
Duy-Hieu Bui
d9858c1dc8
Fixes UART portmap for Arty.
2021-09-03 05:02:36 +07:00
Tingyuan LIANG
d06abdb419
Swap two arguments to resolve bug
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**Related issue**: N/A
**Type of change**: bug fix
**Impact**: other
**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](d4b3878e4f/xilinx/common/tcl/prologue.tcl
2021-08-12 23:22:41 +08:00
abejgonzalez
16cdc88c52
Small comment + org. fix | Remove extra mkdirs
2021-05-12 16:42:05 -07:00
abejgonzalez
2874c98802
Add sim_files.f to fpga
2021-05-06 22:11:58 -07:00
Abraham Gonzalez
985faa4c8e
Small comment updates + cleanup
2021-04-03 12:55:27 -07:00
Abraham Gonzalez
be13781a1c
Set both MBUS/PBUS in configs | Add simple check for correct clocks
2021-04-02 16:43:59 -07:00
Abraham Gonzalez
5a41c5d9ac
Use multi-clock config. frags to determine VCU118 clk freq
2021-04-01 16:21:44 -07:00
Abraham Gonzalez
f334d5799f
Support 30MiB payloads - VCU118 FPGA
2021-04-01 16:21:16 -07:00
Jerry Zhao
ed2bfa8249
Don't pass JTAG oe signal off-chip ( #832 )
2021-03-24 01:08:46 -07:00
abejgonzalez
09ef82cabf
Update harnessClk/Rst naming to buildtop | Small docs cleanup
2021-03-22 13:11:12 -07:00
