Vladimir Milovanović
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3d96cf5bc9
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Adds initial Nexys Video board support.
Co-authored-by: pznikola <p.z.nikola@etf.rs>
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2023-10-05 23:01:29 +02:00 |
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Vladimir Milovanović
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7debb5f52d
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Bump fpga-shells.
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2023-10-06 09:54:42 +02:00 |
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Jerry Zhao
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adebd634b4
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Fix Arty100T Verilog build (#1608)
* Bump rocket-chip
* Bump fpga-shells
* Add Arty100T Verilog build to CI
* Fix Arty100T harness disconnected LEDs
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2023-09-27 13:03:37 +02:00 |
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Jerry Zhao
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0b81a82459
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Fix VCU118 freq adjustment configs
Resolves #1583
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2023-09-06 10:55:53 -07:00 |
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Jerry Zhao
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5495d05aa0
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Bump to latest rocket-chip
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2023-08-22 11:28:57 -07:00 |
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Jerry Zhao
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ef3409f87f
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Merge remote-tracking branch 'origin/main' into rcbump
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2023-07-09 23:31:16 -07:00 |
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Jerry Zhao
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078bce1323
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Bump to chisel3.6
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2023-07-05 10:32:55 -07:00 |
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Jerry Zhao
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89db2372c3
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Merge remote-tracking branch 'origin/main' into tetheredsim
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2023-05-31 21:55:09 -07:00 |
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Jerry Zhao
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ea127aa815
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Merge pull request #1475 from ucb-bar/bumprc
Bump to latest rocket-chip
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2023-05-30 21:59:00 -07:00 |
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jerryho
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9844deb172
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using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width
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2023-05-27 18:12:56 +08:00 |
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jerryho
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45eeee5092
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fix the data field width mismatch between AXI that goes to MIG core and that of the Memory Bus
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2023-05-26 16:08:59 +08:00 |
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Jerry Zhao
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889713b5b1
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Switch to UARTTSIIO
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2023-05-24 19:15:11 -07:00 |
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Jerry Zhao
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6a42c64d3a
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Bump to latest rocket-chip
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2023-05-24 10:17:37 -07:00 |
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Jerry Zhao
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57f5168408
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Set number of idbits correctly for fpga ddr
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2023-05-15 00:04:12 -07:00 |
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Jerry Zhao
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f4739be632
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Update multi-chip API for harnesses
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2023-05-15 00:03:22 -07:00 |
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Jerry Zhao
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2077e4304d
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Explicitly provide refClockFreqMHz to harnessClockInstantiator
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2023-05-13 11:18:03 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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eced8e63d9
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Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
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2023-05-08 18:19:18 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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5f076b184d
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Flip serial_tl_clock to be generated off-chip
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2023-05-07 22:22:36 -07:00 |
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Jerry Zhao
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e93bc3bed7
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Fix Arty FPGA reset harness binder
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2023-04-01 13:53:56 -07:00 |
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Jerry Zhao
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6abf970ccb
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Fix ArtyJTAG matching
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2023-04-01 10:23:22 -07:00 |
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Jerry Zhao
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df2e5ad9dc
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Bump to latest rocket-chip/chisel3.5.6
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2023-03-28 16:48:27 -07:00 |
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Jerry Zhao
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66e4448008
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Merge remote-tracking branch 'origin/main' into bringup2
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2023-02-28 16:19:14 -08:00 |
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Jerry Zhao
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2a4c5e6f88
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Bump testchipip
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2023-02-28 16:16:04 -08:00 |
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joey0320
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8e87a450b6
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fpga makefile clean fix
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2023-02-22 10:19:05 -08:00 |
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joey0320
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32dfc6fbf0
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fixes
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2023-02-21 21:52:03 -08:00 |
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Abraham Gonzalez
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632a7a9348
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Merge pull request #1349 from ucb-bar/misc-improv
Small build system improvements
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2023-02-16 11:40:55 -08:00 |
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Jerry Zhao
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a50e7d3117
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Add more arty100t configs with configurable TSI-UART baudrate
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2023-02-15 21:45:09 -08:00 |
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Jerry Zhao
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fe51a1c7ce
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Remove arty100t IOBinders file
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2023-02-15 14:24:22 -08:00 |
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abejgonzalez
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85fe061244
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Use EICG_wrapper model as addResource/Path | Fix Makefile parsing
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2023-02-15 14:19:55 -08:00 |
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abejgonzalez
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55950b61b9
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Move sim_files creation after FIRTOOL | Have FIRTOOL delete collateral dir
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2023-02-15 12:01:58 -08:00 |
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Jerry Zhao
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ec6bb45674
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Block Arty100T DDR during reset
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2023-02-15 11:15:48 -08:00 |
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Jerry Zhao
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61cc18749a
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Fix more bugs with arty100t
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2023-02-14 17:15:44 -08:00 |
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Jerry Zhao
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85fa9d1120
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Add ARTY100t bringup + TSI-over-UART
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2023-02-14 15:01:52 -08:00 |
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joey0320
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58a6e72528
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rename OUT_DIR to GEN_COLLATERAL_DIR
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2023-02-13 13:24:04 -08:00 |
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joey0320
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6cd46d3c73
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fixes
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2023-02-13 02:14:23 -08:00 |
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Jerry Zhao
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f0df5a9d83
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Bump fpga-shells
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2023-02-01 14:58:36 -08:00 |
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Jerry Zhao
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7780ed23bf
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Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
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2023-01-26 00:12:28 -08:00 |
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abejgonzalez
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c472e22223
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Update FPGA makefile | Reorg firtool args
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2023-01-09 10:33:38 -08:00 |
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abejgonzalez
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292cc753ce
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Run pre-commit on all files
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2022-12-21 15:59:46 -08:00 |
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Abraham Gonzalez
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8e851b0285
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Merge pull request #1278 from Lorilandly/vc707fpga
Add support for VC707 FPGA board changelog:added
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2022-12-14 19:16:49 -08:00 |
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Haoan Li
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dab5720445
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expose functional pins and ports
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2022-12-13 16:53:31 +09:00 |
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-T.K.-
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1b7457d2fc
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FIX: fix Arty FPGA reset signal (#1257)
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2022-12-07 19:34:35 -08:00 |
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Lori Li
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0724431873
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Clean up code
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2022-11-30 16:56:09 +09:00 |
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Lori Li
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a2d1f16488
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revert module imp && fix for 4gb ram
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2022-11-30 03:51:56 +09:00 |
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Haoan Li
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37f2578f6c
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Bump fpga-shells version
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2022-11-24 16:18:03 +09:00 |
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Haoan Li
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fb793d7ee9
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Add support for VC707 fpga board
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2022-11-24 16:08:15 +09:00 |
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