cleanup

.gitmodules

@@ -1,9 +0,0 @@
-[submodule "third_party/fpnew"]
-	path = third_party/fpnew
-	url = https://github.com/pulp-platform/fpnew.git
-[submodule "third_party/softfloat"]
-	path = third_party/softfloat
-	url = https://github.com/ucb-bar/berkeley-softfloat-3.git
-[submodule "third_party/ramulator"]
-	path = third_party/ramulator
-	url = https://github.com/CMU-SAFARI/ramulator.git

Makefile

@@ -1,28 +1,12 @@
 all:
-	$(MAKE) -C third_party
-	$(MAKE) -C hw
-	$(MAKE) -C sim
 	$(MAKE) -C kernel
-	$(MAKE) -C runtime
 	$(MAKE) -C tests
 
 clean:
-	$(MAKE) -C hw clean
-	$(MAKE) -C sim clean
 	$(MAKE) -C kernel clean
-	$(MAKE) -C runtime clean
 	$(MAKE) -C tests clean
 
 clean-all:
-	$(MAKE) -C third_party clean
-	$(MAKE) -C hw clean
-	$(MAKE) -C sim clean
 	$(MAKE) -C kernel clean
-	$(MAKE) -C runtime clean
 	$(MAKE) -C tests clean-all
 
-crtlsim:
-	$(MAKE) -C sim clean
-
-brtlsim:
-	$(MAKE) -C sim

README.md

@@ -1,65 +1,5 @@
-[![Build Status](https://travis-ci.com/vortexgpgpu/vortex.svg?branch=master)](https://travis-ci.com/vortexgpgpu/vortex)
+# Virgo Kernels
-[![codecov](https://codecov.io/gh/vortexgpgpu/vortex/branch/master/graph/badge.svg)](https://codecov.io/gh/vortexgpgpu/vortex)
 
-# Vortex GPGPU
+This repo contains kernels written for the Virgo paper. It is adapted from the Vortex project repo.
 
-Vortex is a full-stack open-source RISC-V GPGPU.
+More details to follow.
-
-## Specifications
-
-- Support RISC-V RV32IMAF and RV64IMAFD
-- Microarchitecture:
-    - configurable number of cores, warps, and threads.
-    - configurable number of ALU, FPU, LSU, and SFU units per core.
-    - configurable pipeline issue width.
-    - optional shared memory, L1, L2, and L3 caches.
-- Software: 
-    - OpenCL 1.2 Support.
-- Supported FPGAs: 
-    - Altera Arria 10
-    - Altera Stratix 10
-    - Xilinx Alveo U50, U250, U280
-    - Xilinx Versal VCK5000
-
-## Directory structure
-
-- `doc`: [Documentation](docs/index.md).
-- `hw`: Hardware sources.
-- `driver`: Host drivers repository.
-- `runtime`: Kernel Runtime software.
-- `sim`: Simulators repository.
-- `tests`: Tests repository.
-- `ci`: Continuous integration scripts.
-- `miscs`: Miscellaneous resources.
-
-## Build Instructions
-More detailed build instructions can be found [here](docs/install_vortex.md).
-### Supported OS Platforms
-- Ubuntu 18.04, 20.04
-- Centos 7
-### Toolchain Dependencies
-- [POCL](http://portablecl.org/)
-- [LLVM](https://llvm.org/)
-- [RISCV-GNU-TOOLCHAIN](https://github.com/riscv-collab/riscv-gnu-toolchain)
-- [Verilator](https://www.veripool.org/verilator)
-- [FpNew](https://github.com/pulp-platform/fpnew.git)
-- [SoftFloat](https://github.com/ucb-bar/berkeley-softfloat-3.git)
-- [Ramulator](https://github.com/CMU-SAFARI/ramulator.git)
-- [Yosys](https://github.com/YosysHQ/yosys)
-- [Sv2v](https://github.com/zachjs/sv2v)
-### Install development tools 
-    $ sudo apt-get install build-essential
-    $ sudo apt-get install git
-### Install Vortex codebase
-    $ git clone --recursive https://github.com/vortexgpgpu/vortex.git
-    $ cd Vortex
-### Install prebuilt toolchain
-    By default, the toolchain will install to /opt folder which requires sudo access. 
-    You can install the toolchain to a different location of your choice by setting TOOLDIR (e.g. export TOOLDIR=$HOME/tools).
-    $ export TOOLDIR=/opt
-    $ ./ci/toolchain_install.sh --all
-    $ source ./ci/toolchain_env.sh
-### Build Vortex sources
-    $ make -s
-### Quick demo running vecadd OpenCL kernel on 2 cores
-    $ ./ci/blackbox.sh --cores=2 --app=vecadd

docs/cache_subsystem.md

@@ -1,27 +0,0 @@
-# Vortex Cache Subsystem
-
-The Vortex Cache Sub-system has the following main properties:
-
-- High-bandwidth transfer with Multi-bank parallelism
-- Non-blocking pipelined architecture with local MSHR
-- Configurable design: Dcache, Icache, L2 cache, L3 cache
-
-### Cache Microarchitecture 
-
-![Image of Cache Hierarchy](./assets/img/cache_microarchitecture.png)
-
-The Vortex cache is comprised of multiple parallel banks. It is comprised of the following modules:
-- **Bank request dispatch crossbar**: assign a bank to incoming requests and resolve collision using stalls.
-- **Bank response merge crossbar**: merge result from banks and forward to the core response.
-- **Memory request multiplexer**: arbitrate bank memory requests
-- **Memory response demultiplexer**: forward memory response to the corresponding bank.
-- **Flush Unit**: perform tag memory initialization.
-
-Incoming requests entering the cache are sent to a dispatch crossbar that select the corresponding bank for each request, resolving bank collisions with stalls. The result output of each bank is merge back into outgoing response port via merger crossbar. Each bank intergates a non-blocking pipeline with a local Miss Status Holding Register (MSHR) to reduce the miss rate. The bank pipeline consists of the following stages:
-
-- **Schedule**: Selects the next request into the pipeline from the incoming core request, memory fill, or the MSHR entry, with priority given to the latter.
-- **Tag Access**: A single-port read/write access to the tag store.
-- **Data Access**: Single-port read/write access to the data store.
-- **Response Handling**: Core response back to the core.
-
-Deadlocks inside the cache can occur when the MSHR is full and a new request is already in the pipeline. It can also occur when the memory request queue is full, and there is an incoming memory response. The cache mitigates MSHR deadlocks by using an early full signal before a new request is issued and similarly mitigates memory deadlocks by ensuring that its request queue never fills up.

docs/codebase.md

@@ -1,41 +0,0 @@
-# Vortex Codebase
-
-The directory/file layout of the Vortex codebase is as followed:
-
-- `hw`:     
-  - `rtl`: hardware rtl sources    
-    - `core`: core pipeline
-    - `cache`: cache subsystem
-    - `mem`: memory subsystem
-    - `fpu`: floating point unit
-    - `interfaces`: interfaces for inter-module communication
-    - `libs`: general-purpose RTL modules    
-  - `syn`: synthesis directory
-    - `altera`: Altera synthesis scripts
-    - `xilinx`: Xilinx synthesis scripts    
-    - `synopsys`: Synopsys synthesis scripts
-    - `modelsim`: Modelsim synthesis scripts
-    - `yosys`: Yosys synthesis scripts
-  - `unit_tests`: unit tests for some hardware components
-- `runtime`: host runtime software APIs
-  - `include`: Vortex driver public headers
-  - `stub`: Vortex stub driver library
-  - `opae`: software driver that uses Intel OPAE API with device targets=fpga|asesim|opaesim
-  - `xrt`: software driver that uses Xilinx XRT API with device targets=hw|hw_emu|sw_emu
-  - `rtlsim`: software driver that uses rtlsim simulator
-  - `simx`: software driver that uses simX simulator
-- `kernel`: GPU kernel software APIs
-  - `include`: Vortex runtime public headers
-  - `linker`: linker file for compiling kernels
-  - `src`: runtime implementation
-- `sim`: 
-  - `opaesim`: Intel OPAE AFU RTL simulator
-  - `rtlsim`: processor RTL simulator
-  - `simX`: cycle approximate simulator for vortex
-- `tests`: tests repository.
-  - `riscv`: RISC-V conformance tests
-  - `kernel`: kernel tests
-  - `regression`: regression tests  
-  - `opencl`: opencl benchmarks and tests
-- `ci`: continuous integration scripts
-- `miscs`: miscellaneous resources.

docs/continuous_integration.md

@@ -1,36 +0,0 @@
-# Continuous Integration
-- Each time you push to the repo, the Continuous Integration pipeline will run
-- This pipeline consists of creating the correct development environment, building your code, and running all tests
-- This is an extensive pipeline so it might take some time to complete
-
-
-## Protecting Master Branch
-Navigate to your Repository:
-Open your repository on GitHub.
-
-Click on "Settings":
-In the upper-right corner of your repository page, click on the "Settings" tab.
-
-Select "Branches" in the left sidebar:
-On the left sidebar, look for the "Branches" option and click on it.
-
-Choose the Branch:
-Under "Branch protection rules," select the branch you want to protect. In this case, choose the main branch.
-
-Enable Branch Protection:``
-Check the box that says "Protect this branch."
-
-Configure Protection Settings:
-You can configure various protection settings. Some common settings include:
-
-Require pull request reviews before merging: This ensures that changes are reviewed before being merged.
-Require status checks to pass before merging: This ensures that automated tests and checks are passing.
-Require signed commits: This enforces that commits are signed with a verified signature.
-Restrict Who Can Push:
-You can further restrict who can push directly to the branch. You might want to limit this privilege to specific people or teams.
-
-Save Changes:
-Once you've configured the protection settings, scroll down and click on the "Save changes" button.
-
-Now, your main branch is protected, and certain criteria must be met before changes can be pushed directly to it. Contributors will need to create pull requests, have their changes reviewed, and meet other specified criteria before the changes can be merged into the main branch.
-

docs/contributing.md

@@ -1,18 +0,0 @@
-# Contributing to Vortex on Github
-
-## Github Details
-- There are two main repos, `vortex` (public, this one) and `vortex-dev` (private)
-- todo: Most current development is on `vortex`
-- If you have a legacy version of `vortex`, you can use the releases branch or tags to access the repo at that point in time
-
-## Contribution Process
-- You should create a new branch from develop that is clearly named with the feature that you want to add
-- Avoid pushing directly to the `master` branch instead you will need to make a Pull Request (PR)
-- There should be protections in place that prevent pushing directly to the main branch, but don't rely on it
-- When you make a PR it will be tested against the continuous integration (ci) pipeline (see `continuous_integration.md`)
-- It is not sufficient to just write some tests, they need to be incorporated into the ci pipeline to make sure they are run
-- During a PR, you might receive feedback regarding your changes and you might need to make further commits to your branch
-
-
-## Creating  and Adding Tests
-see `testing.md`

docs/debugging.md

@@ -1,65 +0,0 @@
-# Debugging Vortex GPU
-
-## Testing changes to the RTL or simulator GPU driver.
-
-The Blackbox utility script will not pick up your changes if the h/w configuration is the same as during teh last run.
-To force the utility to build the driver, you need pass the --rebuild=1 option when running tests. 
-Using --rebuild=0 will prevent the rebuild even if the h/w configuration is different from last run.
-
-    $ ./ci/blackbox.sh --driver=simx --app=demo --rebuild=1
-
-## SimX Debugging
-
-SimX cycle-approximate simulator allows faster debugging of Vortex kernels' execution. 
-The recommended method to enable debugging is to pass the `--debug=<level>` flag to `blackbox` tool when running a program.
-
-    // Running demo program on SimX in debug mode
-    $ ./ci/blackbox.sh --driver=simx --app=demo --debug=1
-
-A debug trace `run.log` is generated in the current directory during the program execution. The trace includes important states of the simulated processor (decoded instruction, register states, pipeline states, etc..). You can increase the verbosity of the trace by changing the debug level.
-
-    // Using SimX in debug mode with verbose level 3
-    $ ./ci/blackbox.sh --driver=simx --app=demo --debug=3
-
-## RTL Debugging
-
-To debug the processor RTL, you need to use VLSIM or RTLSIM driver. VLSIM simulates the full processor including the AFU command processor (using `/rtl/afu/opae/vortex_afu.sv` as top module). RTLSIM simulates the Vortex processor only (using `/rtl/Vortex.v` as top module).
-
-The recommended method to enable debugging is to pass the `--debug` flag to `blackbox` tool when running a program.
-
-    // Running demo program on the opae simulator in debug mode
-    $ TARGET=opaesim ./ci/blackbox.sh --driver=opae --app=demo --debug=1
-
-    // Running demo program on rtlsim in debug mode
-    $ ./ci/blackbox.sh --driver=rtlsim --app=demo --debug=1
-
-A debug trace `run.log` is generated in the current directory during the program execution. The trace includes important states of the simulated processor (memory, caches, pipeline, stalls, etc..). A waveform trace `trace.vcd` is also generated in the current directory during the program execution. You can visualize the waveform trace using any tool that can open VCD files (Modelsim, Quartus, Vivado, etc..). [GTKwave] (http://gtkwave.sourceforge.net) is a great open-source scope analyzer that also works with VCD files.
-
-## FPGA Debugging
-
-Debugging the FPGA directly may be necessary to investigate runtime bugs that the RTL simulation cannot catch. We have implemented an in-house scope analyzer for Vortex that works when the FPGA is running. To enable the FPGA scope analyzer, the FPGA bitstream should be built using `SCOPE=1` flag
-
-    & cd /hw/syn/opae
-    $ CONFIGS="-DSCOPE=1" TARGET=fpga make
-
-When running the program on the FPGA, you need to pass the `--scope` flag to the `blackbox` tool.
-
-    // Running demo program on FPGA with scope enabled
-    $ ./ci/blackbox.sh --driver=fpga --app=demo --scope
-
-
-A waveform trace `trace.vcd` will be generated in the current directory during the program execution. This trace includes a limited set of signals that are defined in `/hw/scripts/scope.json`. You can expand your signals' selection by updating the json file.
-
-## Analyzing Vortex trace log
-
-When debugging Vortex RTL or SimX Simulator, reading the trace run.log file can be overwhelming when the trace gets really large.
-We provide a trace sanitizer tool under ./hw/scripts/trace_csv.py that you can use to convert the large trace into a CSV file containing all the instructions that executed with their source and destination operands.
-
-    $ ./ci/blackbox.sh --driver=rtlsim --app=demo --debug=3 --log=run_rtlsim.log
-    $ ./ci/trace_csv.py -trtlsim run_rtlsim.log -otrace_rtlsim.csv
-
-    $ ./ci/blackbox.sh --driver=simx --app=demo --debug=3 --log=run_simx.log
-    $ ./ci/trace_csv.py -tsimx run_simx.log -otrace_simx.csv
-
-The first column in the CSV trace is UUID (universal unique identifier) of the instruction and the content is sorted by the UUID. You can use the UUID to trace the same instruction running on either the RTL hw or SimX simulator. 
-This can be very effective if you want to use SimX to debugging your RTL hardware by comparing CSV traces.

docs/environment_setup.md

@@ -1,45 +0,0 @@
-# Environment Setup
-These instructions apply to the development vortex repo using the updated toolchain. The updated toolchain is considered to be any commit of `master` pulled from July 2, 2023 onwards. The toolchain update in question can be viewed in this [commit](https://github.com/vortexgpgpu/vortex-dev/commit/0048496ba28d7b9a209a0e569d52d60f2b68fc04). Therefore, if you are unsure whether you are using the new toolchain or not, then you should check the `ci` folder for the existence of the `toolchain_prebuilt.sh` script. Furthermore, you should notice that the `toolchain_install.sh` script has the legacy `llvm()` split into `llvm-vortex()` and `llvm-pocl()`.
-
-
-## Set Up on Your Own System
-The toolchain binaries provided with Vortex are built on Ubuntu-based systems. To install Vortex on your own system, [follow these instructions](install_vortex.md).
-
-
-## Servers for Georgia Tech Students and Collaborators
-### Volvo
-Volvo is a 64-core server provided by HPArch. You need valid credentials to access it. If you don't already have access, you can get in contact with your mentor to ask about setting your account up.
-
-Setup on Volvo:
-1. Connect to Georgia Tech's VPN or ssh into another machine on campus
-2. `ssh volvo.cc.gatech.edu`
-3. Clone Vortex to your home directory: `git clone --recursive https://github.com/vortexgpgpu/vortex.git`
-4. `source /nethome/software/set_vortex_env.sh` to set up the necessary environment variables.
-5. `make -s` in the `vortex` root directory
-6. Run a test program: `./ci/blackbox.sh --cores=2 --app=dogfood`
-
-### Nio
-Nio is a 20-core desktop server provided by HPArch. If you have access to Volvo, you also have access to Nio.
-
-Setup on Nio:
-1. Connect to Georgia Tech's VPN or ssh into another machine on campus
-2. `ssh nio.cc.gatech.edu`
-3. Clone Vortex to your home directory: `git clone --recursive https://github.com/vortexgpgpu/vortex.git`
-4. `source /opt/set_vortex_env_dev.sh` to set up the necessary environment variables.
-5. `make -s` in the `vortex` root directory
-6. Run a test program: `./ci/blackbox.sh --cores=2 --app=dogfood`
-
-
-## Docker (Experimental)
-Docker allows for isolated pre-built environments to be created, shared and used. The emulation mode required for ARM-based processors will incur a decrease in performance. Currently, the dockerfile is not included with the official vortex repository and is not actively maintained or supported.
-
-### Setup with Docker
-1. Clone repo recursively onto your local machine: `git clone --recursive https://github.com/vortexgpgpu/vortex.git`
-2. Download the dockerfile from [here](https://github.gatech.edu/gist/usubramanya3/f1bf3e953faa38a6372e1292ffd0b65c) and place it in the root of the repo.
-3. Build the Dockerfile into an image: `docker build --platform=linux/amd64 -t vortex -f dockerfile .`
-4. Run a container based on the image: `docker run --rm -v ./:/root/vortex/ -it --name vtx-dev --privileged=true --platform=linux/amd64 vortex`
-5. Install the toolchain `./ci/toolchain_install.sh --all` (once per container)
-6. `make -s` in `vortex` root directory
-7. Run a test program: `./ci/blackbox.sh --cores=2 --app=dogfood`
-
-You may exit from a container and resume a container you have exited or start a second terminal session `docker exec -it <container-name> bash`

docs/fpga_setup.md

@@ -1,74 +0,0 @@
-# FPGA Startup and Configuration Guide 
-
-OPAE Environment Setup
-----------------------
-
-    $ source /opt/inteldevstack/init_env_user.sh
-    $ export OPAE_HOME=/opt/opae/1.1.2
-    $ export PATH=$OPAE_HOME/bin:$PATH
-    $ export C_INCLUDE_PATH=$OPAE_HOME/include:$C_INCLUDE_PATH
-    $ export LIBRARY_PATH=$OPAE_HOME/lib:$LIBRARY_PATH
-    $ export LD_LIBRARY_PATH=$OPAE_HOME/lib:$LD_LIBRARY_PATH
-
-OPAE Build
-------------------
-
-The FPGA has to following configuration options:
-- DEVICE_FAMILY=arria10 | stratix10
-- NUM_CORES=#n
-
-Command line:
-
-    $ cd hw/syn/altera/opae
-    $ PREFIX=test1 TARGET=fpga NUM_CORES=4 make
-
-A new folder (ex: `test1_xxx_4c`) will be created and the build will start and take ~30-480 min to complete.
-Setting TARGET=ase will build the project for simulation using Intel ASE.
-
-
-OPAE Build Configuration
-------------------------
-
-The hardware configuration file `/hw/rtl/VX_config.vh` defines all the hardware parameters that can be modified when build the processor.For example, have the following parameters that can be configured:
-- `NUM_WARPS`:   Number of warps per cores
-- `NUM_THREADS`: Number of threads per warps
-- `PERF_ENABLE`: enable the use of all profile counters
-
-You configure the syntesis build from the command line:
-
-    $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make
-
-OPAE Build Progress
--------------------
-
-You could check the last 10 lines in the build log for possible errors until build completion.
-
-    $ tail -n 10 <build_dir>/build.log
-
-Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs.
-
-    $ ps -u <username>
-
-If the build fails and you need to restart it, clean up the build folder using the following command:
-
-    $ make clean
-
-The file `vortex_afu.gbs` should exist when the build is done:
-
-    $ ls -lsa <build_dir>/vortex_afu.gbs
-
-
-Signing the bitstream and Programming the FPGA
-----------------------------------------------
-
-    $ cd <build_dir>
-    $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs
-    $ fpgasupdate vortex_afu_unsigned_ssl.gbs
-
-FPGA sample test running OpenCL sgemm kernel
---------------------------------------------
-
-Run the following from the Vortex root directory
-
-    $ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64"
-

docs/index.md

@@ -1,32 +0,0 @@
-# Vortex Documentation
-
-## Table of Contents
-
-- [Codebase Layout](codebase.md)
-- [Microarchitecture](microarchitecture.md)
-- [Cache Subsystem](cache_subsystem.md)
-- [Software](software.md)
-- [Simulation](simulation.md)
-- [FPGA Setup Guide](fpga_setup.md)
-- [Debugging](debugging.md)
-- [Useful Links](references.md)
-
-## Installation
-
-- For the different environments Vortex supports, [read this document](environment_setup.md).
-- To install on your own system, [follow this document](install_vortex.md).
-
-## Quick Start Scenarios
-
-Running Vortex simulators with different configurations:
-- Run basic driver test with rtlsim driver and Vortex config of 2 clusters, 2 cores, 2 warps, 4 threads
-
-    $ ./ci/blackbox.sh --driver=rtlsim --clusters=2 --cores=2 --warps=2 --threads=4  --app=basic
-
-- Run demo driver test with opae driver and Vortex config of 1 clusters, 4 cores, 4 warps, 2 threads
-
-    $ ./ci/blackbox.sh --driver=opae --clusters=1 --cores=4 --warps=4 --threads=2 --app=demo
-
-- Run dogfood driver test with simx driver and Vortex config of 4 cluster, 4 cores, 8 warps, 6 threads 
-
-    $ ./ci/blackbox.sh --driver=simx --clusters=4 --cores=4 --warps=8 --threads=6  --app=dogfood

docs/install_vortex.md

@@ -1,124 +0,0 @@
-# Installing and Setting Up the Vortex Environment
-
-## Ubuntu 18.04, 20.04
-
-1. Install the following dependencies:
-
-   ```
-   sudo apt-get install build-essential zlib1g-dev libtinfo-dev libncurses5 uuid-dev libboost-serialization-dev libpng-dev libhwloc-dev
-   ```
-
-2. Upgrade gcc to 11:
-
-   ```
-   sudo apt-get install gcc-11 g++-11
-   ```
-   
-   Multiple gcc versions on Ubuntu can be managed with update-alternatives, e.g.:
-   
-   ```
-   sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 9
-   sudo update-alternatives --install /usr/bin/g++ g++ /usr/bin/g++-9 9
-   sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-11 11
-   sudo update-alternatives --install /usr/bin/g++ g++ /usr/bin/g++-11 11
-   ```
-
-3. Download the Vortex codebase:
-
-   ```
-   git clone --recursive https://github.com/vortexgpgpu/vortex.git
-   ```
-
-4. Install Vortex's prebuilt toolchain:
-
-    ```
-    cd vortex
-    sudo ./ci/toolchain_install.sh -all
-	
-    # By default, the toolchain will install to /opt folder. This is recommended, but you can install the toolchain to a different directory by setting DESTDIR.
-    DESTDIR=$TOOLDIR ./ci/toolchain_install.sh -all
-    ```
-
-5. Set up environment:
-
-    ```
-    export VORTEX_HOME=$TOOLDIR/vortex
-    export LLVM_VORTEX=$TOOLDIR/llvm-vortex
-    export LLVM_POCL=$TOOLDIR/llvm-pocl
-    export POCL_CC_PATH=$TOOLDIR/pocl/compiler
-    export POCL_RT_PATH=$TOOLDIR/pocl/runtime
-    export RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv-gnu-toolchain
-    export VERILATOR_ROOT=$TOOLDIR/verilator
-    export SV2V_PATH=$TOOLDIR/sv2v
-    export YOSYS_PATH=$TOOLDIR/yosys
-	
-    export PATH=$YOSYS_PATH/bin:$SV2V_PATH/bin:$VERILATOR_ROOT/bin:$PATH
-    ```
-
-6. Build Vortex
-
-    ```
-    make
-    ```
-
-
-## RHEL 8
-Note: depending on the system, some of the toolchain may need to be recompiled for non-Ubuntu Linux. The source for the tools can be found [here](https://github.com/vortexgpgpu/).
-
-1. Install the following dependencies:
-
-   ```
-   sudo yum install libpng-devel boost boost-devel boost-serialization libuuid-devel opencl-headers hwloc hwloc-devel gmp-devel compat-hwloc1
-   ```
-
-2. Upgrade gcc to 11:
-
-    ```
-    sudo yum install gcc-toolset-11
-    ```
-	
-   Multiple gcc versions on Red Hat can be managed with scl
-
-3. Install MPFR 4.2.0:
-
-   Download [the source](https://ftp.gnu.org/gnu/mpfr/) and follow [the installation documentation](https://www.mpfr.org/mpfr-current/mpfr.html#How-to-Install).
-
-4. Download the Vortex codebase:
-
-   ```
-   git clone --recursive https://github.com/vortexgpgpu/vortex.git
-   ```
-
-5. Install Vortex's prebuilt toolchain:
-
-    ```
-    cd vortex
-    sudo ./ci/toolchain_install.sh -all
-	
-    # By default, the toolchain will install to /opt folder. This is recommended, but you can install the toolchain to a different directory by setting DESTDIR.
-    DESTDIR=$TOOLDIR ./ci/toolchain_install.sh -all
-    ```
-
-6. Set up environment:
-
-    ```
-    export VORTEX_HOME=$TOOLDIR/vortex
-    export LLVM_VORTEX=$TOOLDIR/llvm-vortex
-    export LLVM_POCL=$TOOLDIR/llvm-pocl
-    export POCL_CC_PATH=$TOOLDIR/pocl/compiler
-    export POCL_RT_PATH=$TOOLDIR/pocl/runtime
-    export RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv-gnu-toolchain
-    export VERILATOR_ROOT=$TOOLDIR/verilator
-    export SV2V_PATH=$TOOLDIR/sv2v
-    export YOSYS_PATH=$TOOLDIR/yosys
-	
-    export PATH=$YOSYS_PATH/bin:$SV2V_PATH/bin:$VERILATOR_ROOT/bin:$PATH
-	
-    export LD_LIBRARY_PATH=<path to mpfr>/src/.libs:$LD_LIBRARY_PATH
-    ```
-
-7. Build Vortex
-
-    ```
-    make
-    ```

docs/microarchitecture.md

@@ -1,80 +0,0 @@
-# Vortex Microarchitecture
-
-### Vortex GPGPU Execution Model
-
-Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with a single warp issued per cycle.
-
-- **Threads**
-  - Smallest unit of computation
-  - Each thread has its own register file (32 int + 32 fp registers)
-  - Threads execute in parallel
-- **Warps**
-  - A logical clster of threads
-  - Each thread in a warp execute the same instruction
-    - The PC is shared; maintain thread mask for Writeback
-  - Warp's execution is time-multiplexed at log steps
-    - Ex. warp 0 executes at cycle 0, warp 1 executes at cycle 1
-
-### Vortex RISC-V ISA Extension
-
-- **Thread Mask Control**
-  - Control the number of warps to activate during execution
-  - `TMC` *count*: activate count threads
-- **Warp Scheduling**
-  - Control the number of warps to activate during execution
-  - `WSPAWN` *count, addr*: activate count warps and jump to addr location
-- **Control-Flow Divergence**
-  - Control threads activation when a branch diverges
-    - `SPLIT` *taken, predicate*: apply predicate thread mask and save current state into IPDOM stack
-    - `JOIN`: pop IPDOM stack to restore thread mask
-    - `PRED` *predicate, restore_mask*: thread predicate instruction
-- **Warp Synchronization**
-  - `BAR` *id, count*: stall warps entering barrier *id* until count is reached
-
-### Vortex Pipeline/Datapath
-
-![Image of Vortex Microarchitecture](./assets/img/vortex_microarchitecture.png)
-
-Vortex has a 6-stage pipeline:
-
-- **Schedule**
-  - Warp Scheduler
-    - Schedule the next PC into the pipeline
-    - Track stalled, active warps
-  - IPDOM Stack
-    - Save split/join states for divergent threads
-  - Inflight Tracker
-    - Track in-flight instructions
-
-- **Fetch**
-  - Retrieve instructions from memory
-  - Handle I-cache requests/responses
-- **Decode**
-  - Decode fetched instructions
-  - Notify warp scheduler on control instructions
-- **Issue**
-  - IBuffer
-    - Store decoded instructions in separate per-warp queues
-  - Scoreboard
-    - Track in-use registers
-    - Check register use for decoded instructions
-  - Operands Collector
-    - Fetch the operands for issued instructions from the register file
-- **Execute**
-  - ALU Unit
-    - Handle arithmetic and branch operations
-  - FPU Unit
-    - Handle floating-point operations
-  - LSU Unit
-    - Handle load/store operations
-  - SFU Unit
-    - Handle warp control operations
-    - Handle Control Status Registers (CSRs) operations
-- **Commit**
-  - Write result back to the register file and update the Scoreboard.
-
-### Vortex clustering architecture
-- Sockets
-  - Grouping multiple cores sharing L1 cache
-- Clusters
-  - Grouping of sockets sharing L2 cache

docs/references.md

@@ -1 +0,0 @@
-# Useful Links

docs/simulation.md

@@ -1,50 +0,0 @@
-# Vortex Simulation Methods 
-
-### RTL Simulation
-
-[Verilator](https://www.veripool.org/projects/verilator/wiki) is a Verilog/SystemVerilog design simulator that converts the Verilog HDL to single- or mult-ithreaded C++/SystemC code to perform the design simulation. An installation guide for Verilator is located [here.](https://www.veripool.org/projects/verilator/wiki/Installing)
-
-### Cycle-Approximate Simulation
-
-SimX is a C++ cycle-level in-house simulator developed for Vortex. The relevant files are located in the `simX` folder.
-
-### FGPA Simulation
-
-The current target FPGA for simulation is the Arria10 Intel Accelerator Card v1.0. The guide to build the fpga with specific configurations is located [here.](fpga_setup.md)
-
-### How to Test
-
-Running tests under specific drivers (rtlsim,simx,fpga) is done using the script named `blackbox.sh` located in the `ci` folder. Running command `./ci/blackbox.sh --help` from the Vortex root directory will display the following command line arguments for `blackbox.sh`:
-
-- *Clusters* - used to specify the number of clusters (collection of processing elements) within a configuration.
-- *Cores* - used to specify the number of cores (processing element containing multiple warps) within a configuration.
-- *Warps* - used to specify the number of warps (collection of concurrent hardware threads) within a configuration.
-- *Threads* - used to specify the number of threads (smallest unit of computation) within a configuration.
-- *L2cache* - used to enable the shard l2cache among the Vortex cores.
-- *L3cache* - used to enable the shared l3cache among the Vortex clusters.
-- *Driver* - used to specify which driver to run the Vortex simulation (either rtlsim, opae, xrt, simx).
-- *Debug* - used to enable debug mode for the Vortex simulation.
-- *Perf* - used to enable the detailed performance counters within the Vortex simulation.
-- *App* - used to specify which test/benchmark to run in the Vortex simulation. The main choices are vecadd, sgemm, basic, demo, and dogfood. Other tests/benchmarks are located in the `/benchmarks/opencl` folder though not all of them work wit the current version of Vortex.
-- *Args* - used to pass additional arguments to the application.
-
-Example use of command line arguments: Run the sgemm benchmark using the opae driver with a Vortex configuration of 1 cluster, 4 cores, 4 warps, and 4 threads.
-
-    $ ./ci/blackbox.sh --clusters=1 --cores=4 --warps=4 --threads=4 --driver=opae --app=sgemm
-
-Output from terminal:
-```
-Create context
-Create program from kernel source
-Upload source buffers
-Execute the kernel
-Elapsed time: 2463 ms
-Download destination buffer
-Verify result
-PASSED!
-PERF: core0: instrs=90802, cycles=52776, IPC=1.720517
-PERF: core1: instrs=90693, cycles=53108, IPC=1.707709
-PERF: core2: instrs=90849, cycles=53107, IPC=1.710678
-PERF: core3: instrs=90836, cycles=50347, IPC=1.804199
-PERF: instrs=363180, cycles=53108, IPC=6.838518
-```

docs/software.md

@@ -1 +0,0 @@
-# Vortex OpenCL Support

docs/testing.md

@@ -1,47 +0,0 @@
-# Testing
-
-## Running a Vortex application
-
-The framework provides a utility script: blackbox.sh under the /ci/ folder for executing applications in the tests tree.
-You can query the commandline options of the tool using:
-
-    $ ./ci/blackbox.sh --help
-
-To execute sgemm test program on the simx driver and passing "-n10" as argument to sgemm:
-
-    $ ./ci/blackbox.sh --driver=simx --app=sgemm --args="-n10"
-
-You can execute the same application of a GPU architecture with 2 cores:
-
-    $ ./ci/blackbox.sh --core=2 --driver=simx --app=sgemm --args="-n10"
-
-When excuting, Blackbox needs to recompile the driver if the desired architecture changes. 
-It tracks the latest configuration in a file under the current directory blackbox.<driver>.cache.
-To avoid having to rebuild the driver all the time, Blackbox checks if the latest cached configuration matches the current.
-
-## Running Benchmarks
-
-The Vortex test suite is located under the /test/ folder
-You can execute the default regression suite by running the following commands at the root folder.
-
-    $ make -C tests/regression run-simx 
-    $ make -C tests/regression run-rtlsim
-
-You can execute the default opncl suite by running the following commands at the root folder.
-
-    $ make -C tests/opencl run-simx 
-    $ make -C tests/opencl run-rtlsim
-
-## Creating Your Own Regression Tests
-- Inside `test/` you will find a series of folders which are named based on what they test
-- You can view the tests to see which ones have tests similar to what you are trying to create new tests for
-- once you have found a similar baseline, you can copy the folder and rename it to what you are planning to test
-- `testcases.h` contains each of the test case templates
-- `main.cpp` contains the implementation of each of the test cases and builds a test suite of all the tests cases you want
-
-Compile the test case: `make -C tests/regression/<testcase-name>/ clean-all && make -C tests/regression/<testcase-name>/`
-
-Run the test case: `./ci/blackbox.sh --driver=simx --cores=4 --app=<testcase-name> --debug`
-
-## Adding Your Tests to the CI Pipeline
-see `continuous_integration.md`

hw/.gitignore

@@ -1,2 +0,0 @@
-VX_config.h
-VX_types.h

hw/Makefile

@@ -1,17 +0,0 @@
-RTL_DIR=./rtl
-SCRIPT_DIR=./scripts
-
-all: config
-
-config: VX_config.h VX_types.h
-
-VX_config.h: $(RTL_DIR)/VX_config.vh	 
-	$(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/VX_config.vh -o VX_config.h
-
-VX_types.h: $(RTL_DIR)/VX_types.vh	 
-	$(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/VX_types.vh -o VX_types.h
-
-clean:
-	rm -f VX_config.h VX_types.h
-
-.PHONY: VX_config.h VX_types.h

hw/VX_config.h

@@ -1,685 +0,0 @@
-// auto-generated by gen_config.py. DO NOT EDIT
-// Generated at 2024-05-07 13:55:58.398687
-
-// Translated from ./rtl/VX_config.vh:
-
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef VX_CONFIG_VH
-#define VX_CONFIG_VH
-
-#ifndef MIN
-#define MIN(x, y)   (((x) < (y)) ? (x) : (y))
-#endif
-
-#ifndef MAX
-#define MAX(x, y)   (((x) > (y)) ? (x) : (y))
-#endif
-
-#ifndef CLAMP
-#define CLAMP(x, lo, hi)   (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x)))
-#endif
-
-#ifndef UP
-#define UP(x)   (((x) != 0) ? (x) : 1)
-#endif
-
-///////////////////////////////////////////////////////////////////////////////
-
-#ifndef EXT_M_DISABLE
-#define EXT_M_ENABLE
-#endif
-
-#ifndef EXT_F_DISABLE
-#define EXT_F_ENABLE
-#endif
-
-#ifndef XLEN_32
-#ifndef XLEN_64
-#define XLEN_32
-#endif
-#endif
-
-#ifdef XLEN_64
-#define XLEN 64
-#endif
-
-#ifdef XLEN_32
-#define XLEN 32
-#endif
-
-#ifdef EXT_D_ENABLE
-#define FLEN_64
-#else
-#define FLEN_32
-#endif
-
-#ifdef FLEN_64
-#define FLEN 64
-#endif
-
-#ifdef FLEN_32
-#define FLEN 32
-#endif
-
-#ifdef XLEN_64
-#ifdef FLEN_32
-    #define FPU_RV64F
-#endif
-#endif
-
-#ifndef NUM_CLUSTERS
-#define NUM_CLUSTERS 1
-#endif
-
-#ifndef NUM_CORES
-#define NUM_CORES 8
-#endif
-
-#ifndef NUM_WARPS
-#define NUM_WARPS 8
-#endif
-
-#ifndef NUM_THREADS
-#define NUM_THREADS 8
-#endif
-
-#ifndef NUM_BARRIERS
-#define NUM_BARRIERS 8
-#endif
-
-#ifndef SOCKET_SIZE
-#define SOCKET_SIZE MIN(4, NUM_CORES)
-#endif
-#define NUM_SOCKETS UP(NUM_CORES / SOCKET_SIZE)
-
-#ifdef L2_ENABLE
-    #define L2_ENABLED   1
-#else
-    #define L2_ENABLED   0
-#endif
-
-#ifdef L3_ENABLE
-    #define L3_ENABLED   1
-#else
-    #define L3_ENABLED   0
-#endif
-
-#ifdef L1_DISABLE
-    #define ICACHE_DISABLE
-    #define DCACHE_DISABLE
-#endif
-
-#ifndef MEM_BLOCK_SIZE
-#define MEM_BLOCK_SIZE 64
-#endif
-
-#ifndef MEM_ADDR_WIDTH
-#ifdef XLEN_64
-#define MEM_ADDR_WIDTH 48
-#else
-#define MEM_ADDR_WIDTH 32
-#endif
-#endif
-
-#ifndef L1_LINE_SIZE
-#ifdef L1_DISABLE
-#define L1_LINE_SIZE ((L2_ENABLED || L3_ENABLED) ? 4 : MEM_BLOCK_SIZE)
-#else
-#define L1_LINE_SIZE ((L2_ENABLED || L3_ENABLED) ? 16 : MEM_BLOCK_SIZE)
-#endif
-#endif
-
-#ifdef L2_ENABLE
-#define L2_LINE_SIZE MEM_BLOCK_SIZE
-#else
-#define L2_LINE_SIZE L1_LINE_SIZE
-#endif
-
-#ifdef L3_ENABLE
-#define L3_LINE_SIZE MEM_BLOCK_SIZE
-#else
-#define L3_LINE_SIZE L2_LINE_SIZE
-#endif
-
-#ifdef XLEN_64
-
-#ifndef STARTUP_ADDR
-#define STARTUP_ADDR 0x180000000
-#endif
-
-#ifndef STACK_BASE_ADDR
-#define STACK_BASE_ADDR 0x1FF000000
-#endif
-
-#else
-
-#ifndef STARTUP_ADDR
-#define STARTUP_ADDR 0x80000000
-#endif
-
-#ifndef STACK_BASE_ADDR
-#define STACK_BASE_ADDR 0xFF000000
-#endif
-
-#endif
-
-#ifndef SMEM_BASE_ADDR
-#define SMEM_BASE_ADDR STACK_BASE_ADDR
-#endif
-
-#ifndef SMEM_LOG_SIZE
-#define SMEM_LOG_SIZE   19
-#endif
-
-#ifndef IO_BASE_ADDR
-#define IO_BASE_ADDR (SMEM_BASE_ADDR + (1 << SMEM_LOG_SIZE))
-#endif
-
-#ifndef IO_COUT_ADDR
-#define IO_COUT_ADDR IO_BASE_ADDR
-#endif
-#define IO_COUT_SIZE MEM_BLOCK_SIZE
-
-#ifndef IO_CSR_ADDR
-#define IO_CSR_ADDR (IO_COUT_ADDR + IO_COUT_SIZE)
-#endif
-#define IO_CSR_SIZE (4 * 64 * NUM_CORES * NUM_CLUSTERS)
-
-#ifndef STACK_LOG2_SIZE
-#define STACK_LOG2_SIZE 13
-#endif
-#define STACK_SIZE (1 << STACK_LOG2_SIZE)
-
-#define RESET_DELAY 8
-
-#ifndef STALL_TIMEOUT
-#define STALL_TIMEOUT (100000 * (1 ** (L2_ENABLED + L3_ENABLED)))
-#endif
-
-#ifndef SV_DPI
-#define DPI_DISABLE
-#endif
-
-#ifndef FPU_FPNEW
-#ifndef FPU_DSP
-#ifndef FPU_DPI
-#ifndef SYNTHESIS
-#ifndef DPI_DISABLE
-#define FPU_DPI
-#else
-#define FPU_DSP
-#endif
-#else
-#define FPU_DSP
-#endif
-#endif
-#endif
-#endif
-
-#ifndef SYNTHESIS
-#ifndef DPI_DISABLE
-#define IMUL_DPI
-#define IDIV_DPI
-#endif
-#endif
-
-#ifndef DEBUG_LEVEL
-#define DEBUG_LEVEL 3
-#endif
-
-// Pipeline Configuration /////////////////////////////////////////////////////
-
-// Issue width
-#ifndef ISSUE_WIDTH
-#define ISSUE_WIDTH     NUM_WARPS
-#endif
-
-// Number of ALU units
-#ifndef NUM_ALU_LANES
-#define NUM_ALU_LANES   NUM_THREADS
-#endif
-#ifndef NUM_ALU_BLOCKS
-#define NUM_ALU_BLOCKS  4
-#endif
-
-// Number of FPU units
-#ifndef NUM_FPU_LANES
-#define NUM_FPU_LANES   NUM_THREADS
-#endif
-#ifndef NUM_FPU_BLOCKS
-#define NUM_FPU_BLOCKS  2
-#endif
-
-// Number of LSU units
-#ifndef NUM_LSU_LANES
-#define NUM_LSU_LANES   NUM_THREADS
-#endif
-
-// Number of SFU units
-#ifndef NUM_SFU_LANES
-#define NUM_SFU_LANES   MIN(NUM_THREADS, 4)
-#endif
-
-// Size of Instruction Buffer
-#ifndef IBUF_SIZE
-#define IBUF_SIZE   (4 * ISSUE_WIDTH)
-#endif
-
-// Size of LSU Request Queue
-#ifndef LSUQ_SIZE
-#define LSUQ_SIZE   (4 * NUM_WARPS * (NUM_THREADS / NUM_LSU_LANES))
-#endif
-
-// LSU Duplicate Address Check
-#ifndef LSU_DUP_DISABLE
-#define LSU_DUP_ENABLE
-#endif
-#ifdef LSU_DUP_ENABLE
-#define LSU_DUP_ENABLED 1
-#else
-#define LSU_DUP_ENABLED 0
-#endif
-
-#ifdef GBAR_ENABLE
-#define GBAR_ENABLED 1
-#else
-#define GBAR_ENABLED 0
-#endif
-
-#ifndef LATENCY_IMUL
-#ifdef VIVADO
-#define LATENCY_IMUL 4
-#endif
-#ifdef QUARTUS
-#define LATENCY_IMUL 3
-#endif
-#ifndef LATENCY_IMUL
-#define LATENCY_IMUL 4
-#endif
-#endif
-
-// Floating-Point Units ///////////////////////////////////////////////////////
-
-// Size of FPU Request Queue
-#ifndef FPUQ_SIZE
-#define FPUQ_SIZE (2 * (NUM_THREADS / NUM_FPU_LANES))
-#endif
-
-// FNCP Latency
-#ifndef LATENCY_FNCP
-#define LATENCY_FNCP 2
-#endif
-
-// FMA Latency
-#ifndef LATENCY_FMA
-#ifdef FPU_DPI
-#define LATENCY_FMA 4    
-#endif
-#ifdef FPU_FPNEW
-#define LATENCY_FMA 4    
-#endif
-#ifdef FPU_DSP
-#ifdef QUARTUS
-#define LATENCY_FMA 4
-#endif
-#ifdef VIVADO
-#define LATENCY_FMA 16    
-#endif
-#ifndef LATENCY_FMA
-#define LATENCY_FMA 4    
-#endif
-#endif
-#endif
-
-// FDIV Latency
-#ifndef LATENCY_FDIV
-#ifdef FPU_DPI
-#define LATENCY_FDIV 15    
-#endif
-#ifdef FPU_FPNEW
-#define LATENCY_FDIV 16    
-#endif
-#ifdef FPU_DSP
-#ifdef QUARTUS
-#define LATENCY_FDIV 15
-#endif
-#ifdef VIVADO
-#define LATENCY_FDIV 28    
-#endif
-#ifndef LATENCY_FDIV
-#define LATENCY_FDIV 16
-#endif
-#endif
-#endif
-
-// FSQRT Latency
-#ifndef LATENCY_FSQRT
-#ifdef FPU_DPI
-#define LATENCY_FSQRT 10    
-#endif
-#ifdef FPU_FPNEW
-#define LATENCY_FSQRT 16    
-#endif
-#ifdef FPU_DSP
-#ifdef QUARTUS
-#define LATENCY_FSQRT 10
-#endif
-#ifdef VIVADO
-#define LATENCY_FSQRT 28    
-#endif
-#ifndef LATENCY_FSQRT
-#define LATENCY_FSQRT 16    
-#endif
-#endif
-#endif
-
-// FCVT Latency
-#ifndef LATENCY_FCVT
-#define LATENCY_FCVT 5
-#endif
-
-// Icache Configurable Knobs //////////////////////////////////////////////////
-
-// Cache Enable
-#ifndef ICACHE_DISABLE
-#define ICACHE_ENABLE
-#endif
-#ifdef ICACHE_ENABLE
-    #define ICACHE_ENABLED 1
-#else
-    #define ICACHE_ENABLED 0
-    #define NUM_ICACHES 0
-#endif
-
-// Number of Cache Units
-#ifndef NUM_ICACHES
-#define NUM_ICACHES UP(SOCKET_SIZE / 4)
-#endif
-
-// Cache Size
-#ifndef ICACHE_SIZE
-#define ICACHE_SIZE 16384
-#endif
-
-// Core Response Queue Size
-#ifndef ICACHE_CRSQ_SIZE
-#define ICACHE_CRSQ_SIZE 2
-#endif
-
-// Miss Handling Register Size
-#ifndef ICACHE_MSHR_SIZE
-#define ICACHE_MSHR_SIZE 16
-#endif
-
-// Memory Request Queue Size
-#ifndef ICACHE_MREQ_SIZE
-#define ICACHE_MREQ_SIZE 4
-#endif
-
-// Memory Response Queue Size
-#ifndef ICACHE_MRSQ_SIZE
-#define ICACHE_MRSQ_SIZE 0
-#endif
-
-// Number of Associative Ways
-#ifndef ICACHE_NUM_WAYS
-#define ICACHE_NUM_WAYS 1
-#endif
-
-// Dcache Configurable Knobs //////////////////////////////////////////////////
-
-// Cache Enable
-#ifndef DCACHE_DISABLE
-#define DCACHE_ENABLE
-#endif
-#ifdef DCACHE_ENABLE
-    #define DCACHE_ENABLED 1
-#else
-    #define DCACHE_ENABLED 0
-    #define NUM_DCACHES 0
-    #define DCACHE_NUM_BANKS 1
-#endif
-
-// Number of Cache Units
-#ifndef NUM_DCACHES
-#define NUM_DCACHES UP(SOCKET_SIZE / 4)
-#endif
-
-// Cache Size
-#ifndef DCACHE_SIZE
-#define DCACHE_SIZE 16384
-#endif
-
-// Number of Banks
-#ifndef DCACHE_NUM_BANKS
-#define DCACHE_NUM_BANKS NUM_LSU_LANES
-#endif
-
-// Core Response Queue Size
-#ifndef DCACHE_CRSQ_SIZE
-#define DCACHE_CRSQ_SIZE 2
-#endif
-
-// Miss Handling Register Size
-#ifndef DCACHE_MSHR_SIZE
-#define DCACHE_MSHR_SIZE 8
-#endif
-
-// Memory Request Queue Size
-#ifndef DCACHE_MREQ_SIZE
-#define DCACHE_MREQ_SIZE 4
-#endif
-
-// Memory Response Queue Size
-#ifndef DCACHE_MRSQ_SIZE
-#define DCACHE_MRSQ_SIZE 0
-#endif
-
-// Number of Associative Ways
-#ifndef DCACHE_NUM_WAYS
-#define DCACHE_NUM_WAYS 1
-#endif
-
-// SM Configurable Knobs //////////////////////////////////////////////////////
-
-#ifndef SM_DISABLE
-#define SM_ENABLE
-#endif
-
-#ifdef SM_ENABLE
-    #define SM_ENABLED   1
-#else
-    #define SM_ENABLED   0
-    #define SMEM_NUM_BANKS 1
-#endif
-
-// Number of Banks
-#ifndef SMEM_NUM_BANKS
-#define SMEM_NUM_BANKS (NUM_LSU_LANES)
-#endif
-
-// L2cache Configurable Knobs /////////////////////////////////////////////////
-
-// Cache Size
-#ifndef L2_CACHE_SIZE
-#ifdef ALTERA_S10
-#define L2_CACHE_SIZE 2097152
-#else
-#define L2_CACHE_SIZE 1048576
-#endif
-#endif
-
-// Number of Banks
-#ifndef L2_NUM_BANKS
-#define L2_NUM_BANKS MIN(4, NUM_SOCKETS)
-#endif
-
-// Core Response Queue Size
-#ifndef L2_CRSQ_SIZE
-#define L2_CRSQ_SIZE 2
-#endif
-
-// Miss Handling Register Size
-#ifndef L2_MSHR_SIZE
-#define L2_MSHR_SIZE 16
-#endif
-
-// Memory Request Queue Size
-#ifndef L2_MREQ_SIZE
-#define L2_MREQ_SIZE 4
-#endif
-
-// Memory Response Queue Size
-#ifndef L2_MRSQ_SIZE
-#define L2_MRSQ_SIZE 0
-#endif
-
-// Number of Associative Ways
-#ifndef L2_NUM_WAYS
-#define L2_NUM_WAYS 2
-#endif
-
-// L3cache Configurable Knobs /////////////////////////////////////////////////
-
-// Cache Size
-#ifndef L3_CACHE_SIZE
-#ifdef ALTERA_S10
-#define L3_CACHE_SIZE 2097152
-#else
-#define L3_CACHE_SIZE 1048576
-#endif
-#endif
-
-// Number of Banks
-#ifndef L3_NUM_BANKS
-#define L3_NUM_BANKS MIN(4, NUM_CLUSTERS)
-#endif
-
-// Core Response Queue Size
-#ifndef L3_CRSQ_SIZE
-#define L3_CRSQ_SIZE 2
-#endif
-
-// Miss Handling Register Size
-#ifndef L3_MSHR_SIZE
-#define L3_MSHR_SIZE 16
-#endif
-
-// Memory Request Queue Size
-#ifndef L3_MREQ_SIZE
-#define L3_MREQ_SIZE 4
-#endif
-
-// Memory Response Queue Size
-#ifndef L3_MRSQ_SIZE
-#define L3_MRSQ_SIZE 0
-#endif
-
-// Number of Associative Ways
-#ifndef L3_NUM_WAYS
-#define L3_NUM_WAYS 4
-#endif
-
-// ISA Extensions /////////////////////////////////////////////////////////////
-
-#ifdef EXT_A_ENABLE
-    #define EXT_A_ENABLED   1
-#else
-    #define EXT_A_ENABLED   0
-#endif
-
-#ifdef EXT_C_ENABLE
-    #define EXT_C_ENABLED   1
-#else
-    #define EXT_C_ENABLED   0
-#endif
-
-#ifdef EXT_D_ENABLE
-    #define EXT_D_ENABLED   1
-#else
-    #define EXT_D_ENABLED   0
-#endif
-
-#ifdef EXT_F_ENABLE
-    #define EXT_F_ENABLED   1
-#else
-    #define EXT_F_ENABLED   0
-#endif
-
-#ifdef EXT_M_ENABLE
-    #define EXT_M_ENABLED   1
-#else
-    #define EXT_M_ENABLED   0
-#endif
-
-#define ISA_STD_A           0
-#define ISA_STD_C           2
-#define ISA_STD_D           3
-#define ISA_STD_E           4
-#define ISA_STD_F           5
-#define ISA_STD_H           7
-#define ISA_STD_I           8
-#define ISA_STD_N           13
-#define ISA_STD_Q           16
-#define ISA_STD_S           18
-#define ISA_STD_U           20
-
-#define ISA_EXT_ICACHE      0
-#define ISA_EXT_DCACHE      1
-#define ISA_EXT_L2CACHE     2
-#define ISA_EXT_L3CACHE     3
-#define ISA_EXT_SMEM        4
-
-#define MISA_EXT  (ICACHE_ENABLED  << ISA_EXT_ICACHE) \
-                | (DCACHE_ENABLED  << ISA_EXT_DCACHE) \
-                | (L2_ENABLED      << ISA_EXT_L2CACHE) \
-                | (L3_ENABLED      << ISA_EXT_L3CACHE) \
-                | (SM_ENABLED      << ISA_EXT_SMEM)
-
-#define MISA_STD  (EXT_A_ENABLED <<  0) /* A - Atomic Instructions extension */ \
-                | (0 <<  1) /* B - Tentatively reserved for Bit operations extension */ \
-                | (EXT_C_ENABLED <<  2) /* C - Compressed extension */ \
-                | (EXT_D_ENABLED <<  3) /* D - Double precsision floating-point extension */ \
-                | (0 <<  4) /* E - RV32E base ISA */ \
-                | (EXT_F_ENABLED << 5) /* F - Single precsision floating-point extension */ \
-                | (0 <<  6) /* G - Additional standard extensions present */ \
-                | (0 <<  7) /* H - Hypervisor mode implemented */ \
-                | (1 <<  8) /* I - RV32I/64I/128I base ISA */ \
-                | (0 <<  9) /* J - Reserved */ \
-                | (0 << 10) /* K - Reserved */ \
-                | (0 << 11) /* L - Tentatively reserved for Bit operations extension */ \
-                | (EXT_M_ENABLED << 12) /* M - Integer Multiply/Divide extension */ \
-                | (0 << 13) /* N - User level interrupts supported */ \
-                | (0 << 14) /* O - Reserved */ \
-                | (0 << 15) /* P - Tentatively reserved for Packed-SIMD extension */ \
-                | (0 << 16) /* Q - Quad-precision floating-point extension */ \
-                | (0 << 17) /* R - Reserved */ \
-                | (0 << 18) /* S - Supervisor mode implemented */ \
-                | (0 << 19) /* T - Tentatively reserved for Transactional Memory extension */ \
-                | (1 << 20) /* U - User mode implemented */ \
-                | (0 << 21) /* V - Tentatively reserved for Vector extension */ \
-                | (0 << 22) /* W - Reserved */ \
-                | (1 << 23) /* X - Non-standard extensions present */ \
-                | (0 << 24) /* Y - Reserved */ \
-                | (0 << 25) /* Z - Reserved */
-
-// Device identification //////////////////////////////////////////////////////
-
-#define VENDOR_ID           0
-#define ARCHITECTURE_ID     0
-#define IMPLEMENTATION_ID   0
-
-#endif // VX_CONFIG_VH
-

hw/dpi/float_dpi.cpp

@@ -1,340 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#include <stdio.h>
-#include <math.h>
-#include <unordered_map>
-#include <vector>
-#include <mutex>
-#include <iostream>
-#include <rvfloats.h>
-#include <util.h>
-#include "svdpi.h"
-#include "verilated_vpi.h"
-#include "VX_config.h"
-
-extern "C" {
-  void dpi_fadd(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fsub(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fmul(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fnmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fnmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-
-  void dpi_fdiv(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_fsqrt(bool enable, int dst_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-
-  void dpi_ftoi(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_ftou(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_itof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_utof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags);
-  void dpi_f2f(bool enable, int dst_fmt, int64_t a, int64_t* result);
-  
-  void dpi_fclss(bool enable, int dst_fmt, int64_t a, int64_t* result);
-  void dpi_fsgnj(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result);
-  void dpi_fsgnjn(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result);
-  void dpi_fsgnjx(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result);
-
-  void dpi_flt(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags);
-  void dpi_fle(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags);
-  void dpi_feq(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags);
-  void dpi_fmin(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags);
-  void dpi_fmax(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags);
-}
-
-inline uint64_t nan_box(uint32_t value) {
-#ifdef FPU_RV64F
-  return value | 0xffffffff00000000;
-#else 
-  return value;
-#endif
-}
-
-inline bool is_nan_boxed(uint64_t value) {
-#ifdef FPU_RV64F
-  return (uint32_t(value >> 32) == 0xffffffff);
-#else
-  __unused (value);
-  return true;
-#endif
-}
-
-inline int64_t check_boxing(int64_t a) {  
-  if (!is_nan_boxed(a)) {
-    return nan_box(0x7fc00000); // NaN
-  }
-  return a;
-}
-
-void dpi_fadd(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    *result = rv_fadd_d(a, b, (*frm & 0x7), fflags);
-  } else {
-    *result = nan_box(rv_fadd_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fsub(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    *result = rv_fsub_d(a, b, (*frm & 0x7), fflags);
-  } else {
-    *result = nan_box(rv_fsub_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fmul(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fmul_d(a, b, (*frm & 0x7), fflags); 
-  } else {
-    *result = nan_box(rv_fmul_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fmadd_d(a, b, c, (*frm & 0x7), fflags);
-  } else {
-    *result = nan_box(rv_fmadd_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fmsub_d(a, b, c, (*frm & 0x7), fflags);
-  } else {
-    *result = nan_box(rv_fmsub_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fnmadd(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fnmadd_d(a, b, c, (*frm & 0x7), fflags);
-  } else {
-    *result = nan_box(rv_fnmadd_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fnmsub(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t c, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fnmsub_d(a, b, c, (*frm & 0x7), fflags);
-  } else {
-    *result = nan_box(rv_fnmsub_s(check_boxing(a), check_boxing(b), check_boxing(c), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fdiv(bool enable, int dst_fmt, int64_t a, int64_t b, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fdiv_d(a, b, (*frm & 0x7), fflags); 
-  } else {
-    *result = nan_box(rv_fdiv_s(check_boxing(a), check_boxing(b), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_fsqrt(bool enable, int dst_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fsqrt_d(a, (*frm & 0x7), fflags); 
-  } else {
-    *result = nan_box(rv_fsqrt_s(check_boxing(a), (*frm & 0x7), fflags));
-  }
-}
-
-void dpi_ftoi(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    if (src_fmt) { 
-      *result = rv_ftol_d(a, (*frm & 0x7), fflags);
-    } else {
-      *result = rv_ftol_s(check_boxing(a), (*frm & 0x7), fflags);
-    }
-  } else {    
-    if (src_fmt) { 
-      *result = sext<uint64_t>(rv_ftoi_d(a, (*frm & 0x7), fflags), 32);
-    } else {
-      *result = sext<uint64_t>(rv_ftoi_s(check_boxing(a), (*frm & 0x7), fflags), 32);
-    }
-  }
-}
-
-void dpi_ftou(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    if (src_fmt) { 
-      *result = rv_ftolu_d(a, (*frm & 0x7), fflags);
-    } else {
-      *result = rv_ftolu_s(check_boxing(a), (*frm & 0x7), fflags);
-    }
-  } else {    
-    if (src_fmt) { 
-      *result = sext<uint64_t>(rv_ftou_d(a, (*frm & 0x7), fflags), 32);
-    } else {
-      *result = sext<uint64_t>(rv_ftou_s(check_boxing(a), (*frm & 0x7), fflags), 32); 
-    }
-  }
-}
-
-void dpi_itof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    if (src_fmt) { 
-      *result = rv_ltof_d(a, (*frm & 0x7), fflags);
-    } else { 
-      *result = rv_itof_d(a, (*frm & 0x7), fflags);
-    }
-  } else {
-    if (src_fmt) { 
-      *result = nan_box(rv_ltof_s(a, (*frm & 0x7), fflags)); 
-    } else { 
-      *result = nan_box(rv_itof_s(a, (*frm & 0x7), fflags)); 
-    }
-  }
-}
-
-void dpi_utof(bool enable, int dst_fmt, int src_fmt, int64_t a, const svBitVecVal* frm, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    if (src_fmt) { 
-      *result = rv_lutof_d(a, (*frm & 0x7), fflags);
-    } else { 
-      *result = rv_utof_d(a, (*frm & 0x7), fflags);
-    }
-  } else {
-    if (src_fmt) { 
-      *result = nan_box(rv_lutof_s(a, (*frm & 0x7), fflags));
-    } else { 
-      *result = nan_box(rv_utof_s(a, (*frm & 0x7), fflags));
-    }
-  }
-}
-
-void dpi_f2f(bool enable, int dst_fmt, int64_t a, int64_t* result) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    *result = rv_ftod((int32_t)check_boxing(a));
-  } else {
-    *result = nan_box(rv_dtof(a));
-  }
-}
-
-void dpi_fclss(bool enable, int dst_fmt, int64_t a, int64_t* result) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fclss_d(a); 
-  } else { 
-    *result = rv_fclss_s(check_boxing(a)); 
-  }
-}
-
-void dpi_fsgnj(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fsgnj_d(a, b); 
-  } else {
-    *result = nan_box(rv_fsgnj_s(check_boxing(a), check_boxing(b)));
-  }
-}
-
-void dpi_fsgnjn(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fsgnjn_d(a, b); 
-  } else {
-    *result = nan_box(rv_fsgnjn_s(check_boxing(a), check_boxing(b)));
-  }
-}
-
-void dpi_fsgnjx(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fsgnjx_d(a, b); 
-  } else {
-    *result = nan_box(rv_fsgnjx_s(check_boxing(a), check_boxing(b)));
-  }
-}
-
-void dpi_flt(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) {
-    *result = rv_flt_d(a, b, fflags); 
-  } else {
-    *result = rv_flt_s(check_boxing(a), check_boxing(b), fflags);
-  }
-}
-
-void dpi_fle(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fle_d(a, b, fflags); 
-  } else {
-    *result = rv_fle_s(check_boxing(a), check_boxing(b), fflags);
-  }
-}
-
-void dpi_feq(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_feq_d(a, b, fflags); 
-  } else {
-    *result = rv_feq_s(check_boxing(a), check_boxing(b), fflags);
-  }
-}
-
-void dpi_fmin(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fmin_d(a, b, fflags); 
-  } else {
-    *result = nan_box(rv_fmin_s(check_boxing(a), check_boxing(b), fflags));
-  }
-}
-
-void dpi_fmax(bool enable, int dst_fmt, int64_t a, int64_t b, int64_t* result, svBitVecVal* fflags) {
-  if (!enable) 
-    return;
-  if (dst_fmt) { 
-    *result = rv_fmax_d(a, b, fflags); 
-  } else {
-    *result = nan_box(rv_fmax_s(check_boxing(a), check_boxing(b), fflags));
-  }
-}

hw/dpi/float_dpi.vh

@@ -1,47 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef FLOAT_DPI_VH
-`define FLOAT_DPI_VH
-
-`include "VX_config.vh"
-
-import "DPI-C" function void dpi_fadd(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fsub(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fmul(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fmadd(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fmsub(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fnmadd(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fnmsub(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-
-import "DPI-C" function void dpi_fdiv(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fsqrt(input logic enable, input int dst_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-
-import "DPI-C" function void dpi_ftoi(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_ftou(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_itof(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_utof(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_f2f(input logic enable, input int dst_fmt, input longint a, output longint result);
-
-import "DPI-C" function void dpi_fclss(input logic enable, input int dst_fmt, input longint a, output longint result);
-import "DPI-C" function void dpi_fsgnj(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result);
-import "DPI-C" function void dpi_fsgnjn(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result);
-import "DPI-C" function void dpi_fsgnjx(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result);
-
-import "DPI-C" function void dpi_flt(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fle(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_feq(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fmin(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags);
-import "DPI-C" function void dpi_fmax(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags);
-
-`endif

hw/dpi/util_dpi.cpp

@@ -1,232 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#include <stdio.h>
-#include <math.h>
-#include <unordered_map>
-#include <vector>
-#include <mutex>
-#include <iostream>
-
-#include "svdpi.h"
-#include "verilated_vpi.h"
-
-#include "uuid_gen.h"
-
-#ifdef XLEN_64
-#define iword_t   int64_t
-#define uword_t   uint64_t
-#define idword_t  __int128_t
-#define udword_t  __uint128_t
-#else
-#define iword_t   int32_t
-#define uword_t   uint32_t
-#define idword_t  int64_t
-#define udword_t  uint64_t
-#endif
-
-#ifndef DEBUG_LEVEL
-#define DEBUG_LEVEL 3
-#endif
-
-extern "C" {
-  void dpi_imul(bool enable, bool is_signed_a, bool is_signed_b, iword_t a, iword_t b, iword_t* resultl, iword_t* resulth);
-  void dpi_idiv(bool enable, bool is_signed, iword_t a, iword_t b, iword_t* quotient, iword_t* remainder);
-
-  int dpi_register();
-  void dpi_assert(int inst, bool cond, int delay);
-
-  void dpi_trace(int level, const char* format, ...);
-  void dpi_trace_start();
-  void dpi_trace_stop();
-
-  uint64_t dpi_uuid_gen(bool reset, int wid, uint64_t PC);
-}
-
-bool sim_trace_enabled();
-void sim_trace_enable(bool enable);
-
-class ShiftRegister {
-public:
-  ShiftRegister() : init_(false), depth_(0) {}
-
-  void ensure_init(int depth) {
-    if (!init_) {
-      buffer_.resize(depth);
-      init_  = true;
-      depth_ = depth;
-    }
-  }
-
-  void push(int value, bool enable) {
-    if (!enable)
-      return;      
-    for (unsigned i = 0; i < depth_-1; ++i) {
-      buffer_[i] = buffer_[i+1];
-    }
-    buffer_[depth_-1] = value;
-  }
-
-  int top() const {
-    return buffer_[0];
-  }
-
-private:
-
-  std::vector<int> buffer_;
-  bool init_;
-  unsigned depth_;  
-};
-
-class Instances {
-public:
-  ShiftRegister& get(int inst) {
-    return instances_.at(inst);
-  }
-
-  int allocate() {
-    mutex_.lock();   
-    int inst = instances_.size();
-    instances_.resize(inst + 1); 
-    mutex_.unlock();
-    return inst;
-  }
-
-private:
-  std::vector<ShiftRegister> instances_;
-  std::mutex mutex_;
-};
-
-Instances instances;
-
-int dpi_register() {
-  return instances.allocate();
-}
-
-void dpi_assert(int inst, bool cond, int delay) {
-  ShiftRegister& sr = instances.get(inst);
-
-  sr.ensure_init(delay);
-  sr.push(!cond, 1);
-
-  auto status = sr.top();
-  if (status) {
-    printf("delayed assertion at %s!\n", svGetNameFromScope(svGetScope()));
-    std::abort();
-  }
-}
-
-///////////////////////////////////////////////////////////////////////////////
-
-void dpi_imul(bool enable, bool is_signed_a, bool is_signed_b, iword_t a, iword_t b, iword_t* resultl, iword_t* resulth) {
-  if (!enable)
-    return;
-  udword_t first  = *(uword_t*)&a;
-  udword_t second = *(uword_t*)&b;
-
-  udword_t mask = udword_t(-1) << (8 * sizeof(iword_t));
-    
-  if (is_signed_a && a < 0) {
-    first |= mask;
-  }
-
-  if (is_signed_b && b < 0) {
-    second |= mask;
-  }
-
-  udword_t result;
-  if (is_signed_a || is_signed_b) {
-    result = idword_t(first) * idword_t(second);
-  } else {
-    result = first * second;
-  }
-
-  *resultl = iword_t(result);
-  *resulth = iword_t(result >> (8 * sizeof(iword_t)));
-}
-
-void dpi_idiv(bool enable, bool is_signed, iword_t a, iword_t b, iword_t* quotient, iword_t* remainder) {
-  if (!enable)
-    return;
-
-  uword_t dividen = a;
-  uword_t divisor = b;
-
-  auto inf_neg = uword_t(1) << (8 * sizeof(iword_t) - 1);
-
-  if (is_signed) {
-    if (b == 0) {
-      *quotient  = -1;
-      *remainder = dividen;
-    } else if (dividen == inf_neg && divisor == -1) {
-      *remainder = 0;
-      *quotient  = dividen;
-    } else { 
-      *quotient  = (iword_t)dividen / (iword_t)divisor;
-      *remainder = (iword_t)dividen % (iword_t)divisor;      
-    }
-  } else {    
-    if (b == 0) {
-      *quotient  = -1;
-      *remainder = dividen;
-    } else {
-      *quotient  = dividen / divisor;
-      *remainder = dividen % divisor;
-    }
-  }
-}
-
-///////////////////////////////////////////////////////////////////////////////
-
-void dpi_trace(int level, const char* format, ...) { 
-  if (level > DEBUG_LEVEL)
-    return;
-  if (!sim_trace_enabled())
-    return;
-  va_list va;
-	va_start(va, format);  
-	vprintf(format, va);
-	va_end(va);		  
-}
-
-void dpi_trace_start() { 
-  sim_trace_enable(true);
-}
-
-void dpi_trace_stop() { 
-  sim_trace_enable(false);
-}
-
-///////////////////////////////////////////////////////////////////////////////
-
-std::unordered_map<uint32_t, std::shared_ptr<vortex::UUIDGenerator>> g_uuid_gens;
-
-uint64_t dpi_uuid_gen(bool reset, int wid, uint64_t PC) {
-  if (reset) {
-    g_uuid_gens.clear();
-    return 0;
-  }
-  std::shared_ptr<vortex::UUIDGenerator> uuid_gen;
-  auto it = g_uuid_gens.find(wid);
-  if (it == g_uuid_gens.end()) {
-    uuid_gen = std::make_shared<vortex::UUIDGenerator>();
-    g_uuid_gens.emplace(wid, uuid_gen);
-  } else {
-    uuid_gen = it->second;
-  }
-  uint32_t instr_uuid = uuid_gen->get_uuid(PC);
-  uint32_t instr_id  = instr_uuid & 0xffff;
-  uint32_t instr_ref = instr_uuid >> 16;
-  uint64_t uuid = (uint64_t(instr_ref) << 32) | (wid << 16) | instr_id;
-  return uuid;
-}

hw/dpi/util_dpi.vh

@@ -1,37 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef UTIL_DPI_VH
-`define UTIL_DPI_VH
-
-`include "VX_config.vh"
-
-`ifdef XLEN_64
-`define INT_TYPE longint
-`else
-`define INT_TYPE int
-`endif
-
-import "DPI-C" function void dpi_imul(input logic enable, input logic is_signed_a, input logic is_signed_b, input `INT_TYPE a, input `INT_TYPE b, output `INT_TYPE resultl, output `INT_TYPE resulth);
-import "DPI-C" function void dpi_idiv(input logic enable, input logic is_signed, input `INT_TYPE a, input `INT_TYPE b, output `INT_TYPE quotient, output `INT_TYPE remainder);
-
-import "DPI-C" function int dpi_register();
-import "DPI-C" function void dpi_assert(int inst, input logic cond, input int delay);
-
-import "DPI-C" function void dpi_trace(input int level, input string format /*verilator sformat*/);
-import "DPI-C" function void dpi_trace_start();
-import "DPI-C" function void dpi_trace_stop();
-
-import "DPI-C" function longint dpi_uuid_gen(input logic reset, input int wid, input longint PC);
-
-`endif

hw/rtl/VX_cluster.sv

@@ -1,171 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_cluster import VX_gpu_pkg::*; #(
-    parameter CLUSTER_ID = 0
-) ( 
-    `SCOPE_IO_DECL
-
-    // Clock
-    input  wire                 clk,
-    input  wire                 reset,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave        mem_perf_if,
-`endif
-
-    // DCRs
-    VX_dcr_bus_if.slave         dcr_bus_if,
-
-    // Memory
-    VX_mem_bus_if.master        mem_bus_if,
-
-    // simulation helper signals
-    output wire                 sim_ebreak,
-    output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
-
-    // Status
-    output wire                 busy
-);
-
-`ifdef SCOPE
-    localparam scope_socket = 0;
-    `SCOPE_IO_SWITCH (scope_socket + `NUM_SOCKETS);
-`endif    
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if mem_perf_tmp_if();    
-    assign mem_perf_tmp_if.icache  = 'x;
-    assign mem_perf_tmp_if.dcache  = 'x;
-    assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
-    assign mem_perf_tmp_if.smem    = 'x;
-    assign mem_perf_tmp_if.mem     = mem_perf_if.mem;
-`endif    
-
-`ifdef GBAR_ENABLE
-
-    VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS]();
-    VX_gbar_bus_if gbar_bus_if();
-
-    `RESET_RELAY (gbar_reset, reset);
-
-    VX_gbar_arb #(
-        .NUM_REQS (`NUM_SOCKETS),
-        .OUT_REG  ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
-    ) gbar_arb (
-        .clk        (clk),
-        .reset      (gbar_reset),
-        .bus_in_if  (per_socket_gbar_bus_if),
-        .bus_out_if (gbar_bus_if)
-    );
-
-    VX_gbar_unit #(
-        .INSTANCE_ID ($sformatf("gbar%0d", CLUSTER_ID))
-    ) gbar_unit (
-        .clk         (clk),
-        .reset       (gbar_reset),
-        .gbar_bus_if (gbar_bus_if)
-    );
-
-`endif
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (`L1_LINE_SIZE),
-        .TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
-    ) per_socket_mem_bus_if[`NUM_SOCKETS]();
-
-    `RESET_RELAY (l2_reset, reset);
-
-    VX_cache_wrap #(
-        .INSTANCE_ID    ("l2cache"),
-        .CACHE_SIZE     (`L2_CACHE_SIZE),
-        .LINE_SIZE      (`L2_LINE_SIZE),
-        .NUM_BANKS      (`L2_NUM_BANKS),
-        .NUM_WAYS       (`L2_NUM_WAYS),
-        .WORD_SIZE      (L2_WORD_SIZE),
-        .NUM_REQS       (L2_NUM_REQS),
-        .CRSQ_SIZE      (`L2_CRSQ_SIZE),
-        .MSHR_SIZE      (`L2_MSHR_SIZE),
-        .MRSQ_SIZE      (`L2_MRSQ_SIZE),
-        .MREQ_SIZE      (`L2_MREQ_SIZE),
-        .TAG_WIDTH      (L2_TAG_WIDTH),
-        .WRITE_ENABLE   (1),
-        .UUID_WIDTH     (`UUID_WIDTH),  
-        .CORE_OUT_REG   (2),
-        .MEM_OUT_REG    (2),
-        .NC_ENABLE      (1),
-        .PASSTHRU       (!`L2_ENABLED)
-    ) l2cache (
-        .clk            (clk),
-        .reset          (l2_reset),
-    `ifdef PERF_ENABLE
-        .cache_perf     (mem_perf_tmp_if.l2cache),
-    `endif
-        .core_bus_if    (per_socket_mem_bus_if),
-        .mem_bus_if     (mem_bus_if)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    wire [`NUM_SOCKETS-1:0] per_socket_sim_ebreak;
-    wire [`NUM_SOCKETS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_socket_sim_wb_value;
-    assign sim_ebreak = per_socket_sim_ebreak[0];
-    assign sim_wb_value = per_socket_sim_wb_value[0];
-    `UNUSED_VAR (per_socket_sim_ebreak)
-    `UNUSED_VAR (per_socket_sim_wb_value)
-
-    VX_dcr_bus_if socket_dcr_bus_tmp_if();
-    assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
-    assign socket_dcr_bus_tmp_if.write_addr  = dcr_bus_if.write_addr;
-    assign socket_dcr_bus_tmp_if.write_data  = dcr_bus_if.write_data;
-
-    wire [`NUM_SOCKETS-1:0] per_socket_busy;
-
-    `BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1));
-
-    // Generate all sockets
-    for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
-
-        `RESET_RELAY (socket_reset, reset);
-
-        VX_socket #(
-            .SOCKET_ID ((CLUSTER_ID * `NUM_SOCKETS) + i)
-        ) socket (
-            `SCOPE_IO_BIND  (scope_socket+i)
-
-            .clk            (clk),
-            .reset          (socket_reset),
-
-        `ifdef PERF_ENABLE
-            .mem_perf_if    (mem_perf_tmp_if),
-        `endif
-            
-            .dcr_bus_if     (socket_dcr_bus_if),
-
-            .mem_bus_if     (per_socket_mem_bus_if[i]),
-
-        `ifdef GBAR_ENABLE
-            .gbar_bus_if    (per_socket_gbar_bus_if[i]),
-        `endif
-
-            .sim_ebreak     (per_socket_sim_ebreak[i]),
-            .sim_wb_value   (per_socket_sim_wb_value[i]),
-            .busy           (per_socket_busy[i])
-        );
-    end
-
-    `BUFFER_EX(busy, (| per_socket_busy), 1'b1, (`NUM_SOCKETS > 1));
-
-endmodule

hw/rtl/VX_config.vh

@@ -1,679 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_CONFIG_VH
-`define VX_CONFIG_VH
-
-`ifndef MIN
-`define MIN(x, y)   (((x) < (y)) ? (x) : (y))
-`endif
-
-`ifndef MAX
-`define MAX(x, y)   (((x) > (y)) ? (x) : (y))
-`endif
-
-`ifndef CLAMP
-`define CLAMP(x, lo, hi)   (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x)))
-`endif
-
-`ifndef UP
-`define UP(x)   (((x) != 0) ? (x) : 1)
-`endif
-
-///////////////////////////////////////////////////////////////////////////////
-
-`ifndef EXT_M_DISABLE
-`define EXT_M_ENABLE
-`endif
-
-`ifndef EXT_F_DISABLE
-`define EXT_F_ENABLE
-`endif
-
-`ifndef XLEN_32
-`ifndef XLEN_64
-`define XLEN_32
-`endif
-`endif
-
-`ifdef XLEN_64
-`define XLEN 64
-`endif
-
-`ifdef XLEN_32
-`define XLEN 32
-`endif
-
-`ifdef EXT_D_ENABLE
-`define FLEN_64
-`else
-`define FLEN_32
-`endif
-
-`ifdef FLEN_64
-`define FLEN 64
-`endif
-
-`ifdef FLEN_32
-`define FLEN 32
-`endif
-
-`ifdef XLEN_64
-`ifdef FLEN_32
-    `define FPU_RV64F
-`endif
-`endif
-
-`ifndef NUM_CLUSTERS
-`define NUM_CLUSTERS 1
-`endif
-
-`ifndef NUM_CORES
-`define NUM_CORES 1
-`endif
-
-`ifndef NUM_WARPS
-`define NUM_WARPS 4
-`endif
-
-`ifndef NUM_THREADS
-`define NUM_THREADS 4
-`endif
-
-`ifndef NUM_BARRIERS
-`define NUM_BARRIERS 4
-`endif
-
-`ifndef SOCKET_SIZE
-`define SOCKET_SIZE `MIN(4, `NUM_CORES)
-`endif
-`define NUM_SOCKETS `UP(`NUM_CORES / `SOCKET_SIZE)
-
-`ifdef L2_ENABLE
-    `define L2_ENABLED   1
-`else
-    `define L2_ENABLED   0
-`endif
-
-`ifdef L3_ENABLE
-    `define L3_ENABLED   1
-`else
-    `define L3_ENABLED   0
-`endif
-
-`ifdef L1_DISABLE
-    `define ICACHE_DISABLE
-    `define DCACHE_DISABLE
-`endif
-
-`ifndef MEM_BLOCK_SIZE
-`define MEM_BLOCK_SIZE 64
-`endif
-
-`ifndef MEM_ADDR_WIDTH
-`ifdef XLEN_64
-`define MEM_ADDR_WIDTH 48
-`else
-`define MEM_ADDR_WIDTH 32
-`endif
-`endif
-
-`ifndef L1_LINE_SIZE
-`ifdef L1_DISABLE
-`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 4 : `MEM_BLOCK_SIZE)
-`else
-`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 16 : `MEM_BLOCK_SIZE)
-`endif
-`endif
-
-`ifdef L2_ENABLE
-`define L2_LINE_SIZE `MEM_BLOCK_SIZE
-`else
-`define L2_LINE_SIZE `L1_LINE_SIZE
-`endif
-
-`ifdef L3_ENABLE
-`define L3_LINE_SIZE `MEM_BLOCK_SIZE
-`else
-`define L3_LINE_SIZE `L2_LINE_SIZE
-`endif
-
-`ifdef XLEN_64
-
-`ifndef STARTUP_ADDR
-`define STARTUP_ADDR 64'h180000000
-`endif
-
-`ifndef STACK_BASE_ADDR
-`define STACK_BASE_ADDR 64'h1FF000000
-`endif
-
-`else
-
-`ifndef STARTUP_ADDR
-`define STARTUP_ADDR 32'h80000000
-`endif
-
-`ifndef STACK_BASE_ADDR
-`define STACK_BASE_ADDR 32'hFF000000
-`endif
-
-`endif
-
-`ifndef SMEM_BASE_ADDR
-`define SMEM_BASE_ADDR `STACK_BASE_ADDR
-`endif
-
-`ifndef SMEM_LOG_SIZE
-`define SMEM_LOG_SIZE   14
-`endif
-
-`ifndef IO_BASE_ADDR
-`define IO_BASE_ADDR (`SMEM_BASE_ADDR + (1 << `SMEM_LOG_SIZE))
-`endif
-
-`ifndef IO_COUT_ADDR
-`define IO_COUT_ADDR `IO_BASE_ADDR
-`endif
-`define IO_COUT_SIZE `MEM_BLOCK_SIZE
-
-`ifndef IO_CSR_ADDR
-`define IO_CSR_ADDR (`IO_COUT_ADDR + `IO_COUT_SIZE)
-`endif
-`define IO_CSR_SIZE (4 * 64 * `NUM_CORES * `NUM_CLUSTERS)
-
-`ifndef STACK_LOG2_SIZE
-`define STACK_LOG2_SIZE 13
-`endif
-`define STACK_SIZE (1 << `STACK_LOG2_SIZE)
-
-`define RESET_DELAY 8
-
-`ifndef STALL_TIMEOUT
-`define STALL_TIMEOUT (100000 * (1 ** (`L2_ENABLED + `L3_ENABLED)))
-`endif
-
-`ifndef SV_DPI
-`define DPI_DISABLE
-`endif
-
-`ifndef FPU_FPNEW
-`ifndef FPU_DSP
-`ifndef FPU_DPI
-`ifndef SYNTHESIS
-`ifndef DPI_DISABLE
-`define FPU_DPI
-`else
-`define FPU_DSP
-`endif
-`else
-`define FPU_DSP
-`endif
-`endif
-`endif
-`endif
-
-`ifndef SYNTHESIS
-`ifndef DPI_DISABLE
-`define IMUL_DPI
-`define IDIV_DPI
-`endif
-`endif
-
-`ifndef DEBUG_LEVEL
-`define DEBUG_LEVEL 3
-`endif
-
-// Pipeline Configuration /////////////////////////////////////////////////////
-
-// Issue width
-`ifndef ISSUE_WIDTH
-`define ISSUE_WIDTH     `MIN(`NUM_WARPS, 4)
-`endif
-
-// Number of ALU units
-`ifndef NUM_ALU_LANES
-`define NUM_ALU_LANES   `NUM_THREADS
-`endif
-`ifndef NUM_ALU_BLOCKS
-`define NUM_ALU_BLOCKS  `ISSUE_WIDTH
-`endif
-
-// Number of FPU units
-`ifndef NUM_FPU_LANES
-`define NUM_FPU_LANES   `NUM_THREADS
-`endif
-`ifndef NUM_FPU_BLOCKS
-`define NUM_FPU_BLOCKS  `ISSUE_WIDTH
-`endif
-
-// Number of LSU units
-`ifndef NUM_LSU_LANES
-`define NUM_LSU_LANES   `MIN(`NUM_THREADS, 4)
-`endif
-
-// Number of SFU units
-`ifndef NUM_SFU_LANES
-`define NUM_SFU_LANES   `MIN(`NUM_THREADS, 4)
-`endif
-
-// Size of Instruction Buffer
-`ifndef IBUF_SIZE
-`define IBUF_SIZE   (2 * (`NUM_WARPS / `ISSUE_WIDTH))
-`endif
-
-// Size of LSU Request Queue
-`ifndef LSUQ_SIZE
-`define LSUQ_SIZE   (2 * (`NUM_THREADS / `NUM_LSU_LANES))
-`endif
-
-// LSU Duplicate Address Check
-`ifndef LSU_DUP_DISABLE
-`define LSU_DUP_ENABLE
-`endif
-`ifdef LSU_DUP_ENABLE
-`define LSU_DUP_ENABLED 1
-`else
-`define LSU_DUP_ENABLED 0
-`endif
-
-`ifdef GBAR_ENABLE
-`define GBAR_ENABLED 1
-`else
-`define GBAR_ENABLED 0
-`endif
-
-`ifndef LATENCY_IMUL
-`ifdef VIVADO
-`define LATENCY_IMUL 4
-`endif
-`ifdef QUARTUS
-`define LATENCY_IMUL 3
-`endif
-`ifndef LATENCY_IMUL
-`define LATENCY_IMUL 4
-`endif
-`endif
-
-// Floating-Point Units ///////////////////////////////////////////////////////
-
-// Size of FPU Request Queue
-`ifndef FPUQ_SIZE
-`define FPUQ_SIZE (2 * (`NUM_THREADS / `NUM_FPU_LANES))
-`endif
-
-// FNCP Latency
-`ifndef LATENCY_FNCP
-`define LATENCY_FNCP 2
-`endif
-
-// FMA Latency
-`ifndef LATENCY_FMA
-`ifdef FPU_DPI
-`define LATENCY_FMA 4    
-`endif
-`ifdef FPU_FPNEW
-`define LATENCY_FMA 4    
-`endif
-`ifdef FPU_DSP
-`ifdef QUARTUS
-`define LATENCY_FMA 4
-`endif
-`ifdef VIVADO
-`define LATENCY_FMA 16    
-`endif
-`ifndef LATENCY_FMA
-`define LATENCY_FMA 4    
-`endif
-`endif
-`endif
-
-// FDIV Latency
-`ifndef LATENCY_FDIV
-`ifdef FPU_DPI
-`define LATENCY_FDIV 15    
-`endif
-`ifdef FPU_FPNEW
-`define LATENCY_FDIV 16    
-`endif
-`ifdef FPU_DSP
-`ifdef QUARTUS
-`define LATENCY_FDIV 15
-`endif
-`ifdef VIVADO
-`define LATENCY_FDIV 28    
-`endif
-`ifndef LATENCY_FDIV
-`define LATENCY_FDIV 16
-`endif
-`endif
-`endif
-
-// FSQRT Latency
-`ifndef LATENCY_FSQRT
-`ifdef FPU_DPI
-`define LATENCY_FSQRT 10    
-`endif
-`ifdef FPU_FPNEW
-`define LATENCY_FSQRT 16    
-`endif
-`ifdef FPU_DSP
-`ifdef QUARTUS
-`define LATENCY_FSQRT 10
-`endif
-`ifdef VIVADO
-`define LATENCY_FSQRT 28    
-`endif
-`ifndef LATENCY_FSQRT
-`define LATENCY_FSQRT 16    
-`endif
-`endif
-`endif
-
-// FCVT Latency
-`ifndef LATENCY_FCVT
-`define LATENCY_FCVT 5
-`endif
-
-// Icache Configurable Knobs //////////////////////////////////////////////////
-
-// Cache Enable
-`ifndef ICACHE_DISABLE
-`define ICACHE_ENABLE
-`endif
-`ifdef ICACHE_ENABLE
-    `define ICACHE_ENABLED 1
-`else
-    `define ICACHE_ENABLED 0
-    `define NUM_ICACHES 0
-`endif
-
-// Number of Cache Units
-`ifndef NUM_ICACHES
-`define NUM_ICACHES `UP(`SOCKET_SIZE / 4)
-`endif
-
-// Cache Size
-`ifndef ICACHE_SIZE
-`define ICACHE_SIZE 16384
-`endif
-
-// Core Response Queue Size
-`ifndef ICACHE_CRSQ_SIZE
-`define ICACHE_CRSQ_SIZE 2
-`endif
-
-// Miss Handling Register Size
-`ifndef ICACHE_MSHR_SIZE
-`define ICACHE_MSHR_SIZE 16
-`endif
-
-// Memory Request Queue Size
-`ifndef ICACHE_MREQ_SIZE
-`define ICACHE_MREQ_SIZE 4
-`endif
-
-// Memory Response Queue Size
-`ifndef ICACHE_MRSQ_SIZE
-`define ICACHE_MRSQ_SIZE 0
-`endif
-
-// Number of Associative Ways
-`ifndef ICACHE_NUM_WAYS
-`define ICACHE_NUM_WAYS 1
-`endif
-
-// Dcache Configurable Knobs //////////////////////////////////////////////////
-
-// Cache Enable
-`ifndef DCACHE_DISABLE
-`define DCACHE_ENABLE
-`endif
-`ifdef DCACHE_ENABLE
-    `define DCACHE_ENABLED 1
-`else
-    `define DCACHE_ENABLED 0
-    `define NUM_DCACHES 0
-    `define DCACHE_NUM_BANKS 1
-`endif
-
-// Number of Cache Units
-`ifndef NUM_DCACHES
-`define NUM_DCACHES `UP(`SOCKET_SIZE / 4)
-`endif
-
-// Cache Size
-`ifndef DCACHE_SIZE
-`define DCACHE_SIZE 16384
-`endif
-
-// Number of Banks
-`ifndef DCACHE_NUM_BANKS
-`define DCACHE_NUM_BANKS `MIN(`NUM_LSU_LANES, 4)
-`endif
-
-// Core Response Queue Size
-`ifndef DCACHE_CRSQ_SIZE
-`define DCACHE_CRSQ_SIZE 2
-`endif
-
-// Miss Handling Register Size
-`ifndef DCACHE_MSHR_SIZE
-`define DCACHE_MSHR_SIZE 16
-`endif
-
-// Memory Request Queue Size
-`ifndef DCACHE_MREQ_SIZE
-`define DCACHE_MREQ_SIZE 4
-`endif
-
-// Memory Response Queue Size
-`ifndef DCACHE_MRSQ_SIZE
-`define DCACHE_MRSQ_SIZE 0
-`endif
-
-// Number of Associative Ways
-`ifndef DCACHE_NUM_WAYS
-`define DCACHE_NUM_WAYS 1
-`endif
-
-// SM Configurable Knobs //////////////////////////////////////////////////////
-
-`ifndef SM_DISABLE
-`define SM_ENABLE
-`endif
-
-`ifdef SM_ENABLE
-    `define SM_ENABLED   1
-`else
-    `define SM_ENABLED   0
-    `define SMEM_NUM_BANKS 1
-`endif
-
-// Number of Banks
-`ifndef SMEM_NUM_BANKS
-`define SMEM_NUM_BANKS (`NUM_LSU_LANES)
-`endif
-
-// L2cache Configurable Knobs /////////////////////////////////////////////////
-
-// Cache Size
-`ifndef L2_CACHE_SIZE
-`ifdef ALTERA_S10
-`define L2_CACHE_SIZE 2097152
-`else
-`define L2_CACHE_SIZE 1048576
-`endif
-`endif
-
-// Number of Banks
-`ifndef L2_NUM_BANKS
-`define L2_NUM_BANKS `MIN(4, `NUM_SOCKETS)
-`endif
-
-// Core Response Queue Size
-`ifndef L2_CRSQ_SIZE
-`define L2_CRSQ_SIZE 2
-`endif
-
-// Miss Handling Register Size
-`ifndef L2_MSHR_SIZE
-`define L2_MSHR_SIZE 16
-`endif
-
-// Memory Request Queue Size
-`ifndef L2_MREQ_SIZE
-`define L2_MREQ_SIZE 4
-`endif
-
-// Memory Response Queue Size
-`ifndef L2_MRSQ_SIZE
-`define L2_MRSQ_SIZE 0
-`endif
-
-// Number of Associative Ways
-`ifndef L2_NUM_WAYS
-`define L2_NUM_WAYS 2
-`endif
-
-// L3cache Configurable Knobs /////////////////////////////////////////////////
-
-// Cache Size
-`ifndef L3_CACHE_SIZE
-`ifdef ALTERA_S10
-`define L3_CACHE_SIZE 2097152
-`else
-`define L3_CACHE_SIZE 1048576
-`endif
-`endif
-
-// Number of Banks
-`ifndef L3_NUM_BANKS
-`define L3_NUM_BANKS `MIN(4, `NUM_CLUSTERS)
-`endif
-
-// Core Response Queue Size
-`ifndef L3_CRSQ_SIZE
-`define L3_CRSQ_SIZE 2
-`endif
-
-// Miss Handling Register Size
-`ifndef L3_MSHR_SIZE
-`define L3_MSHR_SIZE 16
-`endif
-
-// Memory Request Queue Size
-`ifndef L3_MREQ_SIZE
-`define L3_MREQ_SIZE 4
-`endif
-
-// Memory Response Queue Size
-`ifndef L3_MRSQ_SIZE
-`define L3_MRSQ_SIZE 0
-`endif
-
-// Number of Associative Ways
-`ifndef L3_NUM_WAYS
-`define L3_NUM_WAYS 4
-`endif
-
-// ISA Extensions /////////////////////////////////////////////////////////////
-
-`ifdef EXT_A_ENABLE
-    `define EXT_A_ENABLED   1
-`else
-    `define EXT_A_ENABLED   0
-`endif
-
-`ifdef EXT_C_ENABLE
-    `define EXT_C_ENABLED   1
-`else
-    `define EXT_C_ENABLED   0
-`endif
-
-`ifdef EXT_D_ENABLE
-    `define EXT_D_ENABLED   1
-`else
-    `define EXT_D_ENABLED   0
-`endif
-
-`ifdef EXT_F_ENABLE
-    `define EXT_F_ENABLED   1
-`else
-    `define EXT_F_ENABLED   0
-`endif
-
-`ifdef EXT_M_ENABLE
-    `define EXT_M_ENABLED   1
-`else
-    `define EXT_M_ENABLED   0
-`endif
-
-`define ISA_STD_A           0
-`define ISA_STD_C           2
-`define ISA_STD_D           3
-`define ISA_STD_E           4
-`define ISA_STD_F           5
-`define ISA_STD_H           7
-`define ISA_STD_I           8
-`define ISA_STD_N           13
-`define ISA_STD_Q           16
-`define ISA_STD_S           18
-`define ISA_STD_U           20
-
-`define ISA_EXT_ICACHE      0
-`define ISA_EXT_DCACHE      1
-`define ISA_EXT_L2CACHE     2
-`define ISA_EXT_L3CACHE     3
-`define ISA_EXT_SMEM        4
-
-`define MISA_EXT  (`ICACHE_ENABLED  << `ISA_EXT_ICACHE) \
-                | (`DCACHE_ENABLED  << `ISA_EXT_DCACHE) \
-                | (`L2_ENABLED      << `ISA_EXT_L2CACHE) \
-                | (`L3_ENABLED      << `ISA_EXT_L3CACHE) \
-                | (`SM_ENABLED      << `ISA_EXT_SMEM)
-
-`define MISA_STD  (`EXT_A_ENABLED <<  0) /* A - Atomic Instructions extension */ \
-                | (0 <<  1) /* B - Tentatively reserved for Bit operations extension */ \
-                | (`EXT_C_ENABLED <<  2) /* C - Compressed extension */ \
-                | (`EXT_D_ENABLED <<  3) /* D - Double precsision floating-point extension */ \
-                | (0 <<  4) /* E - RV32E base ISA */ \
-                | (`EXT_F_ENABLED << 5) /* F - Single precsision floating-point extension */ \
-                | (0 <<  6) /* G - Additional standard extensions present */ \
-                | (0 <<  7) /* H - Hypervisor mode implemented */ \
-                | (1 <<  8) /* I - RV32I/64I/128I base ISA */ \
-                | (0 <<  9) /* J - Reserved */ \
-                | (0 << 10) /* K - Reserved */ \
-                | (0 << 11) /* L - Tentatively reserved for Bit operations extension */ \
-                | (`EXT_M_ENABLED << 12) /* M - Integer Multiply/Divide extension */ \
-                | (0 << 13) /* N - User level interrupts supported */ \
-                | (0 << 14) /* O - Reserved */ \
-                | (0 << 15) /* P - Tentatively reserved for Packed-SIMD extension */ \
-                | (0 << 16) /* Q - Quad-precision floating-point extension */ \
-                | (0 << 17) /* R - Reserved */ \
-                | (0 << 18) /* S - Supervisor mode implemented */ \
-                | (0 << 19) /* T - Tentatively reserved for Transactional Memory extension */ \
-                | (1 << 20) /* U - User mode implemented */ \
-                | (0 << 21) /* V - Tentatively reserved for Vector extension */ \
-                | (0 << 22) /* W - Reserved */ \
-                | (1 << 23) /* X - Non-standard extensions present */ \
-                | (0 << 24) /* Y - Reserved */ \
-                | (0 << 25) /* Z - Reserved */
-
-// Device identification //////////////////////////////////////////////////////
-
-`define VENDOR_ID           0
-`define ARCHITECTURE_ID     0
-`define IMPLEMENTATION_ID   0
-
-`endif // VX_CONFIG_VH

hw/rtl/VX_define.vh

@@ -1,432 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_DEFINE_VH
-`define VX_DEFINE_VH
-
-`include "VX_platform.vh"
-`include "VX_config.vh"
-`include "VX_types.vh"
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define NW_BITS         `CLOG2(`NUM_WARPS)
-`define NC_WIDTH        `UP(`NC_BITS)
-
-`define NT_BITS         `CLOG2(`NUM_THREADS)
-`define NW_WIDTH        `UP(`NW_BITS)
-
-`define NC_BITS         `CLOG2(`NUM_CORES)
-`define NT_WIDTH        `UP(`NT_BITS)
-
-`define NB_BITS         `CLOG2(`NUM_BARRIERS)
-`define NB_WIDTH        `UP(`NB_BITS)
-
-`define NUM_IREGS       32
-
-`define NRI_BITS        `CLOG2(`NUM_IREGS)
-
-`ifdef EXT_F_ENABLE
-`define NUM_REGS        (2 * `NUM_IREGS)
-`else
-`define NUM_REGS        `NUM_IREGS
-`endif
-
-`define NR_BITS         `CLOG2(`NUM_REGS)
-
-`define PERF_CTR_BITS   44
-
-`ifndef NDEBUG
-`define UUID_WIDTH      44
-`else
-`define UUID_WIDTH      1
-`endif
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define EX_ALU          0
-`define EX_LSU          1
-`define EX_SFU          2
-`define EX_FPU          (`EX_SFU + `EXT_F_ENABLED)
-
-`define NUM_EX_UNITS    (3 + `EXT_F_ENABLED)
-`define EX_BITS         `CLOG2(`NUM_EX_UNITS)
-`define EX_WIDTH        `UP(`EX_BITS)
-
-`define SFU_CSRS        0
-`define SFU_WCTL        1
-
-`define NUM_SFU_UNITS   (2)
-`define SFU_BITS        `CLOG2(`NUM_SFU_UNITS)
-`define SFU_WIDTH       `UP(`SFU_BITS)
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define INST_LUI        7'b0110111
-`define INST_AUIPC      7'b0010111
-`define INST_JAL        7'b1101111
-`define INST_JALR       7'b1100111
-`define INST_B          7'b1100011 // branch instructions
-`define INST_L          7'b0000011 // load instructions
-`define INST_S          7'b0100011 // store instructions
-`define INST_I          7'b0010011 // immediate instructions
-`define INST_R          7'b0110011 // register instructions
-`define INST_FENCE      7'b0001111 // Fence instructions
-`define INST_SYS        7'b1110011 // system instructions
-
-// RV64I instruction specific opcodes (for any W instruction)
-`define INST_I_W        7'b0011011 // W type immediate instructions
-`define INST_R_W        7'b0111011 // W type register instructions
-
-`define INST_FL         7'b0000111 // float load instruction
-`define INST_FS         7'b0100111 // float store  instruction
-`define INST_FMADD      7'b1000011  
-`define INST_FMSUB      7'b1000111
-`define INST_FNMSUB     7'b1001011
-`define INST_FNMADD     7'b1001111 
-`define INST_FCI        7'b1010011 // float common instructions
-
-// Custom extension opcodes
-`define INST_EXT1       7'b0001011 // 0x0B
-`define INST_EXT2       7'b0101011 // 0x2B
-`define INST_EXT3       7'b1011011 // 0x5B
-`define INST_EXT4       7'b1111011 // 0x7B
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define INST_FRM_RNE    3'b000  // round to nearest even
-`define INST_FRM_RTZ    3'b001  // round to zero
-`define INST_FRM_RDN    3'b010  // round to -inf
-`define INST_FRM_RUP    3'b011  // round to +inf
-`define INST_FRM_RMM    3'b100  // round to nearest max magnitude
-`define INST_FRM_DYN    3'b111  // dynamic mode
-`define INST_FRM_BITS   3
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define INST_OP_BITS    4
-`define INST_MOD_BITS   3
-`define INST_FMT_BITS   2
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define INST_ALU_ADD         4'b0000
-`define INST_ALU_LUI         4'b0010
-`define INST_ALU_AUIPC       4'b0011
-`define INST_ALU_SLTU        4'b0100
-`define INST_ALU_SLT         4'b0101
-`define INST_ALU_SUB         4'b0111
-`define INST_ALU_SRL         4'b1000
-`define INST_ALU_SRA         4'b1001
-`define INST_ALU_AND         4'b1100
-`define INST_ALU_OR          4'b1101
-`define INST_ALU_XOR         4'b1110
-`define INST_ALU_SLL         4'b1111
-`define INST_ALU_OTHER       4'b0111
-`define INST_ALU_BITS        4
-`define INST_ALU_CLASS(op)   op[3:2]
-`define INST_ALU_SIGNED(op)  op[0]
-`define INST_ALU_IS_SUB(op)  op[1]
-`define INST_ALU_IS_BR(mod)  mod[0]
-`define INST_ALU_IS_M(mod)   mod[1]
-`define INST_ALU_IS_W(mod)   mod[2]
-
-`define INST_BR_EQ           4'b0000
-`define INST_BR_NE           4'b0010
-`define INST_BR_LTU          4'b0100 
-`define INST_BR_GEU          4'b0110 
-`define INST_BR_LT           4'b0101
-`define INST_BR_GE           4'b0111
-`define INST_BR_JAL          4'b1000
-`define INST_BR_JALR         4'b1001
-`define INST_BR_ECALL        4'b1010
-`define INST_BR_EBREAK       4'b1011
-`define INST_BR_URET         4'b1100
-`define INST_BR_SRET         4'b1101
-`define INST_BR_MRET         4'b1110
-`define INST_BR_OTHER        4'b1111
-`define INST_BR_BITS         4
-`define INST_BR_CLASS(op)    {1'b0, ~op[3]}
-`define INST_BR_IS_NEG(op)   op[1]
-`define INST_BR_IS_LESS(op)  op[2]
-`define INST_BR_IS_STATIC(op) op[3]
-
-`define INST_M_MUL           3'b000
-`define INST_M_MULHU         3'b001
-`define INST_M_MULH          3'b010
-`define INST_M_MULHSU        3'b011
-`define INST_M_DIV           3'b100
-`define INST_M_DIVU          3'b101
-`define INST_M_REM           3'b110
-`define INST_M_REMU          3'b111
-`define INST_M_BITS          3
-`define INST_M_SIGNED(op)    (~op[0])
-`define INST_M_IS_MULX(op)   (~op[2])
-`define INST_M_IS_MULH(op)   (op[1:0] != 0)
-`define INST_M_SIGNED_A(op)  (op[1:0] != 1)
-`define INST_M_IS_REM(op)    op[1]
-
-`define INST_FMT_B           3'b000
-`define INST_FMT_H           3'b001
-`define INST_FMT_W           3'b010
-`define INST_FMT_D           3'b011
-`define INST_FMT_BU          3'b100
-`define INST_FMT_HU          3'b101
-`define INST_FMT_WU          3'b110
-
-`define INST_LSU_LB          4'b0000 
-`define INST_LSU_LH          4'b0001
-`define INST_LSU_LW          4'b0010
-`define INST_LSU_LD          4'b0011 // new for RV64I LD
-`define INST_LSU_LBU         4'b0100
-`define INST_LSU_LHU         4'b0101
-`define INST_LSU_LWU         4'b0110 // new for RV64I LWU
-`define INST_LSU_SB          4'b1000 
-`define INST_LSU_SH          4'b1001
-`define INST_LSU_SW          4'b1010
-`define INST_LSU_SD          4'b1011 // new for RV64I SD
-`define INST_LSU_FENCE       4'b1111
-`define INST_LSU_BITS        4
-`define INST_LSU_FMT(op)     op[2:0]
-`define INST_LSU_WSIZE(op)   op[1:0]
-`define INST_LSU_IS_FENCE(op) (op[3:2] == 3)
-
-`define INST_FENCE_BITS      1
-`define INST_FENCE_D         1'h0
-`define INST_FENCE_I         1'h1
-
-`define INST_FPU_ADD         4'b0000 
-`define INST_FPU_SUB         4'b0001 
-`define INST_FPU_MUL         4'b0010 
-`define INST_FPU_DIV         4'b0011
-`define INST_FPU_SQRT        4'b0100
-`define INST_FPU_CMP         4'b0101 // mod: LE=0, LT=1, EQ=2
-`define INST_FPU_F2F         4'b0110
-`define INST_FPU_MISC        4'b0111 // mod: SGNJ=0, SGNJN=1, SGNJX=2, CLASS=3, MVXW=4, MVWX=5, FMIN=6, FMAX=7
-`define INST_FPU_F2I         4'b1000
-`define INST_FPU_F2U         4'b1001
-`define INST_FPU_I2F         4'b1010
-`define INST_FPU_U2F         4'b1011
-`define INST_FPU_MADD        4'b1100 
-`define INST_FPU_MSUB        4'b1101   
-`define INST_FPU_NMSUB       4'b1110   
-`define INST_FPU_NMADD       4'b1111
-`define INST_FPU_BITS        4
-`define INST_FPU_IS_W(mod)   (mod[4])
-`define INST_FPU_IS_CLASS(op, mod) (op == `INST_FPU_MISC && mod == 3)
-`define INST_FPU_IS_MVXW(op, mod) (op == `INST_FPU_MISC && mod == 4)
-
-`define INST_SFU_TMC         4'h0
-`define INST_SFU_WSPAWN      4'h1 
-`define INST_SFU_SPLIT       4'h2
-`define INST_SFU_JOIN        4'h3
-`define INST_SFU_BAR         4'h4
-`define INST_SFU_PRED        4'h5
-`define INST_SFU_CSRRW       4'h6
-`define INST_SFU_CSRRS       4'h7
-`define INST_SFU_CSRRC       4'h8
-`define INST_SFU_CMOV        4'h9
-`define INST_SFU_BITS        4
-`define INST_SFU_CSR(f3)     (4'h6 + 4'(f3) - 4'h1)
-`define INST_SFU_IS_WCTL(op) (op <= 5)
-`define INST_SFU_IS_CSR(op)  (op >= 6 && op <= 8)
-
-///////////////////////////////////////////////////////////////////////////////
-
-// non-cacheable tag bits
-`define NC_TAG_BITS             1
-
-// cache address type bits
-`ifdef SM_ENABLE
-`define CACHE_ADDR_TYPE_BITS    (`NC_TAG_BITS + 1)
-`else
-`define CACHE_ADDR_TYPE_BITS    `NC_TAG_BITS
-`endif
-
-`define ARB_SEL_BITS(I, O)      ((I > O) ? `CLOG2((I + O - 1) / O) : 0)
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define CACHE_MEM_TAG_WIDTH(mshr_size, num_banks) \
-        (`CLOG2(mshr_size) + `CLOG2(num_banks) + `NC_TAG_BITS)
-        
-`define CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) \
-        (`CLOG2(num_reqs) + `CLOG2(line_size / word_size) + tag_width)
-
-`define CACHE_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) \
-        (`CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) + `NC_TAG_BITS)
-
-`define CACHE_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, tag_width) \
-        `MAX(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), `CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width))
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches) \
-        (tag_width + `ARB_SEL_BITS(num_inputs, `UP(num_caches)))  
-
-`define CACHE_CLUSTER_MEM_ARB_TAG(tag_width, num_caches) \
-        (tag_width + `ARB_SEL_BITS(`UP(num_caches), 1))
-
-`define CACHE_CLUSTER_MEM_TAG_WIDTH(mshr_size, num_banks, num_caches) \
-        `CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks),  num_caches)
-
-`define CACHE_CLUSTER_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \
-        `CACHE_CLUSTER_MEM_ARB_TAG((`CLOG2(num_reqs) + `CLOG2(line_size / word_size) + `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)), num_caches)
-
-`define CACHE_CLUSTER_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \
-        `CACHE_CLUSTER_MEM_ARB_TAG((`CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)) + `NC_TAG_BITS), num_caches)
-
-`define CACHE_CLUSTER_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \
-        `CACHE_CLUSTER_MEM_ARB_TAG(`MAX(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), `CACHE_NC_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches))), num_caches)
-
-///////////////////////////////////////////////////////////////////////////////
-
-`ifdef ICACHE_ENABLE
-`define L1_ENABLE
-`endif
-`ifdef DCACHE_ENABLE
-`define L1_ENABLE
-`endif
-
-`define VX_MEM_BYTEEN_WIDTH     `L3_LINE_SIZE   
-`define VX_MEM_ADDR_WIDTH       (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE))
-`define VX_MEM_DATA_WIDTH       (`L3_LINE_SIZE * 8)
-`define VX_MEM_TAG_WIDTH        L3_MEM_TAG_WIDTH
-
-`define VX_DCR_ADDR_WIDTH       `VX_DCR_ADDR_BITS
-`define VX_DCR_DATA_WIDTH       32
-
-`define TO_FULL_ADDR(x)         {x, (`MEM_ADDR_WIDTH-$bits(x))'(0)}
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define BUFFER_EX(dst, src, ena, latency) \
-    VX_pipe_register #( \
-        .DATAW  ($bits(dst)), \
-        .RESETW ($bits(dst)), \
-        .DEPTH  (latency) \
-    ) __``dst ( \
-        .clk      (clk), \
-        .reset    (reset), \
-        .enable   (ena), \
-        .data_in  (src), \
-        .data_out (dst) \
-    )
-
-`define BUFFER(dst, src) `BUFFER_EX(dst, src, 1'b1, 1)
-
-`define POP_COUNT_EX(out, in, model) \
-    VX_popcount #( \
-        .N ($bits(in)), \
-        .MODEL (model) \
-    ) __``out ( \
-        .data_in  (in), \
-        .data_out (out) \
-    )
-
-`define POP_COUNT(out, in) `POP_COUNT_EX(out, in, 1)
-
-`define ASSIGN_VX_MEM_BUS_IF(dst, src) \
-    assign dst.req_valid  = src.req_valid; \
-    assign dst.req_data   = src.req_data; \
-    assign src.req_ready  = dst.req_ready; \
-    assign src.rsp_valid  = dst.rsp_valid; \
-    assign src.rsp_data   = dst.rsp_data; \
-    assign dst.rsp_ready  = src.rsp_ready
-
-`define ASSIGN_VX_MEM_BUS_IF_X(dst, src, TD, TS) \
-    assign dst.req_valid = src.req_valid; \
-    assign dst.req_data.rw = src.req_data.rw; \
-    assign dst.req_data.byteen = src.req_data.byteen; \
-    assign dst.req_data.addr = src.req_data.addr; \
-    assign dst.req_data.data = src.req_data.data; \
-    if (TD != TS) \
-        assign dst.req_data.tag = {src.req_data.tag, {(TD-TS){1'b0}}}; \
-    else \
-        assign dst.req_data.tag = src.req_data.tag; \
-    assign src.req_ready = dst.req_ready; \
-    assign src.rsp_valid = dst.rsp_valid; \
-    assign src.rsp_data.data = dst.rsp_data.data; \
-    assign src.rsp_data.tag = dst.rsp_data.tag[TD-1 -: TS]; \
-    assign dst.rsp_ready = src.rsp_ready
-
-`define BUFFER_DCR_BUS_IF(dst, src, enable) \
-    logic [(1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH)-1:0] __``dst; \
-    if (enable) begin \
-        always @(posedge clk) begin \
-            __``dst <= {src.write_valid, src.write_addr, src.write_data}; \
-        end \
-    end else begin \
-        assign __``dst = {src.write_valid, src.write_addr, src.write_data}; \
-    end \
-    VX_dcr_bus_if dst(); \
-    assign {dst.write_valid, dst.write_addr, dst.write_data} = __``dst
-
-`define PERF_COUNTER_ADD(dst, src, field, width, dst_count, src_count, reg_enable) \
-    for (genvar __d = 0; __d < dst_count; ++__d) begin \
-        localparam __count = ((src_count > dst_count) ? ((src_count + dst_count - 1) / dst_count) : 1); \
-        wire [__count-1:0][width-1:0] __reduce_add_i_``src``field; \
-        wire [width-1:0] __reduce_add_o_``dst``field; \
-        for (genvar __i = 0; __i < __count; ++__i) begin \
-            assign __reduce_add_i_``src``field[__i] = ``src[__d * __count + __i].``field; \
-        end \
-        VX_reduce #(.DATAW_IN(width), .N(__count), .OP("+")) __reduce_add_``dst``field ( \
-            __reduce_add_i_``src``field, \
-            __reduce_add_o_``dst``field \
-        ); \
-        if (reg_enable) begin \
-            reg [width-1:0] __reduce_add_r_``dst``field; \
-            always @(posedge clk) begin \
-                if (reset) begin \
-                    __reduce_add_r_``dst``field <= '0; \
-                end else begin \
-                    __reduce_add_r_``dst``field <= __reduce_add_o_``dst``field; \
-                end \
-            end \
-            assign ``dst[__d].``field = __reduce_add_r_``dst``field; \
-        end else begin \
-            assign ``dst[__d].``field = __reduce_add_o_``dst``field; \
-        end \
-    end
-
-`define ASSIGN_BLOCKED_WID(dst, src, block_idx, block_size) \
-    if (block_size != 1) begin \
-        if (block_size != `NUM_WARPS) begin \
-            assign dst = {src[`NW_WIDTH-1:`CLOG2(block_size)], `CLOG2(block_size)'(block_idx)}; \
-        end else begin \
-            assign dst = `NW_WIDTH'(block_idx); \
-        end \
-    end else begin \
-        assign dst = src; \
-    end
-
-`define TO_DISPATCH_DATA(data, tid) { \
-    data.uuid, \
-    data.wis, \
-    data.tmask, \
-    data.op_type, \
-    data.op_mod, \
-    data.wb, \
-    data.use_PC, \
-    data.use_imm, \
-    data.PC, \
-    data.imm, \
-    data.rd, \
-    tid, \
-    data.rs1_data, \
-    data.rs2_data, \
-    data.rs3_data}
-
-///////////////////////////////////////////////////////////////////////////////
-
-`endif // VX_DEFINE_VH

hw/rtl/VX_gpu_pkg.sv

@@ -1,239 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_GPU_PKG_VH
-`define VX_GPU_PKG_VH
-
-`include "VX_define.vh"
-
-package VX_gpu_pkg;
-
-    typedef struct packed {
-        logic                    valid;
-        logic [`NUM_THREADS-1:0] tmask;
-    } tmc_t;
-
-    typedef struct packed {
-        logic                   valid;
-        logic [`NUM_WARPS-1:0]  wmask;
-        logic [`XLEN-1:0]       pc;
-    } wspawn_t;
-
-    typedef struct packed {
-        logic                    valid;
-        logic                    is_dvg;
-        logic [`NUM_THREADS-1:0] then_tmask;
-        logic [`NUM_THREADS-1:0] else_tmask;
-        logic [`XLEN-1:0]        next_pc;
-    } split_t;
-
-    typedef struct packed {
-        logic valid;
-        logic is_dvg;
-    } join_t;
-
-    typedef struct packed {
-        logic                   valid;
-        logic [`NB_WIDTH-1:0]   id;
-        logic                   is_global;
-    `ifdef GBAR_ENABLE
-        logic [`MAX(`NW_WIDTH, `NC_WIDTH)-1:0] size_m1;
-    `else
-        logic [`NW_WIDTH-1:0]   size_m1;
-    `endif
-    } barrier_t;
-
-    typedef struct packed {
-        logic [`XLEN-1:0]   startup_addr;
-        logic [7:0]         mpm_class;
-    } base_dcrs_t;
-
-    typedef struct packed {
-        logic [`PERF_CTR_BITS-1:0] reads;
-        logic [`PERF_CTR_BITS-1:0] writes;
-        logic [`PERF_CTR_BITS-1:0] read_misses;
-        logic [`PERF_CTR_BITS-1:0] write_misses;
-        logic [`PERF_CTR_BITS-1:0] bank_stalls;
-        logic [`PERF_CTR_BITS-1:0] mshr_stalls;
-        logic [`PERF_CTR_BITS-1:0] mem_stalls;
-        logic [`PERF_CTR_BITS-1:0] crsp_stalls;
-    } cache_perf_t;
-
-    typedef struct packed {
-        logic [`PERF_CTR_BITS-1:0] reads;
-        logic [`PERF_CTR_BITS-1:0] writes;
-        logic [`PERF_CTR_BITS-1:0] latency;
-    } mem_perf_t;
-
-    /* verilator lint_off UNUSED */
-
-    ////////////////////////// Icache Parameters //////////////////////////////
-
-    // Word size in bytes
-    localparam ICACHE_WORD_SIZE	    = 4;
-    localparam ICACHE_ADDR_WIDTH	= (`MEM_ADDR_WIDTH - `CLOG2(ICACHE_WORD_SIZE));
-
-    // Block size in bytes
-    localparam ICACHE_LINE_SIZE	    = `L1_LINE_SIZE;
-
-    // Core request tag Id bits       
-    localparam ICACHE_TAG_ID_BITS	= `NW_WIDTH;
-
-    // Core request tag bits
-    localparam ICACHE_TAG_WIDTH	    = (`UUID_WIDTH + ICACHE_TAG_ID_BITS);
-
-    // Memory request data bits
-    localparam ICACHE_MEM_DATA_WIDTH = (ICACHE_LINE_SIZE * 8);
-
-    // Memory request tag bits
-    `ifdef ICACHE_ENABLE
-    localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_MEM_TAG_WIDTH(`ICACHE_MSHR_SIZE, 1, `NUM_ICACHES);
-    `else
-    localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(1, ICACHE_LINE_SIZE, ICACHE_WORD_SIZE, ICACHE_TAG_WIDTH, `SOCKET_SIZE, `NUM_ICACHES);
-    `endif
-
-    ////////////////////////// Dcache Parameters //////////////////////////////
-
-    // Word size in bytes
-    localparam DCACHE_WORD_SIZE	    = (`XLEN / 8);
-    localparam DCACHE_ADDR_WIDTH	= (`MEM_ADDR_WIDTH - `CLOG2(DCACHE_WORD_SIZE));
-
-    // Block size in bytes
-    localparam DCACHE_LINE_SIZE 	= `L1_LINE_SIZE;
-
-    // Input request size
-    localparam DCACHE_NUM_REQS	    = `MAX(`DCACHE_NUM_BANKS, `SMEM_NUM_BANKS);
-
-    // Memory request size
-    localparam LSU_MEM_REQS	        = `NUM_LSU_LANES;
-
-    // Batch select bits
-    localparam DCACHE_NUM_BATCHES	= ((LSU_MEM_REQS + DCACHE_NUM_REQS - 1) / DCACHE_NUM_REQS);
-    localparam DCACHE_BATCH_SEL_BITS = `CLOG2(DCACHE_NUM_BATCHES);
-
-    // Core request tag Id bits
-    localparam LSUQ_TAG_BITS	    = (`CLOG2(`LSUQ_SIZE) + DCACHE_BATCH_SEL_BITS);
-    localparam DCACHE_TAG_ID_BITS	= (LSUQ_TAG_BITS + `CACHE_ADDR_TYPE_BITS);
-
-    // Core request tag bits
-    localparam DCACHE_TAG_WIDTH	    = (`UUID_WIDTH + DCACHE_TAG_ID_BITS);
-    localparam DCACHE_NOSM_TAG_WIDTH = (DCACHE_TAG_WIDTH - `SM_ENABLED);
-    
-    // Memory request data bits
-    localparam DCACHE_MEM_DATA_WIDTH = (DCACHE_LINE_SIZE * 8);
-
-    // Memory request tag bits
-    `ifdef DCACHE_ENABLE
-    localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_MEM_TAG_WIDTH(`DCACHE_MSHR_SIZE, `DCACHE_NUM_BANKS, DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_NOSM_TAG_WIDTH, `SOCKET_SIZE, `NUM_DCACHES);
-    `else
-    localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_BYPASS_TAG_WIDTH(DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_NOSM_TAG_WIDTH, `SOCKET_SIZE, `NUM_DCACHES);
-    `endif
-
-    /////////////////////////////// L1 Parameters /////////////////////////////
-
-    localparam L1_MEM_TAG_WIDTH     = `MAX(ICACHE_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
-    localparam L1_MEM_ARB_TAG_WIDTH = (L1_MEM_TAG_WIDTH + `CLOG2(2));
-    
-    /////////////////////////////// L2 Parameters /////////////////////////////
-
-    localparam ICACHE_MEM_ARB_IDX = 0;
-    localparam DCACHE_MEM_ARB_IDX = ICACHE_MEM_ARB_IDX + 1;
-
-    // Word size in bytes
-    localparam L2_WORD_SIZE	        = `L1_LINE_SIZE;
-
-    // Input request size
-    localparam L2_NUM_REQS	        = `NUM_SOCKETS;
-
-    // Core request tag bits
-    localparam L2_TAG_WIDTH	        = L1_MEM_ARB_TAG_WIDTH;
-
-    // Memory request data bits
-    localparam L2_MEM_DATA_WIDTH	= (`L2_LINE_SIZE * 8);
-
-    // Memory request tag bits
-    `ifdef L2_ENABLE
-    localparam L2_MEM_TAG_WIDTH     = `CACHE_NC_MEM_TAG_WIDTH(`L2_MSHR_SIZE, `L2_NUM_BANKS, L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
-    `else
-    localparam L2_MEM_TAG_WIDTH     = `CACHE_NC_BYPASS_TAG_WIDTH(L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
-    `endif
-
-    /////////////////////////////// L3 Parameters /////////////////////////////
-
-    // Word size in bytes
-    localparam L3_WORD_SIZE	        = `L2_LINE_SIZE;
-
-    // Input request size
-    localparam L3_NUM_REQS	        = `NUM_CLUSTERS;
-
-    // Core request tag bits
-    localparam L3_TAG_WIDTH	        = L2_MEM_TAG_WIDTH;
-
-    // Memory request data bits
-    localparam L3_MEM_DATA_WIDTH	= (`L3_LINE_SIZE * 8);
-
-    // Memory request tag bits
-    `ifdef L3_ENABLE
-    localparam L3_MEM_TAG_WIDTH     = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM_BANKS, L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
-    `else
-    localparam L3_MEM_TAG_WIDTH     = `CACHE_NC_BYPASS_TAG_WIDTH(L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
-    `endif
-
-    /* verilator lint_on UNUSED */
-
-    /////////////////////////////// Issue parameters //////////////////////////
-
-    localparam ISSUE_ISW   = `CLOG2(`ISSUE_WIDTH);
-    localparam ISSUE_ISW_W = `UP(ISSUE_ISW);   
-    localparam ISSUE_RATIO = `NUM_WARPS / `ISSUE_WIDTH;
-    localparam ISSUE_WIS   = `CLOG2(ISSUE_RATIO);
-    localparam ISSUE_WIS_W = `UP(ISSUE_WIS);
-    
-`IGNORE_UNUSED_BEGIN
-    function logic [`NW_WIDTH-1:0] wis_to_wid(
-        input logic [ISSUE_WIS_W-1:0] wis, 
-        input logic [ISSUE_ISW_W-1:0] isw
-    );
-        if (ISSUE_WIS == 0) begin
-            wis_to_wid = `NW_WIDTH'(isw);
-        end else if (ISSUE_ISW == 0) begin
-            wis_to_wid = `NW_WIDTH'(wis);
-        end else begin 
-            wis_to_wid = `NW_WIDTH'({wis, isw});
-        end
-    endfunction
-
-    function logic [ISSUE_ISW_W-1:0] wid_to_isw(
-        input logic [`NW_WIDTH-1:0] wid
-    );
-        if (ISSUE_ISW != 0) begin    
-            wid_to_isw = wid[ISSUE_ISW_W-1:0];
-        end else begin
-            wid_to_isw = 0;
-        end
-    endfunction
-
-    function logic [ISSUE_WIS_W-1:0] wid_to_wis(
-        input logic [`NW_WIDTH-1:0] wid
-    );
-        if (ISSUE_WIS != 0) begin
-            wid_to_wis = ISSUE_WIS_W'(wid >> ISSUE_ISW);
-        end else begin
-            wid_to_wis = 0;
-        end
-    endfunction
-`IGNORE_UNUSED_END
-
-endpackage
-
-`endif // VX_GPU_PKG_VH

hw/rtl/VX_platform.vh

@@ -1,275 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_PLATFORM_VH
-`define VX_PLATFORM_VH
-
-`ifdef SV_DPI
-`include "util_dpi.vh"
-`endif
-
-`include "VX_scope.vh"
-
-///////////////////////////////////////////////////////////////////////////////
-
-`ifdef VIVADO
-`define STRING
-`else
-`define STRING string
-`endif
-
-`ifdef SYNTHESIS
-`define TRACING_ON
-`define TRACING_OFF
-`ifndef NDEBUG
-    `define DEBUG_BLOCK(x) x
-`else
-    `define DEBUG_BLOCK(x)
-`endif
-`define IGNORE_UNOPTFLAT_BEGIN
-`define IGNORE_UNOPTFLAT_END
-`define IGNORE_UNUSED_BEGIN
-`define IGNORE_UNUSED_END
-`define IGNORE_WARNINGS_BEGIN
-`define IGNORE_WARNINGS_END
-`define UNUSED_PARAM(x)
-`define UNUSED_SPARAM(x)
-`define UNUSED_VAR(x)
-`define UNUSED_PIN(x) . x ()
-`define UNUSED_ARG(x) x
-`define TRACE(level, args) $write args
-`else
-`ifdef VERILATOR
-`define TRACING_ON      /* verilator tracing_on */
-`define TRACING_OFF     /* verilator tracing_off */
-`ifndef NDEBUG
-    `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
-                           x \
-                           /* verilator lint_on UNUSED */
-`else
-    `define DEBUG_BLOCK(x)
-`endif
-
-`define IGNORE_UNOPTFLAT_BEGIN /* verilator lint_off UNOPTFLAT */
-
-`define IGNORE_UNOPTFLAT_END  /* verilator lint_off UNOPTFLAT */
-
-`define IGNORE_UNUSED_BEGIN   /* verilator lint_off UNUSED */
-
-`define IGNORE_UNUSED_END     /* verilator lint_on UNUSED */
-
-`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
-                              /* verilator lint_off PINCONNECTEMPTY */ \
-                              /* verilator lint_off WIDTH */ \
-                              /* verilator lint_off UNOPTFLAT */ \
-                              /* verilator lint_off UNDRIVEN */ \
-                              /* verilator lint_off DECLFILENAME */ \
-                              /* verilator lint_off IMPLICIT */ \
-                              /* verilator lint_off PINMISSING */ \
-                              /* verilator lint_off IMPORTSTAR */ \
-                              /* verilator lint_off UNSIGNED */
-
-`define IGNORE_WARNINGS_END   /* verilator lint_on UNUSED */ \
-                              /* verilator lint_on PINCONNECTEMPTY */ \
-                              /* verilator lint_on WIDTH */ \
-                              /* verilator lint_on UNOPTFLAT */ \
-                              /* verilator lint_on UNDRIVEN */ \
-                              /* verilator lint_on DECLFILENAME */ \
-                              /* verilator lint_on IMPLICIT */ \
-                              /* verilator lint_off PINMISSING */ \
-                              /* verilator lint_on IMPORTSTAR */ \
-                              /* verilator lint_on UNSIGNED */
-
-`define UNUSED_PARAM(x)  /* verilator lint_off UNUSED */ \
-                         localparam  __``x = x; \
-                         /* verilator lint_on UNUSED */
-
-`define UNUSED_SPARAM(x) /* verilator lint_off UNUSED */ \
-                         localparam `STRING __``x = x; \
-                         /* verilator lint_on UNUSED */
-
-`define UNUSED_VAR(x)   if (1) begin \
-                            /* verilator lint_off UNUSED */ \
-                            wire [$bits(x)-1:0] __x = x; \
-                            /* verilator lint_on UNUSED */ \
-                        end
-
-`define UNUSED_PIN(x)   /* verilator lint_off PINCONNECTEMPTY */ \
-                        . x () \
-                        /* verilator lint_on PINCONNECTEMPTY */
-`define UNUSED_ARG(x)   /* verilator lint_off UNUSED */ \
-                        x \
-                        /* verilator lint_on UNUSED */
-`define TRACE(level, args) dpi_trace(level, $sformatf args)
-`endif
-`endif
-
-`ifdef SIMULATION
-    `define STATIC_ASSERT(cond, msg) \
-    generate                     \
-        if (!(cond)) $error msg; \
-    endgenerate
-
-    `define ERROR(msg) \
-        $error msg
-
-    `define ASSERT(cond, msg) \
-        assert(cond) else $error msg
-
-    `define RUNTIME_ASSERT(cond, msg)     \
-        always @(posedge clk) begin       \
-            assert(cond) else $error msg; \
-        end
-`else
-    `define STATIC_ASSERT(cond, msg)
-    `define ERROR(msg)                  //
-    `define ASSERT(cond, msg)           //
-    `define RUNTIME_ASSERT(cond, msg)
-`endif
-
-///////////////////////////////////////////////////////////////////////////////
-
-`ifdef QUARTUS
-`define MAX_FANOUT      4
-`define IF_DATA_SIZE(x) $bits(x.data)
-`define USE_FAST_BRAM   (* ramstyle = "MLAB, no_rw_check" *)
-`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
-`define DISABLE_BRAM    (* ramstyle = "logic" *)
-`define PRESERVE_NET    (* preserve *)
-`elsif VIVADO
-`define MAX_FANOUT      4
-`define IF_DATA_SIZE(x) $bits(x.data)
-`define USE_FAST_BRAM   (* ram_style = "distributed" *)
-`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *)
-`define DISABLE_BRAM    (* ram_style = "registers" *)
-`define PRESERVE_NET    (* keep = "true" *)
-`else
-`define MAX_FANOUT      4
-`define IF_DATA_SIZE(x) x.DATA_WIDTH
-`define USE_FAST_BRAM
-`define NO_RW_RAM_CHECK
-`define DISABLE_BRAM
-`define PRESERVE_NET
-`endif
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define STRINGIFY(x) `"x`"
-
-`define CLOG2(x)    $clog2(x)
-`define FLOG2(x)    ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0))
-`define LOG2UP(x)   (((x) > 1) ? $clog2(x) : 1)
-`define ISPOW2(x)   (((x) != 0) && (0 == ((x) & ((x) - 1))))
-
-`define ABS(x)      (((x) < 0) ? (-(x)) : (x));
-
-`ifndef MIN
-`define MIN(x, y)   (((x) < (y)) ? (x) : (y))
-`endif
-
-`ifndef MAX
-`define MAX(x, y)   (((x) > (y)) ? (x) : (y))
-`endif
-
-`ifndef CLAMP
-`define CLAMP(x, lo, hi)   (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x)))
-`endif
-
-`ifndef UP
-`define UP(x)       (((x) != 0) ? (x) : 1)
-`endif
-
-`define RTRIM(x, s) x[$bits(x)-1:($bits(x)-s)]
-
-`define LTRIM(x, s) x[s-1:0]
-
-`define TRACE_ARRAY1D(lvl, arr, m)              \
-    `TRACE(lvl, ("{"));                         \
-    for (integer __i = (m-1); __i >= 0; --__i) begin  \
-        if (__i != (m-1)) `TRACE(lvl, (", "));    \
-        `TRACE(lvl, ("0x%0h", arr[__i]));         \
-    end                                         \
-    `TRACE(lvl, ("}"));
-
-`define TRACE_ARRAY2D(lvl, arr, m, n)           \
-    `TRACE(lvl, ("{"));                         \
-    for (integer __i = n-1; __i >= 0; --__i) begin    \
-        if (__i != (n-1)) `TRACE(lvl, (", "));    \
-        `TRACE(lvl, ("{"));                     \
-        for (integer __j = (m-1); __j >= 0; --__j) begin \
-            if (__j != (m-1)) `TRACE(lvl, (", "));\
-            `TRACE(lvl, ("0x%0h", arr[__i][__j]));  \
-        end                                     \
-        `TRACE(lvl, ("}"));                     \
-    end                                         \
-    `TRACE(lvl, ("}"))
-
-`define RESET_RELAY_EX(dst, src, size, fanout)  \
-    wire [size-1:0] dst;                        \
-    VX_reset_relay #(.N(size), .MAX_FANOUT(fanout)) __``dst ( \
-        .clk     (clk),                         \
-        .reset   (src),                         \
-        .reset_o (dst)                          \
-    )
-
-`define RESET_RELAY_EN(dst, src, enable) \
-    `RESET_RELAY_EX (dst, src, 1, ((enable) ? 0 : -1))
-
-`define RESET_RELAY(dst, src) \
-    `RESET_RELAY_EX (dst, src, 1, 0)
-
-// size(x): 0 -> 0, 1 -> 1, 2 -> 2, 3 -> 2, 4-> 2
-`define OUT_REG_TO_EB_SIZE(out_reg)   `MIN(out_reg, 2)
-
-// reg(x): 0 -> 0, 1 -> 1, 2 -> 0, 3 -> 1, 4 -> 2
-`define OUT_REG_TO_EB_REG(out_reg)    ((out_reg & 1) + ((out_reg >> 2) << 1))
-
-`define REPEAT(n,f,s)   `_REPEAT_``n(f,s)
-`define _REPEAT_0(f,s)
-`define _REPEAT_1(f,s)  `f(0)
-`define _REPEAT_2(f,s)  `f(1)  `s `_REPEAT_1(f,s)
-`define _REPEAT_3(f,s)  `f(2)  `s `_REPEAT_2(f,s)
-`define _REPEAT_4(f,s)  `f(3)  `s `_REPEAT_3(f,s)
-`define _REPEAT_5(f,s)  `f(4)  `s `_REPEAT_4(f,s)
-`define _REPEAT_6(f,s)  `f(5)  `s `_REPEAT_5(f,s)
-`define _REPEAT_7(f,s)  `f(6)  `s `_REPEAT_6(f,s)
-`define _REPEAT_8(f,s)  `f(7)  `s `_REPEAT_7(f,s)
-`define _REPEAT_9(f,s)  `f(8)  `s `_REPEAT_8(f,s)
-`define _REPEAT_10(f,s) `f(9)  `s `_REPEAT_9(f,s)
-`define _REPEAT_11(f,s) `f(10) `s `_REPEAT_10(f,s)
-`define _REPEAT_12(f,s) `f(11) `s `_REPEAT_11(f,s)
-`define _REPEAT_13(f,s) `f(12) `s `_REPEAT_12(f,s)
-`define _REPEAT_14(f,s) `f(13) `s `_REPEAT_13(f,s)
-`define _REPEAT_15(f,s) `f(14) `s `_REPEAT_14(f,s)
-`define _REPEAT_16(f,s) `f(15) `s `_REPEAT_15(f,s)
-`define _REPEAT_17(f,s) `f(16) `s `_REPEAT_16(f,s)
-`define _REPEAT_18(f,s) `f(17) `s `_REPEAT_17(f,s)
-`define _REPEAT_19(f,s) `f(18) `s `_REPEAT_18(f,s)
-`define _REPEAT_20(f,s) `f(19) `s `_REPEAT_19(f,s)
-`define _REPEAT_21(f,s) `f(20) `s `_REPEAT_20(f,s)
-`define _REPEAT_22(f,s) `f(21) `s `_REPEAT_21(f,s)
-`define _REPEAT_23(f,s) `f(22) `s `_REPEAT_22(f,s)
-`define _REPEAT_24(f,s) `f(23) `s `_REPEAT_23(f,s)
-`define _REPEAT_25(f,s) `f(24) `s `_REPEAT_24(f,s)
-`define _REPEAT_26(f,s) `f(25) `s `_REPEAT_25(f,s)
-`define _REPEAT_27(f,s) `f(26) `s `_REPEAT_26(f,s)
-`define _REPEAT_28(f,s) `f(27) `s `_REPEAT_27(f,s)
-`define _REPEAT_29(f,s) `f(28) `s `_REPEAT_28(f,s)
-`define _REPEAT_30(f,s) `f(29) `s `_REPEAT_29(f,s)
-`define _REPEAT_31(f,s) `f(30) `s `_REPEAT_30(f,s)
-`define _REPEAT_32(f,s) `f(31) `s `_REPEAT_31(f,s)
-
-`define REPEAT_COMMA ,
-`define REPEAT_SEMICOLON ;
-
-`endif // VX_PLATFORM_VH

hw/rtl/VX_scope.vh

@@ -1,68 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_SCOPE_VH
-`define VX_SCOPE_VH
-
-`ifdef SCOPE
-
-`define SCOPE_IO_DECL \
-    input wire scope_reset, \
-    input wire scope_bus_in, \
-    output wire scope_bus_out,
-
-`define SCOPE_IO_SWITCH(__count) \
-    wire scope_bus_in_w [__count]; \
-    wire scope_bus_out_w [__count]; \
-    `RESET_RELAY_EX(scope_reset_w, scope_reset, __count, 4); \
-    VX_scope_switch #( \
-        .N (__count) \
-    ) scope_switch ( \
-        .clk (clk), \
-        .reset (scope_reset), \
-        .req_in (scope_bus_in), \
-        .rsp_out (scope_bus_out), \
-        .req_out (scope_bus_in_w), \
-        .rsp_in (scope_bus_out_w) \
-    );
-
-`define SCOPE_IO_BIND(__i) \
-    .scope_reset (scope_reset_w[__i]), \
-    .scope_bus_in (scope_bus_in_w[__i]), \
-    .scope_bus_out (scope_bus_out_w[__i]),
-
-`define SCOPE_IO_UNUSED() \
-    `UNUSED_VAR (scope_reset); \
-    `UNUSED_VAR (scope_bus_in); \
-    assign scope_bus_out = 0;
-
-`define SCOPE_IO_UNUSED_W(__i) \
-    `UNUSED_VAR (scope_reset_w[__i]); \
-    `UNUSED_VAR (scope_bus_in_w[__i]); \
-    assign scope_bus_out_w[__i] = 0;
-
-`else
-
-`define SCOPE_IO_DECL
-
-`define SCOPE_IO_SWITCH(__count)
-
-`define SCOPE_IO_BIND(__i)
-
-`define SCOPE_IO_UNUSED_W(__i)
-
-`define SCOPE_IO_UNUSED(__i)
-
-`endif
-
-`endif // VX_SCOPE_VH

hw/rtl/VX_socket.sv

@@ -1,247 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_socket import VX_gpu_pkg::*; #( 
-    parameter SOCKET_ID = 0
-) (        
-    `SCOPE_IO_DECL
-    
-    // Clock
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave    mem_perf_if,
-`endif
-
-    // DCRs
-    VX_dcr_bus_if.slave     dcr_bus_if,
-
-    // Memory
-    VX_mem_bus_if.master    mem_bus_if,
-
-`ifdef GBAR_ENABLE
-    // Barrier
-    VX_gbar_bus_if.master   gbar_bus_if,
-`endif
-
-    // simulation helper signals
-    output wire             sim_ebreak,
-    output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
-
-    // Status
-    output wire             busy
-);
-
-`ifdef GBAR_ENABLE
-    VX_gbar_bus_if per_core_gbar_bus_if[`SOCKET_SIZE]();
-
-    `RESET_RELAY (gbar_arb_reset, reset);
-
-    VX_gbar_arb #(
-        .NUM_REQS (`SOCKET_SIZE),
-        .OUT_REG  ((`SOCKET_SIZE > 1) ? 2 : 0)
-    ) gbar_arb (
-        .clk        (clk),
-        .reset      (gbar_arb_reset),
-        .bus_in_if  (per_core_gbar_bus_if),
-        .bus_out_if (gbar_bus_if)
-    );
-`endif
-
-    ///////////////////////////////////////////////////////////////////////////
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if mem_perf_tmp_if();
-    assign mem_perf_tmp_if.l2cache = mem_perf_if.l2cache;
-    assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
-    assign mem_perf_tmp_if.smem = 'x;
-    assign mem_perf_tmp_if.mem = mem_perf_if.mem;
-`endif
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (ICACHE_WORD_SIZE), 
-        .TAG_WIDTH (ICACHE_TAG_WIDTH)
-    ) per_core_icache_bus_if[`SOCKET_SIZE]();
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (ICACHE_LINE_SIZE),
-        .TAG_WIDTH (ICACHE_MEM_TAG_WIDTH)
-    ) icache_mem_bus_if();
-
-    `RESET_RELAY (icache_reset, reset);
-
-    VX_cache_cluster #(
-        .INSTANCE_ID    ($sformatf("socket%0d-icache", SOCKET_ID)),    
-        .NUM_UNITS      (`NUM_ICACHES),
-        .NUM_INPUTS     (`SOCKET_SIZE),
-        .TAG_SEL_IDX    (0),
-        .CACHE_SIZE     (`ICACHE_SIZE),
-        .LINE_SIZE      (ICACHE_LINE_SIZE),
-        .NUM_BANKS      (1),
-        .NUM_WAYS       (`ICACHE_NUM_WAYS),
-        .WORD_SIZE      (ICACHE_WORD_SIZE),
-        .NUM_REQS       (1),
-        .CRSQ_SIZE      (`ICACHE_CRSQ_SIZE),
-        .MSHR_SIZE      (`ICACHE_MSHR_SIZE),
-        .MRSQ_SIZE      (`ICACHE_MRSQ_SIZE),
-        .MREQ_SIZE      (`ICACHE_MREQ_SIZE),
-        .TAG_WIDTH      (ICACHE_TAG_WIDTH),
-        .UUID_WIDTH     (`UUID_WIDTH),
-        .WRITE_ENABLE   (0),
-        .CORE_OUT_REG   (2),
-        .MEM_OUT_REG    (2)
-    ) icache (
-    `ifdef PERF_ENABLE
-        .cache_perf     (mem_perf_tmp_if.icache),
-    `endif
-        .clk            (clk),
-        .reset          (icache_reset),
-        .core_bus_if    (per_core_icache_bus_if),
-        .mem_bus_if     (icache_mem_bus_if)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (DCACHE_WORD_SIZE),
-        .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
-    ) per_core_dcache_bus_if[`SOCKET_SIZE * DCACHE_NUM_REQS]();
-    
-    VX_mem_bus_if #(
-        .DATA_SIZE (DCACHE_LINE_SIZE),
-        .TAG_WIDTH (DCACHE_MEM_TAG_WIDTH)
-    ) dcache_mem_bus_if();
-
-    `RESET_RELAY (dcache_reset, reset);
-
-    VX_cache_cluster #(
-        .INSTANCE_ID    ($sformatf("socket%0d-dcache", SOCKET_ID)),    
-        .NUM_UNITS      (`NUM_DCACHES),
-        .NUM_INPUTS     (`SOCKET_SIZE),
-        .TAG_SEL_IDX    (1),
-        .CACHE_SIZE     (`DCACHE_SIZE),
-        .LINE_SIZE      (DCACHE_LINE_SIZE),
-        .NUM_BANKS      (`DCACHE_NUM_BANKS),
-        .NUM_WAYS       (`DCACHE_NUM_WAYS),
-        .WORD_SIZE      (DCACHE_WORD_SIZE),
-        .NUM_REQS       (DCACHE_NUM_REQS),
-        .CRSQ_SIZE      (`DCACHE_CRSQ_SIZE),
-        .MSHR_SIZE      (`DCACHE_MSHR_SIZE),
-        .MRSQ_SIZE      (`DCACHE_MRSQ_SIZE),
-        .MREQ_SIZE      (`DCACHE_MREQ_SIZE),
-        .TAG_WIDTH      (DCACHE_NOSM_TAG_WIDTH),
-        .UUID_WIDTH     (`UUID_WIDTH),
-        .WRITE_ENABLE   (1),        
-        .NC_ENABLE      (1),
-        .CORE_OUT_REG   (`SM_ENABLED ? 2 : 1),
-        .MEM_OUT_REG    (2)
-    ) dcache (
-    `ifdef PERF_ENABLE
-        .cache_perf     (mem_perf_tmp_if.dcache),
-    `endif        
-        .clk            (clk),
-        .reset          (dcache_reset),        
-        .core_bus_if    (per_core_dcache_bus_if),
-        .mem_bus_if     (dcache_mem_bus_if)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////  
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (`L1_LINE_SIZE),
-        .TAG_WIDTH (L1_MEM_TAG_WIDTH)
-    ) l1_mem_bus_if[2]();
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (`L1_LINE_SIZE),
-        .TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
-    ) l1_mem_arb_bus_if[1]();
-
-    `ASSIGN_VX_MEM_BUS_IF_X (l1_mem_bus_if[0], icache_mem_bus_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH);
-    `ASSIGN_VX_MEM_BUS_IF_X (l1_mem_bus_if[1], dcache_mem_bus_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
-
-    `RESET_RELAY (mem_arb_reset, reset);
-
-    VX_mem_arb #(
-        .NUM_INPUTS   (2),
-        .DATA_SIZE    (`L1_LINE_SIZE),
-        .TAG_WIDTH    (L1_MEM_TAG_WIDTH),
-        .TAG_SEL_IDX  (1), // Skip 0 for NC flag
-        .ARBITER      ("R"),
-        .OUT_REG_REQ  (2),
-        .OUT_REG_RSP  (2)
-    ) mem_arb (
-        .clk        (clk),
-        .reset      (mem_arb_reset),
-        .bus_in_if  (l1_mem_bus_if),
-        .bus_out_if (l1_mem_arb_bus_if)
-    );
-
-    `ASSIGN_VX_MEM_BUS_IF (mem_bus_if, l1_mem_arb_bus_if[0]);
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    wire [`SOCKET_SIZE-1:0] per_core_sim_ebreak;
-    wire [`SOCKET_SIZE-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_core_sim_wb_value;
-    assign sim_ebreak = per_core_sim_ebreak[0];
-    assign sim_wb_value = per_core_sim_wb_value[0];
-    `UNUSED_VAR (per_core_sim_ebreak)
-    `UNUSED_VAR (per_core_sim_wb_value)
-
-    wire [`SOCKET_SIZE-1:0] per_core_busy;
-
-    `BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, (`SOCKET_SIZE > 1));
-
-    `SCOPE_IO_SWITCH (`SOCKET_SIZE)
-
-    // Generate all cores
-    for (genvar i = 0; i < `SOCKET_SIZE; ++i) begin
-
-        `RESET_RELAY (core_reset, reset);
-
-        VX_core #(
-            .CORE_ID ((SOCKET_ID * `SOCKET_SIZE) + i)
-        ) core (
-            `SCOPE_IO_BIND  (i)
-
-            .clk            (clk),
-            .reset          (core_reset),
-
-        `ifdef PERF_ENABLE
-            .mem_perf_if    (mem_perf_tmp_if),
-        `endif
-            
-            .dcr_bus_if     (core_dcr_bus_if),
-
-            .dcache_bus_if  (per_core_dcache_bus_if[i * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]),
-
-            .icache_bus_if  (per_core_icache_bus_if[i]),
-
-        `ifdef GBAR_ENABLE
-            .gbar_bus_if    (per_core_gbar_bus_if[i]),
-        `endif
-
-            .sim_ebreak     (per_core_sim_ebreak[i]),
-            .sim_wb_value   (per_core_sim_wb_value[i]),
-            .busy           (per_core_busy[i])
-        );
-    end
-
-    `BUFFER_EX(busy, (| per_core_busy), 1'b1, (`SOCKET_SIZE > 1));
-    
-endmodule

hw/rtl/VX_types.vh

@@ -1,187 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_TYPES_VH
-`define VX_TYPES_VH
-
-// Device configuration registers
-
-`define VX_CSR_ADDR_BITS                12
-`define VX_DCR_ADDR_BITS                12
-
-`define VX_DCR_BASE_STATE_BEGIN         12'h001
-`define VX_DCR_BASE_STARTUP_ADDR0       12'h001
-`define VX_DCR_BASE_STARTUP_ADDR1       12'h002
-`define VX_DCR_BASE_MPM_CLASS           12'h003
-`define VX_DCR_BASE_STATE_END           12'h004
-
-`define VX_DCR_BASE_STATE(addr)         ((addr) - `VX_DCR_BASE_STATE_BEGIN)
-`define VX_DCR_BASE_STATE_COUNT         (`VX_DCR_BASE_STATE_END-`VX_DCR_BASE_STATE_BEGIN)
-
-// Machine Performance-monitoring counters classes
-
-`define VX_DCR_MPM_CLASS_NONE           0           
-`define VX_DCR_MPM_CLASS_CORE           1
-`define VX_DCR_MPM_CLASS_MEM            2
-
-// User Floating-Point CSRs
-
-`define VX_CSR_FFLAGS                   12'h001
-`define VX_CSR_FRM                      12'h002
-`define VX_CSR_FCSR                     12'h003
- 
-`define VX_CSR_SATP                     12'h180
-
-`define VX_CSR_PMPCFG0                  12'h3A0
-`define VX_CSR_PMPADDR0                 12'h3B0
-
-`define VX_CSR_MSTATUS                  12'h300
-`define VX_CSR_MISA                     12'h301
-`define VX_CSR_MEDELEG                  12'h302
-`define VX_CSR_MIDELEG                  12'h303
-`define VX_CSR_MIE                      12'h304
-`define VX_CSR_MTVEC                    12'h305
-
-`define VX_CSR_MEPC                     12'h341
-
-`define VX_CSR_MNSTATUS                 12'h744
-
-`define VX_CSR_MPM_BASE                 12'hB00
-`define VX_CSR_MPM_BASE_H               12'hB80
-`define VX_CSR_MPM_USER                 12'hB03
-`define VX_CSR_MPM_USER_H               12'hB83
-
-// Machine Performance-monitoring core counters
-// PERF: Standard
-`define VX_CSR_MCYCLE                   12'hB00
-`define VX_CSR_MCYCLE_H                 12'hB80
-`define VX_CSR_MPM_RESERVED             12'hB01
-`define VX_CSR_MPM_RESERVED_H           12'hB81
-`define VX_CSR_MINSTRET                 12'hB02
-`define VX_CSR_MINSTRET_H               12'hB82
-// PERF: pipeline
-`define VX_CSR_MPM_SCHED_ID             12'hB03
-`define VX_CSR_MPM_SCHED_ID_H           12'hB83
-`define VX_CSR_MPM_SCHED_ST             12'hB04
-`define VX_CSR_MPM_SCHED_ST_H           12'hB84
-`define VX_CSR_MPM_IBUF_ST              12'hB05
-`define VX_CSR_MPM_IBUF_ST_H            12'hB85
-`define VX_CSR_MPM_SCRB_ST              12'hB06
-`define VX_CSR_MPM_SCRB_ST_H            12'hB86
-`define VX_CSR_MPM_SCRB_ALU             12'hB07
-`define VX_CSR_MPM_SCRB_ALU_H           12'hB87
-`define VX_CSR_MPM_SCRB_FPU             12'hB08
-`define VX_CSR_MPM_SCRB_FPU_H           12'hB88
-`define VX_CSR_MPM_SCRB_LSU             12'hB09
-`define VX_CSR_MPM_SCRB_LSU_H           12'hB89
-`define VX_CSR_MPM_SCRB_SFU             12'hB0A
-`define VX_CSR_MPM_SCRB_SFU_H           12'hB8A
-// PERF: memory
-`define VX_CSR_MPM_IFETCHES             12'hB0B
-`define VX_CSR_MPM_IFETCHES_H           12'hB8B
-`define VX_CSR_MPM_LOADS                12'hB0C
-`define VX_CSR_MPM_LOADS_H              12'hB8C
-`define VX_CSR_MPM_STORES               12'hB0D
-`define VX_CSR_MPM_STORES_H             12'hB8D
-`define VX_CSR_MPM_IFETCH_LT            12'hB0E
-`define VX_CSR_MPM_IFETCH_LT_H          12'hB8E
-`define VX_CSR_MPM_LOAD_LT              12'hB0F 
-`define VX_CSR_MPM_LOAD_LT_H            12'hB8F
-// SFU: scoreboard
-`define VX_CSR_MPM_SCRB_WCTL            12'hB10
-`define VX_CSR_MPM_SCRB_WCTL_H          12'hB90
-`define VX_CSR_MPM_SCRB_CSRS            12'hB11
-`define VX_CSR_MPM_SCRB_CSRS_H          12'hB91
-
-// Machine Performance-monitoring memory counters
-// PERF: icache
-`define VX_CSR_MPM_ICACHE_READS         12'hB03     // total reads
-`define VX_CSR_MPM_ICACHE_READS_H       12'hB83
-`define VX_CSR_MPM_ICACHE_MISS_R        12'hB04     // read misses
-`define VX_CSR_MPM_ICACHE_MISS_R_H      12'hB84
-`define VX_CSR_MPM_ICACHE_MSHR_ST       12'hB05     // MSHR stalls
-`define VX_CSR_MPM_ICACHE_MSHR_ST_H     12'hB85
-// PERF: dcache
-`define VX_CSR_MPM_DCACHE_READS         12'hB06     // total reads
-`define VX_CSR_MPM_DCACHE_READS_H       12'hB86
-`define VX_CSR_MPM_DCACHE_WRITES        12'hB07     // total writes
-`define VX_CSR_MPM_DCACHE_WRITES_H      12'hB87
-`define VX_CSR_MPM_DCACHE_MISS_R        12'hB08     // read misses
-`define VX_CSR_MPM_DCACHE_MISS_R_H      12'hB88
-`define VX_CSR_MPM_DCACHE_MISS_W        12'hB09     // write misses
-`define VX_CSR_MPM_DCACHE_MISS_W_H      12'hB89
-`define VX_CSR_MPM_DCACHE_BANK_ST       12'hB0A     // bank conflicts
-`define VX_CSR_MPM_DCACHE_BANK_ST_H     12'hB8A
-`define VX_CSR_MPM_DCACHE_MSHR_ST       12'hB0B     // MSHR stalls
-`define VX_CSR_MPM_DCACHE_MSHR_ST_H     12'hB8B
-// PERF: l2cache
-`define VX_CSR_MPM_L2CACHE_READS        12'hB0C     // total reads
-`define VX_CSR_MPM_L2CACHE_READS_H      12'hB8C
-`define VX_CSR_MPM_L2CACHE_WRITES       12'hB0D     // total writes
-`define VX_CSR_MPM_L2CACHE_WRITES_H     12'hB8D
-`define VX_CSR_MPM_L2CACHE_MISS_R       12'hB0E     // read misses
-`define VX_CSR_MPM_L2CACHE_MISS_R_H     12'hB8E
-`define VX_CSR_MPM_L2CACHE_MISS_W       12'hB0F     // write misses
-`define VX_CSR_MPM_L2CACHE_MISS_W_H     12'hB8F
-`define VX_CSR_MPM_L2CACHE_BANK_ST      12'hB10     // bank conflicts
-`define VX_CSR_MPM_L2CACHE_BANK_ST_H    12'hB90
-`define VX_CSR_MPM_L2CACHE_MSHR_ST      12'hB11     // MSHR stalls
-`define VX_CSR_MPM_L2CACHE_MSHR_ST_H    12'hB91
-// PERF: l3cache
-`define VX_CSR_MPM_L3CACHE_READS        12'hB12     // total reads
-`define VX_CSR_MPM_L3CACHE_READS_H      12'hB92
-`define VX_CSR_MPM_L3CACHE_WRITES       12'hB13     // total writes
-`define VX_CSR_MPM_L3CACHE_WRITES_H     12'hB93
-`define VX_CSR_MPM_L3CACHE_MISS_R       12'hB14     // read misses
-`define VX_CSR_MPM_L3CACHE_MISS_R_H     12'hB94
-`define VX_CSR_MPM_L3CACHE_MISS_W       12'hB15     // write misses
-`define VX_CSR_MPM_L3CACHE_MISS_W_H     12'hB95
-`define VX_CSR_MPM_L3CACHE_BANK_ST      12'hB16     // bank conflicts
-`define VX_CSR_MPM_L3CACHE_BANK_ST_H    12'hB96
-`define VX_CSR_MPM_L3CACHE_MSHR_ST      12'hB17     // MSHR stalls
-`define VX_CSR_MPM_L3CACHE_MSHR_ST_H    12'hB97
-// PERF: memory
-`define VX_CSR_MPM_MEM_READS            12'hB18     // total reads
-`define VX_CSR_MPM_MEM_READS_H          12'hB98
-`define VX_CSR_MPM_MEM_WRITES           12'hB19     // total writes
-`define VX_CSR_MPM_MEM_WRITES_H         12'hB99
-`define VX_CSR_MPM_MEM_LT               12'hB1A     // memory latency
-`define VX_CSR_MPM_MEM_LT_H             12'hB9A
-// PERF: smem
-`define VX_CSR_MPM_SMEM_READS           12'hB1B     // memory reads
-`define VX_CSR_MPM_SMEM_READS_H         12'hB9B
-`define VX_CSR_MPM_SMEM_WRITES          12'hB1C     // memory writes
-`define VX_CSR_MPM_SMEM_WRITES_H        12'hB9C
-`define VX_CSR_MPM_SMEM_BANK_ST         12'hB1D     // bank conflicts
-`define VX_CSR_MPM_SMEM_BANK_ST_H       12'hB9D
-
-// Machine Information Registers
-
-`define VX_CSR_MVENDORID                12'hF11
-`define VX_CSR_MARCHID                  12'hF12
-`define VX_CSR_MIMPID                   12'hF13
-`define VX_CSR_MHARTID                  12'hF14
-
-// GPGU CSRs
-
-`define VX_CSR_THREAD_ID                12'hCC0
-`define VX_CSR_WARP_ID                  12'hCC1
-`define VX_CSR_CORE_ID                  12'hCC2
-`define VX_CSR_WARP_MASK                12'hCC3
-`define VX_CSR_THREAD_MASK              12'hCC4     // warning! this value is also used in LLVM
-
-`define VX_CSR_NUM_THREADS              12'hFC0
-`define VX_CSR_NUM_WARPS                12'hFC1
-`define VX_CSR_NUM_CORES                12'hFC2
-
-`endif // VX_TYPES_VH

hw/rtl/Vortex.sv

@@ -1,215 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module Vortex import VX_gpu_pkg::*; (
-    `SCOPE_IO_DECL
-
-    // Clock
-    input  wire                             clk,
-    input  wire                             reset,
-
-    // Memory request
-    output wire                             mem_req_valid,
-    output wire                             mem_req_rw,
-    output wire [`VX_MEM_BYTEEN_WIDTH-1:0]  mem_req_byteen,
-    output wire [`VX_MEM_ADDR_WIDTH-1:0]    mem_req_addr,
-    output wire [`VX_MEM_DATA_WIDTH-1:0]    mem_req_data,
-    output wire [`VX_MEM_TAG_WIDTH-1:0]     mem_req_tag,
-    input  wire                             mem_req_ready,
-
-    // Memory response    
-    input wire                              mem_rsp_valid,    
-    input wire [`VX_MEM_DATA_WIDTH-1:0]     mem_rsp_data,
-    input wire [`VX_MEM_TAG_WIDTH-1:0]      mem_rsp_tag,
-    output wire                             mem_rsp_ready,
-
-    // DCR write request
-    input  wire                             dcr_wr_valid,
-    input  wire [`VX_DCR_ADDR_WIDTH-1:0]    dcr_wr_addr,
-    input  wire [`VX_DCR_DATA_WIDTH-1:0]    dcr_wr_data,
-
-    // Status
-    output wire                             busy
-);
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if mem_perf_if();
-    assign mem_perf_if.icache  = 'x;
-    assign mem_perf_if.dcache  = 'x;
-    assign mem_perf_if.l2cache = 'x;
-`endif
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (`L2_LINE_SIZE),
-        .TAG_WIDTH (L2_MEM_TAG_WIDTH)
-    ) per_cluster_mem_bus_if[`NUM_CLUSTERS]();
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (`L3_LINE_SIZE),
-        .TAG_WIDTH (L3_MEM_TAG_WIDTH)
-    ) mem_bus_if();
-
-    `RESET_RELAY (l3_reset, reset);
-
-    VX_cache_wrap #(
-        .INSTANCE_ID    ("l3cache"),
-        .CACHE_SIZE     (`L3_CACHE_SIZE),
-        .LINE_SIZE      (`L3_LINE_SIZE),
-        .NUM_BANKS      (`L3_NUM_BANKS),
-        .NUM_WAYS       (`L3_NUM_WAYS),
-        .WORD_SIZE      (L3_WORD_SIZE),
-        .NUM_REQS       (L3_NUM_REQS),
-        .CRSQ_SIZE      (`L3_CRSQ_SIZE),
-        .MSHR_SIZE      (`L3_MSHR_SIZE),
-        .MRSQ_SIZE      (`L3_MRSQ_SIZE),
-        .MREQ_SIZE      (`L3_MREQ_SIZE),
-        .TAG_WIDTH      (L2_MEM_TAG_WIDTH),
-        .WRITE_ENABLE   (1),
-        .UUID_WIDTH     (`UUID_WIDTH),  
-        .CORE_OUT_REG   (2),
-        .MEM_OUT_REG    (2),
-        .NC_ENABLE      (1),
-        .PASSTHRU       (!`L3_ENABLED)
-    ) l3cache (
-        .clk            (clk),
-        .reset          (l3_reset),
-
-    `ifdef PERF_ENABLE
-        .cache_perf     (mem_perf_if.l3cache),
-    `endif
-
-        .core_bus_if    (per_cluster_mem_bus_if),
-        .mem_bus_if     (mem_bus_if)
-    );
-
-    assign mem_req_valid = mem_bus_if.req_valid;
-    assign mem_req_rw    = mem_bus_if.req_data.rw;
-    assign mem_req_byteen= mem_bus_if.req_data.byteen;
-    assign mem_req_addr  = mem_bus_if.req_data.addr;
-    assign mem_req_data  = mem_bus_if.req_data.data;
-    assign mem_req_tag   = mem_bus_if.req_data.tag;
-    assign mem_bus_if.req_ready = mem_req_ready;
-
-    assign mem_bus_if.rsp_valid = mem_rsp_valid;
-    assign mem_bus_if.rsp_data.data  = mem_rsp_data;
-    assign mem_bus_if.rsp_data.tag   = mem_rsp_tag;
-    assign mem_rsp_ready = mem_bus_if.rsp_ready;
-
-    wire mem_req_fire = mem_req_valid && mem_req_ready;
-    wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
-    `UNUSED_VAR (mem_req_fire)
-    `UNUSED_VAR (mem_rsp_fire)
-
-    wire sim_ebreak /* verilator public */;
-    wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value /* verilator public */;    
-    wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak;
-    wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_cluster_sim_wb_value;
-    assign sim_ebreak = per_cluster_sim_ebreak[0];
-    assign sim_wb_value = per_cluster_sim_wb_value[0];
-    `UNUSED_VAR (per_cluster_sim_ebreak)
-    `UNUSED_VAR (per_cluster_sim_wb_value)        
-
-    VX_dcr_bus_if dcr_bus_if();
-    assign dcr_bus_if.write_valid = dcr_wr_valid;
-    assign dcr_bus_if.write_addr  = dcr_wr_addr;
-    assign dcr_bus_if.write_data  = dcr_wr_data;
-
-    wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
-
-    `SCOPE_IO_SWITCH (`NUM_CLUSTERS)
-
-    // Generate all clusters
-    for (genvar i = 0; i < `NUM_CLUSTERS; ++i) begin
-
-        `RESET_RELAY (cluster_reset, reset);
-
-        `BUFFER_DCR_BUS_IF (cluster_dcr_bus_if, dcr_bus_if, (`NUM_CLUSTERS > 1));
-
-        VX_cluster #(
-            .CLUSTER_ID (i)
-        ) cluster (
-            `SCOPE_IO_BIND (i)
-
-            .clk                (clk),
-            .reset              (cluster_reset),
-
-        `ifdef PERF_ENABLE
-            .mem_perf_if        (mem_perf_if),
-        `endif
-            
-            .dcr_bus_if         (cluster_dcr_bus_if),
-
-            .mem_bus_if         (per_cluster_mem_bus_if[i]),
-
-            .sim_ebreak         (per_cluster_sim_ebreak[i]),
-            .sim_wb_value       (per_cluster_sim_wb_value[i]),
-
-            .busy               (per_cluster_busy[i])
-        );
-    end
-
-    `BUFFER_EX(busy, (| per_cluster_busy), 1'b1, (`NUM_CLUSTERS > 1));
-
-`ifdef PERF_ENABLE
-
-    reg [`PERF_CTR_BITS-1:0] perf_mem_pending_reads;    
-    mem_perf_t mem_perf;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_mem_pending_reads <= '0;
-        end else begin
-            perf_mem_pending_reads <= $signed(perf_mem_pending_reads) + 
-                `PERF_CTR_BITS'($signed(2'(mem_req_fire && ~mem_bus_if.req_data.rw) - 2'(mem_rsp_fire)));
-        end
-    end
-
-    wire mem_rd_req_fire = mem_req_fire && ~mem_bus_if.req_data.rw;
-    wire mem_wr_req_fire = mem_req_fire && mem_bus_if.req_data.rw;
-
-    always @(posedge clk) begin
-        if (reset) begin       
-            mem_perf <= '0;
-        end else begin
-            mem_perf.reads <= mem_perf.reads + `PERF_CTR_BITS'(mem_rd_req_fire);
-            mem_perf.writes <= mem_perf.writes + `PERF_CTR_BITS'(mem_wr_req_fire);
-            mem_perf.latency <= mem_perf.latency + perf_mem_pending_reads;
-        end
-    end
-    assign mem_perf_if.mem = mem_perf;
-    
-`endif
-
-`ifdef DBG_TRACE_CORE_MEM
-    always @(posedge clk) begin
-        if (mem_req_fire) begin
-            if (mem_req_rw)
-                `TRACE(1, ("%d: MEM Wr Req: addr=0x%0h, tag=0x%0h, byteen=0x%0h data=0x%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data));
-            else
-                `TRACE(1, ("%d: MEM Rd Req: addr=0x%0h, tag=0x%0h, byteen=0x%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen));
-        end
-        if (mem_rsp_fire) begin
-            `TRACE(1, ("%d: MEM Rsp: tag=0x%0h, data=0x%0h\n", $time, mem_rsp_tag, mem_rsp_data));
-        end
-    end
-`endif
-
-`ifdef SIMULATION
-    always @(posedge clk) begin
-        $fflush(); // flush stdout buffer
-    end
-`endif
-
-endmodule

hw/rtl/Vortex_axi.sv

@@ -1,218 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module Vortex_axi import VX_gpu_pkg::*; #(
-    parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH, 
-    parameter AXI_ADDR_WIDTH = `XLEN,
-    parameter AXI_TID_WIDTH  = `VX_MEM_TAG_WIDTH,
-    parameter AXI_NUM_BANKS  = 1
-)(
-    `SCOPE_IO_DECL
-
-    // Clock
-    input  wire                         clk,
-    input  wire                         reset,
-
-    // AXI write request address channel    
-    output wire                         m_axi_awvalid [AXI_NUM_BANKS],
-    input wire                          m_axi_awready [AXI_NUM_BANKS],
-    output wire [AXI_ADDR_WIDTH-1:0]    m_axi_awaddr [AXI_NUM_BANKS],
-    output wire [AXI_TID_WIDTH-1:0]     m_axi_awid [AXI_NUM_BANKS],
-    output wire [7:0]                   m_axi_awlen [AXI_NUM_BANKS],
-    output wire [2:0]                   m_axi_awsize [AXI_NUM_BANKS],
-    output wire [1:0]                   m_axi_awburst [AXI_NUM_BANKS],
-    output wire [1:0]                   m_axi_awlock [AXI_NUM_BANKS],
-    output wire [3:0]                   m_axi_awcache [AXI_NUM_BANKS],
-    output wire [2:0]                   m_axi_awprot [AXI_NUM_BANKS],
-    output wire [3:0]                   m_axi_awqos [AXI_NUM_BANKS],
-    output wire [3:0]                   m_axi_awregion [AXI_NUM_BANKS],
-
-    // AXI write request data channel     
-    output wire                         m_axi_wvalid [AXI_NUM_BANKS], 
-    input wire                          m_axi_wready [AXI_NUM_BANKS],
-    output wire [AXI_DATA_WIDTH-1:0]    m_axi_wdata [AXI_NUM_BANKS],
-    output wire [AXI_DATA_WIDTH/8-1:0]  m_axi_wstrb [AXI_NUM_BANKS],    
-    output wire                         m_axi_wlast [AXI_NUM_BANKS],  
-
-    // AXI write response channel
-    input wire                          m_axi_bvalid [AXI_NUM_BANKS],
-    output wire                         m_axi_bready [AXI_NUM_BANKS],
-    input wire [AXI_TID_WIDTH-1:0]      m_axi_bid [AXI_NUM_BANKS],
-    input wire [1:0]                    m_axi_bresp [AXI_NUM_BANKS],
-    
-    // AXI read request channel
-    output wire                         m_axi_arvalid [AXI_NUM_BANKS],
-    input wire                          m_axi_arready [AXI_NUM_BANKS],
-    output wire [AXI_ADDR_WIDTH-1:0]    m_axi_araddr [AXI_NUM_BANKS],
-    output wire [AXI_TID_WIDTH-1:0]     m_axi_arid [AXI_NUM_BANKS],
-    output wire [7:0]                   m_axi_arlen [AXI_NUM_BANKS],
-    output wire [2:0]                   m_axi_arsize [AXI_NUM_BANKS],
-    output wire [1:0]                   m_axi_arburst [AXI_NUM_BANKS],            
-    output wire [1:0]                   m_axi_arlock [AXI_NUM_BANKS],    
-    output wire [3:0]                   m_axi_arcache [AXI_NUM_BANKS],
-    output wire [2:0]                   m_axi_arprot [AXI_NUM_BANKS],        
-    output wire [3:0]                   m_axi_arqos [AXI_NUM_BANKS], 
-    output wire [3:0]                   m_axi_arregion [AXI_NUM_BANKS],
-    
-    // AXI read response channel
-    input wire                          m_axi_rvalid [AXI_NUM_BANKS],
-    output wire                         m_axi_rready [AXI_NUM_BANKS],
-    input wire [AXI_DATA_WIDTH-1:0]     m_axi_rdata [AXI_NUM_BANKS],
-    input wire                          m_axi_rlast [AXI_NUM_BANKS],
-    input wire [AXI_TID_WIDTH-1:0]      m_axi_rid [AXI_NUM_BANKS],
-    input wire [1:0]                    m_axi_rresp [AXI_NUM_BANKS],
-    
-    // DCR write request
-    input  wire                         dcr_wr_valid,
-    input  wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
-    input  wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
-
-    // Status
-    output wire                         busy
-);
-    `STATIC_ASSERT((AXI_DATA_WIDTH == `VX_MEM_DATA_WIDTH), ("invalid memory data size: current=%0d, expected=%0d", AXI_DATA_WIDTH, `VX_MEM_DATA_WIDTH))
-    `STATIC_ASSERT((AXI_ADDR_WIDTH >= `XLEN), ("invalid memory address size: current=%0d, expected=%0d", AXI_ADDR_WIDTH, `VX_MEM_ADDR_WIDTH))
-    //`STATIC_ASSERT((AXI_TID_WIDTH >= `VX_MEM_TAG_WIDTH), ("invalid memory tag size: current=%0d, expected=%0d", AXI_TID_WIDTH, `VX_MEM_TAG_WIDTH))
-    
-    wire                            mem_req_valid;
-    wire                            mem_req_rw; 
-    wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen;
-    wire [`VX_MEM_ADDR_WIDTH-1:0]   mem_req_addr;
-    wire [`VX_MEM_DATA_WIDTH-1:0]   mem_req_data;
-    wire [`VX_MEM_TAG_WIDTH-1:0]    mem_req_tag;
-    wire                            mem_req_ready;
-
-    wire                            mem_rsp_valid;        
-    wire [`VX_MEM_DATA_WIDTH-1:0]   mem_rsp_data;
-    wire [`VX_MEM_TAG_WIDTH-1:0]    mem_rsp_tag;
-    wire                            mem_rsp_ready;
-    
-    wire [`XLEN-1:0] m_axi_awaddr_unqual [AXI_NUM_BANKS];
-    wire [`XLEN-1:0] m_axi_araddr_unqual [AXI_NUM_BANKS];
-
-    wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_awid_unqual [AXI_NUM_BANKS];
-    wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_arid_unqual [AXI_NUM_BANKS];
-    
-    wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_bid_unqual [AXI_NUM_BANKS];
-    wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_rid_unqual [AXI_NUM_BANKS];
-
-    for (genvar i = 0; i < AXI_NUM_BANKS; ++i) begin
-        assign m_axi_awaddr[i] = `XLEN'(m_axi_awaddr_unqual[i]);
-        assign m_axi_araddr[i] = `XLEN'(m_axi_araddr_unqual[i]);
-        
-        assign m_axi_awid[i] = AXI_TID_WIDTH'(m_axi_awid_unqual[i]);
-        assign m_axi_arid[i] = AXI_TID_WIDTH'(m_axi_arid_unqual[i]);
-
-        assign m_axi_rid_unqual[i] = `VX_MEM_TAG_WIDTH'(m_axi_rid[i]);
-        assign m_axi_bid_unqual[i] = `VX_MEM_TAG_WIDTH'(m_axi_bid[i]);
-    end
-
-    VX_axi_adapter #(
-        .DATA_WIDTH (`VX_MEM_DATA_WIDTH), 
-        .ADDR_WIDTH (`XLEN),
-        .TAG_WIDTH  (`VX_MEM_TAG_WIDTH),
-        .NUM_BANKS  (AXI_NUM_BANKS),
-        .OUT_REG_RSP((AXI_NUM_BANKS > 1) ? 2 : 0)
-    ) axi_adapter (
-        .clk            (clk),
-        .reset          (reset),
-
-        .mem_req_valid  (mem_req_valid),
-        .mem_req_rw     (mem_req_rw),
-        .mem_req_byteen (mem_req_byteen),
-        .mem_req_addr   (mem_req_addr),
-        .mem_req_data   (mem_req_data),
-        .mem_req_tag    (mem_req_tag),
-        .mem_req_ready  (mem_req_ready),
-
-        .mem_rsp_valid  (mem_rsp_valid),
-        .mem_rsp_data   (mem_rsp_data),
-        .mem_rsp_tag    (mem_rsp_tag),
-        .mem_rsp_ready  (mem_rsp_ready),
-                
-        .m_axi_awvalid  (m_axi_awvalid),
-        .m_axi_awready  (m_axi_awready),
-        .m_axi_awaddr   (m_axi_awaddr_unqual),
-        .m_axi_awid     (m_axi_awid_unqual),
-        .m_axi_awlen    (m_axi_awlen),
-        .m_axi_awsize   (m_axi_awsize),
-        .m_axi_awburst  (m_axi_awburst),  
-        .m_axi_awlock   (m_axi_awlock),    
-        .m_axi_awcache  (m_axi_awcache),
-        .m_axi_awprot   (m_axi_awprot),        
-        .m_axi_awqos    (m_axi_awqos),  
-        .m_axi_awregion (m_axi_awregion),
-
-        .m_axi_wvalid   (m_axi_wvalid),
-        .m_axi_wready   (m_axi_wready),
-        .m_axi_wdata    (m_axi_wdata),
-        .m_axi_wstrb    (m_axi_wstrb),
-        .m_axi_wlast    (m_axi_wlast),
-        
-        .m_axi_bvalid   (m_axi_bvalid),
-        .m_axi_bready   (m_axi_bready),
-        .m_axi_bid      (m_axi_bid_unqual),
-        .m_axi_bresp    (m_axi_bresp),
-        
-        .m_axi_arvalid  (m_axi_arvalid),
-        .m_axi_arready  (m_axi_arready),
-        .m_axi_araddr   (m_axi_araddr_unqual),
-        .m_axi_arid     (m_axi_arid_unqual),        
-        .m_axi_arlen    (m_axi_arlen),
-        .m_axi_arsize   (m_axi_arsize),
-        .m_axi_arburst  (m_axi_arburst), 
-        .m_axi_arlock   (m_axi_arlock),    
-        .m_axi_arcache  (m_axi_arcache),
-        .m_axi_arprot   (m_axi_arprot),        
-        .m_axi_arqos    (m_axi_arqos),
-        .m_axi_arregion (m_axi_arregion),        
-        
-        .m_axi_rvalid   (m_axi_rvalid),
-        .m_axi_rready   (m_axi_rready),
-        .m_axi_rdata    (m_axi_rdata),        
-        .m_axi_rlast    (m_axi_rlast) ,       
-        .m_axi_rid      (m_axi_rid_unqual),
-        .m_axi_rresp    (m_axi_rresp)
-    );
-
-    `SCOPE_IO_SWITCH (1)
-    
-    Vortex vortex (
-        `SCOPE_IO_BIND  (0)
-
-        .clk            (clk),
-        .reset          (reset),
-
-        .mem_req_valid  (mem_req_valid),
-        .mem_req_rw     (mem_req_rw),
-        .mem_req_byteen (mem_req_byteen),
-        .mem_req_addr   (mem_req_addr),
-        .mem_req_data   (mem_req_data),
-        .mem_req_tag    (mem_req_tag),
-        .mem_req_ready  (mem_req_ready),
-
-        .mem_rsp_valid  (mem_rsp_valid),
-        .mem_rsp_data   (mem_rsp_data),
-        .mem_rsp_tag    (mem_rsp_tag),
-        .mem_rsp_ready  (mem_rsp_ready),
-
-        .dcr_wr_valid   (dcr_wr_valid),
-        .dcr_wr_addr    (dcr_wr_addr),
-        .dcr_wr_data    (dcr_wr_data),
-
-        .busy           (busy)
-    );
-
-endmodule

hw/rtl/afu/opae/ccip/ccip_if_pkg.sv

@@ -1,244 +0,0 @@
-// Date: 02/2/2016
-// Compliant with CCI-P spec v0.71
-package ccip_if_pkg;
-
-//=====================================================================
-// CCI-P interface defines
-//=====================================================================
-parameter CCIP_VERSION_NUMBER    = 12'h071;
-
-parameter CCIP_CLADDR_WIDTH      = 42; 
-parameter CCIP_CLDATA_WIDTH      = 512; 
-
-parameter CCIP_MMIOADDR_WIDTH    = 16; 
-parameter CCIP_MMIODATA_WIDTH    = 64; 
-parameter CCIP_TID_WIDTH         = 9; 
-
-parameter CCIP_MDATA_WIDTH       = 16; 
-
-
-// Number of requests that can be accepted after almost full is asserted. 
-parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8; 
-
-parameter CCIP_MMIO_RD_TIMEOUT = 512;
-
-parameter CCIP_SYNC_RESET_POLARITY=1;       // Active High Reset
-
-// Base types 
-//---------------------------------------------------------------------- 
-typedef logic [CCIP_CLADDR_WIDTH-1:0]   t_ccip_clAddr;
-typedef logic [CCIP_CLDATA_WIDTH-1:0]   t_ccip_clData;
-
-
-typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
-typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
-typedef logic [CCIP_TID_WIDTH-1:0]      t_ccip_tid;
-
-
-typedef logic [CCIP_MDATA_WIDTH-1:0]    t_ccip_mdata;
-typedef logic [1:0]                     t_ccip_clNum;
-typedef logic [2:0]                     t_ccip_qwIdx;
-
-  
-// Request Type  Encodings
-//----------------------------------------------------------------------
-// Channel 0
-typedef enum logic [3:0] {
-    eREQ_RDLINE_I  = 4'h0,      // Memory Read with FPGA Cache Hint=Invalid
-    eREQ_RDLINE_S  = 4'h1       // Memory Read with FPGA Cache Hint=Shared
-} t_ccip_c0_req;
-
-// Channel 1
-typedef enum logic [3:0] {
-    eREQ_WRLINE_I  = 4'h0,      // Memory Write with FPGA Cache Hint=Invalid
-    eREQ_WRLINE_M  = 4'h1,      // Memory Write with FPGA Cache Hint=Modified
-    eREQ_WRPUSH_I  = 4'h2,      // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
-    eREQ_WRFENCE   = 4'h4,      // Memory Write Fence
-//    eREQ_ATOMIC    = 4'h5,      // Atomic operation: Compare-Exchange for Memory Addr  ** NOT SUPPORTED CURRENTELY **
-    eREQ_INTR      = 4'h6       // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
-} t_ccip_c1_req;
-
-// Response Type  Encodings
-//----------------------------------------------------------------------
-// Channel 0
-typedef enum logic [3:0] {
-    eRSP_RDLINE     = 4'h0,     // Memory Read
-    eRSP_UMSG       = 4'h4      // UMsg received
-//    eRSP_ATOMIC     = 4'h5      // Atomic Operation: Compare-Exchange for Memory Addr
-} t_ccip_c0_rsp;
-
-// Channel 1
-typedef enum logic [3:0] {
-    eRSP_WRLINE     = 4'h0,     // Memory Write
-    eRSP_WRFENCE    = 4'h4,     // Memory Write Fence 
-    eRSP_INTR       = 4'h6      // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
-} t_ccip_c1_rsp;
-
-//
-// Virtual Channel Select
-//----------------------------------------------------------------------
-typedef enum logic [1:0] {
-    eVC_VA  = 2'b00,
-    eVC_VL0 = 2'b01,
-    eVC_VH0 = 2'b10,
-    eVC_VH1 = 2'b11
-} t_ccip_vc;
-
-// Multi-CL Memory Request
-//----------------------------------------------------------------------
-typedef enum logic [1:0] {
-    eCL_LEN_1 = 2'b00,
-    eCL_LEN_2 = 2'b01,
-    eCL_LEN_4 = 2'b11
-} t_ccip_clLen;
-
-//
-// Structures for Request and Response headers
-//----------------------------------------------------------------------
-typedef struct packed {
-    t_ccip_vc       vc_sel;
-    logic [1:0]     rsvd1;     // reserved, drive 0
-    t_ccip_clLen    cl_len;
-    t_ccip_c0_req   req_type;
-    logic [5:0]     rsvd0;     // reserved, drive 0
-    t_ccip_clAddr   address;
-    t_ccip_mdata    mdata;
-} t_ccip_c0_ReqMemHdr;
-parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
-
-typedef struct packed {
-    logic [5:0]     rsvd2;
-    t_ccip_vc       vc_sel;
-    logic           sop;
-    logic           rsvd1;     // reserved, drive 0
-    t_ccip_clLen    cl_len;
-    t_ccip_c1_req   req_type;
-    logic [5:0]     rsvd0;     // reserved, drive 0
-    t_ccip_clAddr   address;
-    t_ccip_mdata    mdata;
-} t_ccip_c1_ReqMemHdr;
-parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
-
-typedef struct packed {
-    logic [5:0]     rsvd2;          // reserved, drive 0
-    t_ccip_vc       vc_sel;
-    logic [3:0]     rsvd1;          // reserved, drive 0
-    t_ccip_c1_req   req_type;
-    logic [47:0]    rsvd0;          // reserved, drive 0
-    t_ccip_mdata    mdata;
-}t_ccip_c1_ReqFenceHdr;
-
-typedef struct packed {
-    t_ccip_vc       vc_used;
-    logic           rsvd1;          // reserved, don't care
-    logic           hit_miss;
-    logic [1:0]     rsvd0;          // reserved, don't care
-    t_ccip_clNum    cl_num;
-    t_ccip_c0_rsp   resp_type;
-    t_ccip_mdata    mdata;
-} t_ccip_c0_RspMemHdr;
-parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
-
-typedef struct packed {
-    t_ccip_vc       vc_used;
-    logic           rsvd1;          // reserved, don't care
-    logic           hit_miss;
-    logic           format;
-    logic           rsvd0;          // reserved, don't care
-    t_ccip_clNum    cl_num;
-    t_ccip_c1_rsp   resp_type;
-    t_ccip_mdata    mdata;
-} t_ccip_c1_RspMemHdr;
-parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
-
-typedef struct packed {
-    logic [7:0]     rsvd0;          // reserved, don't care
-    t_ccip_c1_rsp   resp_type;
-    t_ccip_mdata    mdata;
-} t_ccip_c1_RspFenceHdr;
-
-// Alternate Channel 0 MMIO request from host : 
-//  MMIO requests arrive on the same channel as read responses, sharing
-//  t_if_ccip_c0_Rx below.  When either mmioRdValid or mmioWrValid is set
-//  the message is an MMIO request and should be processed by casting
-//  t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
-typedef struct packed {
-    t_ccip_mmioAddr address;    // 4B aligned Mmio address
-    logic [1:0]     length;     // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
-    logic           rsvd;       // reserved, don't care
-    t_ccip_tid      tid;
-} t_ccip_c0_ReqMmioHdr;
-
-typedef struct packed {
-    t_ccip_tid     tid;         // Returned back from ReqMmioHdr
-} t_ccip_c2_RspMmioHdr;
-parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
-
-//------------------------------------------------------------------------
-// CCI-P Input & Output bus structures 
-// 
-// Users are encouraged to use these for AFU development
-//------------------------------------------------------------------------
-// Channel 0 : Memory Reads
-typedef struct packed { 
-    t_ccip_c0_ReqMemHdr  hdr;            // Request Header 
-    logic                valid;          // Request Valid 
-} t_if_ccip_c0_Tx; 
-
-
-// Channel 1 : Memory Writes,  Interrupts, CmpXchg
-typedef struct packed { 
-    t_ccip_c1_ReqMemHdr  hdr;            // Request Header 
-    t_ccip_clData        data;           // Request Data 
-    logic                valid;          // Request Wr Valid 
-} t_if_ccip_c1_Tx; 
-
-// Channel 2 : MMIO Read response
-typedef struct packed { 
-    t_ccip_c2_RspMmioHdr    hdr;            // Response Header 
-    logic                   mmioRdValid;    // Response Read Valid 
-    t_ccip_mmioData         data;           // Response Data 
-} t_if_ccip_c2_Tx; 
-  
-// Wrap all Tx channels
-typedef struct packed {
-    t_if_ccip_c0_Tx      c0; 
-    t_if_ccip_c1_Tx      c1; 
-    t_if_ccip_c2_Tx      c2; 
-} t_if_ccip_Tx;
-
-// Channel 0: Memory Read response, MMIO Request
-typedef struct packed { 
-    t_ccip_c0_RspMemHdr  hdr;            //  Rd Response/ MMIO req Header
-    t_ccip_clData        data;           //  Rd Data / MMIO req Data 
-    // Only one of valid, mmioRdValid and mmioWrValid may be set
-    // in a cycle.  When either mmioRdValid or mmioWrValid are true
-    // the hdr must be processed specially.  See t_ccip_c0_ReqMmioHdr
-    // above.
-    logic                rspValid;       //  Rd Response Valid 
-    logic                mmioRdValid;    //  MMIO Read Valid
-    logic                mmioWrValid;    //  MMIO Write Valid
-} t_if_ccip_c0_Rx;
-
-// Channel 1: Memory Writes 
-typedef struct packed { 
-    t_ccip_c1_RspMemHdr  hdr;            //  Response Header 
-    logic                rspValid;       //  Response Valid 
-} t_if_ccip_c1_Rx; 
-
-// Wrap all channels 
-typedef struct packed { 
-    logic                c0TxAlmFull;    //  C0 Request Channel Almost Full 
-    logic                c1TxAlmFull;    //  C1 Request Channel Almost Full 
-
-    t_if_ccip_c0_Rx      c0; 
-    t_if_ccip_c1_Rx      c1; 
-} t_if_ccip_Rx;
-
-
-typedef union packed { 
-    t_ccip_c0_RspMemHdr  rspMemHdr;
-    t_ccip_c0_ReqMmioHdr reqMmioHdr;
-} t_if_ccip_c0_RxHdr;
-
-endpackage

hw/rtl/afu/opae/ccip_interface_reg.sv

@@ -1,48 +0,0 @@
-// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
-
-// Register all interface signals
-
-import ccip_if_pkg::*;
-module ccip_interface_reg(
-  // CCI-P Clocks and Resets
-  input           logic             pClk,                    // 400MHz - CC-P clock domain. Primary Clock
-  input           logic             pck_cp2af_softReset_T0,  // CCI-P ACTIVE HIGH Soft Reset
-  input           logic [1:0]       pck_cp2af_pwrState_T0,   // CCI-P AFU Power State
-  input           logic             pck_cp2af_error_T0,      // CCI-P Protocol Error Detected
-  // Interface structures
-  input           t_if_ccip_Rx      pck_cp2af_sRx_T0,        // CCI-P Rx Port
-  input           t_if_ccip_Tx      pck_af2cp_sTx_T0,        // CCI-P Tx Port
-  
-  output          logic             pck_cp2af_softReset_T1,
-  output          logic [1:0]       pck_cp2af_pwrState_T1, 
-  output          logic             pck_cp2af_error_T1,    
-                                    
-  output          t_if_ccip_Rx      pck_cp2af_sRx_T1,      
-  output          t_if_ccip_Tx      pck_af2cp_sTx_T1
-
-);
-(* preserve *) logic             pck_cp2af_softReset_T0_q;
-(* preserve *) logic [1:0]       pck_cp2af_pwrState_T0_q;
-(* preserve *) logic             pck_cp2af_error_T0_q;
-(* preserve *) t_if_ccip_Rx      pck_cp2af_sRx_T0_q;     
-(* preserve *) t_if_ccip_Tx      pck_af2cp_sTx_T0_q;
-
-always@(posedge pClk)
-begin
-    pck_cp2af_softReset_T0_q   <= pck_cp2af_softReset_T0;
-    pck_cp2af_pwrState_T0_q    <= pck_cp2af_pwrState_T0;
-    pck_cp2af_error_T0_q       <= pck_cp2af_error_T0;
-    pck_cp2af_sRx_T0_q         <= pck_cp2af_sRx_T0;
-    pck_af2cp_sTx_T0_q         <= pck_af2cp_sTx_T0;
-end
-
-always_comb
-begin
-    pck_cp2af_softReset_T1      = pck_cp2af_softReset_T0_q;
-    pck_cp2af_pwrState_T1       = pck_cp2af_pwrState_T0_q;
-    pck_cp2af_error_T1          = pck_cp2af_error_T0_q;
-    pck_cp2af_sRx_T1            = pck_cp2af_sRx_T0_q;
-    pck_af2cp_sTx_T1            = pck_af2cp_sTx_T0_q;
-end
-
-endmodule

hw/rtl/afu/opae/ccip_std_afu.sv

@@ -1,123 +0,0 @@
-// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
-
-// Top Level Vortex Driver
-
-// To be done:
-// Check how to run this with OPAE. Looks like setup issue
-
-
-`include "platform_if.vh"
-
-import local_mem_cfg_pkg::*;
-
-module ccip_std_afu #(
-    parameter NUM_LOCAL_MEM_BANKS = 2
-) (
-    // CCI-P Clocks and Resets
-    input  logic        pClk,                 // Primary CCI-P interface clock.
-    input  logic        pClkDiv2,             // Aligned, pClk divided by 2.
-    input  logic        pClkDiv4,             // Aligned, pClk divided by 4.
-    input  logic        uClk_usr,             // User clock domain. Refer to clock programming guide.
-    input  logic        uClk_usrDiv2,         // Aligned, user clock divided by 2.
-    input  logic        pck_cp2af_softReset,  // CCI-P ACTIVE HIGH Soft Reset
-
-    input  logic [1:0]  pck_cp2af_pwrState,   // CCI-P AFU Power State
-    input  logic        pck_cp2af_error,      // CCI-P Protocol Error Detected
-
-    // CCI-P structures
-    input  t_if_ccip_Rx pck_cp2af_sRx,        // CCI-P Rx Port
-    output t_if_ccip_Tx pck_af2cp_sTx,        // CCI-P Tx Port
-
-    // Local memory interface
-    avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS]
-);
-
-    // ====================================================================
-    // Pick the proper clk and reset, as chosen by the AFU's JSON file
-    // ====================================================================
-
-    // The platform may transform the CCI-P clock from pClk to a clock
-    // chosen in the AFU's JSON file.
-    logic clk;
-    assign clk = `PLATFORM_PARAM_CCI_P_CLOCK;
-
-    logic reset;
-    assign reset = `PLATFORM_PARAM_CCI_P_RESET;
-
-
-    // ====================================================================
-    // Register signals at interface before consuming them
-    // ====================================================================
-
-    (* noprune *) logic [1:0]  cp2af_pwrState_T1;
-    (* noprune *) logic        cp2af_error_T1;
-
-    logic        reset_T1;
-    t_if_ccip_Rx cp2af_sRx_T1;
-    t_if_ccip_Tx af2cp_sTx_T0;
-
-    ccip_interface_reg inst_green_ccip_interface_reg
-       (
-        .pClk                    (clk),
-        .pck_cp2af_softReset_T0  (reset),
-        .pck_cp2af_pwrState_T0   (pck_cp2af_pwrState),
-        .pck_cp2af_error_T0      (pck_cp2af_error),
-        .pck_cp2af_sRx_T0        (pck_cp2af_sRx),
-        .pck_af2cp_sTx_T0        (af2cp_sTx_T0),
-
-        .pck_cp2af_softReset_T1  (reset_T1),
-        .pck_cp2af_pwrState_T1   (cp2af_pwrState_T1),
-        .pck_cp2af_error_T1      (cp2af_error_T1),
-        .pck_cp2af_sRx_T1        (cp2af_sRx_T1),
-        .pck_af2cp_sTx_T1        (pck_af2cp_sTx)
-        );
-
-
-    // ====================================================================
-    // User AFU goes here
-    // ====================================================================
-
-    t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS];
-    logic                 avs_waitrequest [NUM_LOCAL_MEM_BANKS];
-    t_local_mem_data      avs_readdata [NUM_LOCAL_MEM_BANKS];
-    logic                 avs_readdatavalid [NUM_LOCAL_MEM_BANKS];
-    t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS];
-    t_local_mem_data      avs_writedata [NUM_LOCAL_MEM_BANKS];
-    t_local_mem_addr      avs_address [NUM_LOCAL_MEM_BANKS];
-    logic                 avs_write [NUM_LOCAL_MEM_BANKS];
-    logic                 avs_read [NUM_LOCAL_MEM_BANKS];    
-
-    for (genvar b = 0; b < NUM_LOCAL_MEM_BANKS; b++) begin
-        assign local_mem[b].burstcount = avs_burstcount[b];
-        assign local_mem[b].writedata  = avs_writedata[b];
-        assign local_mem[b].address    = avs_address[b];
-        assign local_mem[b].byteenable = avs_byteenable[b];
-        assign local_mem[b].write      = avs_write[b];
-        assign local_mem[b].read       = avs_read[b];
-        
-        assign avs_waitrequest[b]   = local_mem[b].waitrequest;
-        assign avs_readdata[b]      = local_mem[b].readdata;
-        assign avs_readdatavalid[b] = local_mem[b].readdatavalid;
-    end
-
-    vortex_afu #(
-        .NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
-    ) afu (
-        .clk                 (clk),
-        .reset               (reset_T1),
-
-        .cp2af_sRxPort       (cp2af_sRx_T1),
-        .af2cp_sTxPort       (af2cp_sTx_T0),        
-
-        .avs_writedata       (avs_writedata),
-        .avs_readdata        (avs_readdata),
-        .avs_address         (avs_address),
-        .avs_waitrequest     (avs_waitrequest),
-        .avs_write           (avs_write),
-        .avs_read            (avs_read),
-        .avs_byteenable      (avs_byteenable),
-        .avs_burstcount      (avs_burstcount),
-        .avs_readdatavalid   (avs_readdatavalid)
-    );
-
-endmodule

hw/rtl/afu/opae/local_mem_cfg_pkg.sv

@@ -1,61 +0,0 @@
-//
-// Copyright (c) 2017, Intel Corporation
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// Redistributions of source code must retain the above copyright notice, this
-// list of conditions and the following disclaimer.
-//
-// Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// Neither the name of the Intel Corporation nor the names of its contributors
-// may be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-
-//`include "platform_afu_top_config.vh"
-
-`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
-
-package local_mem_cfg_pkg;
-
-    parameter LOCAL_MEM_VERSION_NUMBER = 1;
-
-    parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
-    parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
-
-    parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
-
-    // Number of bytes in a data line
-    parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
-
-
-    // Base types
-    // --------------------------------------------------------------------
-
-    typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
-    typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
-
-    typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
-
-    // Byte-level mask of a data line
-    typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
-
-endpackage // local_mem_cfg_pkg
-
-`endif // PLATFORM_PROVIDES_LOCAL_MEMORY

hw/rtl/afu/opae/vortex_afu.vh

@@ -1,39 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VORTEX_AFU_VH
-`define VORTEX_AFU_VH
-
-`define AFU_ACCEL_NAME "vortex_afu"
-`define AFU_ACCEL_UUID 128'h35F9452B_25C2_434C_93D5_6F8C60DB361C
-
-`define AFU_IMAGE_CMD_MEM_READ 1
-`define AFU_IMAGE_CMD_MEM_WRITE 2
-`define AFU_IMAGE_CMD_RUN 3
-`define AFU_IMAGE_CMD_DCR_WRITE 4
-`define AFU_IMAGE_CMD_MAX_VALUE 4
-
-`define AFU_IMAGE_MMIO_CMD_TYPE 10
-`define AFU_IMAGE_MMIO_CMD_ARG0 12
-`define AFU_IMAGE_MMIO_CMD_ARG1 14
-`define AFU_IMAGE_MMIO_CMD_ARG2 16
-`define AFU_IMAGE_MMIO_STATUS 18
-`define AFU_IMAGE_MMIO_SCOPE_READ 20
-`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
-`define AFU_IMAGE_MMIO_DEV_CAPS 24
-`define AFU_IMAGE_MMIO_ISA_CAPS 26
-
-`define AFU_IMAGE_POWER 0
-`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
-
-`endif // VORTEX_AFU_VH

hw/rtl/afu/xrt/VX_afu_ctrl.sv

@@ -1,419 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "vortex_afu.vh"
-
-module VX_afu_ctrl #(
-    parameter AXI_ADDR_WIDTH = 8,
-    parameter AXI_DATA_WIDTH = 32,
-    parameter AXI_NUM_BANKS  = 1
-) (
-    // axi4 lite slave signals
-    input  wire                         clk,
-    input  wire                         reset,
-    input  wire                         clk_en,
-    
-    input  wire                         s_axi_awvalid,
-    input  wire [AXI_ADDR_WIDTH-1:0]    s_axi_awaddr,    
-    output wire                         s_axi_awready,
-
-    input  wire                         s_axi_wvalid,
-    input  wire [AXI_DATA_WIDTH-1:0]    s_axi_wdata,
-    input  wire [AXI_DATA_WIDTH/8-1:0]  s_axi_wstrb,    
-    output wire                         s_axi_wready,
-
-    output wire                         s_axi_bvalid,
-    output wire [1:0]                   s_axi_bresp,    
-    input  wire                         s_axi_bready,
-
-    input  wire                         s_axi_arvalid,
-    input  wire [AXI_ADDR_WIDTH-1:0]    s_axi_araddr,    
-    output wire                         s_axi_arready,
-
-    output wire                         s_axi_rvalid,
-    output wire [AXI_DATA_WIDTH-1:0]    s_axi_rdata,
-    output wire [1:0]                   s_axi_rresp,    
-    input  wire                         s_axi_rready,    
-    
-    output wire                         ap_reset,
-    output wire                         ap_start,
-    input  wire                         ap_done,
-    input  wire                         ap_ready,
-    input  wire                         ap_idle,  
-    output wire                         interrupt,
-
-`ifdef SCOPE
-    input wire                          scope_bus_in,
-    output wire                         scope_bus_out,
-`endif
-
-    output wire [63:0]                  mem_base [AXI_NUM_BANKS],
-
-    output wire                         dcr_wr_valid,
-    output wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
-    output wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data
-);
-
-    // Address Info
-    // 0x00 : Control signals
-    //        bit 0  - ap_start (Read/Write/COH)
-    //        bit 1  - ap_done (Read/COR)
-    //        bit 2  - ap_idle (Read)
-    //        bit 3  - ap_ready (Read)
-    //        bit 4  - ap_reset (Write)
-    //        bit 7  - auto_restart (Read/Write)
-    //        others - reserved
-    // 0x04 : Global Interrupt Enable Register
-    //        bit 0  - Global Interrupt Enable (Read/Write)
-    //        others - reserved
-    // 0x08 : IP Interrupt Enable Register (Read/Write)
-    //        bit 0  - Channel 0 (ap_done)
-    //        bit 1  - Channel 1 (ap_ready)
-    //        others - reserved
-    // 0x0c : IP Interrupt Status Register (Read/TOW)
-    //        bit 0  - Channel 0 (ap_done)
-    //        bit 1  - Channel 1 (ap_ready)
-    //        others - reserved
-    // 0x10 : Low 32-bit Data signal of DEV_CAPS
-    // 0x14 : High 32-bit Data signal of DEV_CAPS
-    // 0x18 : Control signal of DEV_CAPS
-    // 0x1C : Low 32-bit Data signal of ISA_CAPS
-    // 0x20 : High 32-bit Data signal of ISA_CAPS
-    // 0x24 : Control signal of ISA_CAPS
-    // 0x28 : Low 32-bit Data signal of DCR
-    // 0x2C : High 32-bit Data signal of DCR
-    // 0x30 : Control signal of DCR
-    // 0x34 : Low 32-bit Data signal of SCP
-    // 0x38 : High 32-bit Data signal of SCP
-    // 0x3C : Control signal of SCP
-    // 0x40 : Low 32-bit Data signal of MEM
-    // 0x44 : High 32-bit Data signal of MEM
-    // 0x48 : Control signal of MEM
-    // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
-
-    // Parameters    
-    localparam
-        ADDR_AP_CTRL    = 8'h00,
-        ADDR_GIE        = 8'h04,
-        ADDR_IER        = 8'h08,
-        ADDR_ISR        = 8'h0C,
-
-        ADDR_DEV_0      = 8'h10,
-        ADDR_DEV_1      = 8'h14,
-        ADDR_DEV_CTRL   = 8'h18,
-        
-        ADDR_ISA_0      = 8'h1C,
-        ADDR_ISA_1      = 8'h20,
-        ADDR_ISA_CTRL   = 8'h24,
-        
-        ADDR_DCR_0      = 8'h28,
-        ADDR_DCR_1      = 8'h2C,
-        ADDR_DCR_CTRL   = 8'h30,
-
-        ADDR_SCP_0      = 8'h34,
-        ADDR_SCP_1      = 8'h38,
-        ADDR_SCP_CTRL   = 8'h3C,
-
-        ADDR_MEM_0      = 8'h40,
-        ADDR_MEM_1      = 8'h44,
-        ADDR_MEM_CTRL   = 8'h48,
-        
-        ADDR_BITS       = 8;
-
-    localparam
-        WSTATE_IDLE     = 2'd0,
-        WSTATE_DATA     = 2'd1,
-        WSTATE_RESP     = 2'd2;
-    
-    localparam
-        RSTATE_IDLE     = 2'd0,
-        RSTATE_DATA     = 2'd1;
-
-    // device caps
-    wire [63:0] dev_caps = {16'b0,
-                            8'(`SM_ENABLED ? `SMEM_LOG_SIZE : 0),
-                            16'(`NUM_CORES * `NUM_CLUSTERS), 
-                            8'(`NUM_WARPS), 
-                            8'(`NUM_THREADS), 
-                            8'(`IMPLEMENTATION_ID)};
-
-    wire [63:0] isa_caps = {32'(`MISA_EXT), 
-                            2'(`CLOG2(`XLEN)-4), 
-                            30'(`MISA_STD)};
-
-    reg [1:0]   wstate;
-    reg [ADDR_BITS-1:0] waddr;
-    wire [31:0] wmask;
-    wire        s_axi_aw_fire;
-    wire        s_axi_w_fire;
-    
-    reg [1:0]   rstate;
-    reg [31:0]  rdata;
-    wire [ADDR_BITS-1:0] raddr;
-    wire        s_axi_ar_fire;
-
-    reg         ap_reset_r;
-    reg         ap_start_r;
-    reg         auto_restart_r;
-    reg         gie_r;
-    reg [1:0]   ier_r;
-    reg [1:0]   isr_r;
-    reg [63:0]  mem_r [AXI_NUM_BANKS];
-    reg [31:0]  dcra_r;
-    reg [31:0]  dcrv_r;
-    reg         dcr_wr_valid_r;   
-      
-`ifdef SCOPE
-
-    reg [63:0] scope_bus_wdata;
-    reg [63:0] scope_bus_rdata;    
-    reg [5:0] scope_bus_ctr;
-
-    reg cmd_scope_reading;
-    reg cmd_scope_writing;
-    reg scope_bus_out_r;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            cmd_scope_reading <= 0;
-            cmd_scope_writing <= 0;            
-            scope_bus_ctr <= '0;
-            scope_bus_out_r <= 0;
-        end else if (clk_en) begin
-            if (s_axi_w_fire && waddr == ADDR_SCP_0) begin
-                scope_bus_wdata[31:0] <= (s_axi_wdata & wmask) | (scope_bus_wdata[31:0] & ~wmask);
-            end
-            if (s_axi_w_fire && waddr == ADDR_SCP_1) begin
-                scope_bus_wdata[63:32] <= (s_axi_wdata & wmask) | (scope_bus_wdata[63:32] & ~wmask);           
-                cmd_scope_writing <= 1;
-                scope_bus_out_r   <= 1;    
-                scope_bus_ctr     <= 63;
-            end             
-            if (scope_bus_in) begin
-                cmd_scope_reading <= 1;
-                scope_bus_ctr     <= 63;
-            end     
-            if (cmd_scope_reading) begin
-                scope_bus_rdata <= {scope_bus_rdata[62:0], scope_bus_in};
-                scope_bus_ctr   <= scope_bus_ctr - 1;
-                if (scope_bus_ctr == 0) begin
-                    cmd_scope_reading <= 0;
-                end
-            end            
-            if (cmd_scope_writing) begin
-                scope_bus_out_r <= 1'(scope_bus_wdata >> scope_bus_ctr);
-                scope_bus_ctr <= scope_bus_ctr - 1;
-                if (scope_bus_ctr == 0) begin
-                    cmd_scope_writing <= 0;
-                end
-            end          
-        end
-    end
-
-    assign scope_bus_out = scope_bus_out_r;
-
-`endif
-
-    // AXI Write       
-
-    assign s_axi_awready = (wstate == WSTATE_IDLE);
-    assign s_axi_wready  = (wstate == WSTATE_DATA);
-    assign s_axi_bvalid  = (wstate == WSTATE_RESP);
-    assign s_axi_bresp   = 2'b00;  // OKAY
-
-    assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready;
-    assign s_axi_w_fire  = s_axi_wvalid && s_axi_wready;
-
-    for (genvar i = 0; i < 4; ++i) begin
-        assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}};
-    end
-
-    // wstate
-    always @(posedge clk) begin
-        if (reset) begin
-            wstate <= WSTATE_IDLE;
-        end else if (clk_en) begin
-            case (wstate)
-            WSTATE_IDLE: wstate <= s_axi_awvalid ? WSTATE_DATA : WSTATE_IDLE;
-            WSTATE_DATA: wstate <= s_axi_wvalid ? WSTATE_RESP : WSTATE_DATA;
-            WSTATE_RESP: wstate <= s_axi_bready ? WSTATE_IDLE : WSTATE_RESP;
-            default:     wstate <= WSTATE_IDLE;
-            endcase
-        end
-    end
-
-    // waddr
-    always @(posedge clk) begin
-        if (clk_en) begin
-            if (s_axi_aw_fire)
-                waddr <= s_axi_awaddr[ADDR_BITS-1:0];
-        end
-    end
-    
-    // wdata
-    always @(posedge clk) begin
-        if (reset) begin
-            ap_start_r <= 0;
-            ap_reset_r <= 0;
-            auto_restart_r <= 0;
-            
-            gie_r <= 0;
-            ier_r <= '0;
-            isr_r <= '0;
-
-            dcra_r <= '0;
-            dcrv_r <= '0;
-            dcr_wr_valid_r <= 0;
-
-            for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin
-                mem_r[i] <= '0;
-            end
-        end else if (clk_en) begin
-            if (ap_ready)
-                ap_start_r <= auto_restart_r;
-
-            dcr_wr_valid_r <= 0;
-
-            if (s_axi_w_fire) begin
-                case (waddr)
-                ADDR_AP_CTRL: begin
-                    if (s_axi_wstrb[0]) begin 
-                        if (s_axi_wdata[0])
-                            ap_start_r <= 1;
-                        if (s_axi_wdata[4])
-                            ap_reset_r <= 1;
-                        if (s_axi_wdata[7])
-                            auto_restart_r <= 1;
-                    end
-                end
-                ADDR_GIE: begin
-                    if (s_axi_wstrb[0])
-                        gie_r <= s_axi_wdata[0];
-                end
-                ADDR_IER: begin
-                    if (s_axi_wstrb[0])
-                        ier_r <= s_axi_wdata[1:0];
-                end
-                ADDR_ISR: begin
-                    if (s_axi_wstrb[0])
-                        isr_r <= isr_r ^ s_axi_wdata[1:0];
-                end
-                ADDR_DCR_0: begin
-                    dcra_r <= (s_axi_wdata & wmask) | (dcra_r & ~wmask);
-                end
-                ADDR_DCR_1: begin
-                    dcrv_r <= (s_axi_wdata & wmask) | (dcrv_r & ~wmask);
-                    dcr_wr_valid_r <= 1;
-                end
-                default: begin
-                    for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin
-                        if (waddr == (ADDR_MEM_0 + i * 12)) begin
-                            mem_r[i][31:0] <= (s_axi_wdata & wmask) | (mem_r[i][31:0] & ~wmask);
-                        end
-                        if (waddr == (ADDR_MEM_1 + i * 12)) begin
-                            mem_r[i][63:32] <= (s_axi_wdata & wmask) | (mem_r[i][63:32] & ~wmask);
-                        end
-                    end
-                end
-                endcase
-                
-                if (ier_r[0] & ap_done)
-                    isr_r[0] <= 1'b1;
-                if (ier_r[1] & ap_ready)
-                    isr_r[1] <= 1'b1;
-            end
-        end
-    end
-
-    // AXI Read
-
-    assign s_axi_arready = (rstate == RSTATE_IDLE);
-    assign s_axi_rvalid  = (rstate == RSTATE_DATA);
-    assign s_axi_rdata   = rdata;
-    assign s_axi_rresp   = 2'b00;  // OKAY
-    
-    assign s_axi_ar_fire = s_axi_arvalid && s_axi_arready;
-    assign raddr = s_axi_araddr[ADDR_BITS-1:0];
-    
-    // rstate
-    always @(posedge clk) begin
-        if (reset) begin
-            rstate <= RSTATE_IDLE;
-        end else if (clk_en) begin
-            case (rstate)
-            RSTATE_IDLE: rstate <= s_axi_arvalid ? RSTATE_DATA : RSTATE_IDLE;
-            RSTATE_DATA: rstate <= (s_axi_rready & s_axi_rvalid) ? RSTATE_IDLE : RSTATE_DATA;
-            default:     rstate <= RSTATE_IDLE;
-            endcase
-        end
-    end
-
-    // rdata
-    always @(posedge clk) begin
-        if (clk_en) begin
-            if (s_axi_ar_fire) begin
-                rdata <= '0;
-                case (raddr)
-                    ADDR_AP_CTRL: begin
-                        rdata[0] <= ap_start_r;
-                        rdata[1] <= ap_done;
-                        rdata[2] <= ap_idle;
-                        rdata[3] <= ap_ready;
-                        rdata[7] <= auto_restart_r;
-                    end
-                    ADDR_GIE: begin
-                        rdata <= 32'(gie_r);
-                    end
-                    ADDR_IER: begin
-                        rdata <= 32'(ier_r);
-                    end
-                    ADDR_ISR: begin
-                        rdata <= 32'(isr_r);
-                    end
-                    ADDR_DEV_0: begin
-                        rdata <= dev_caps[31:0];
-                    end
-                    ADDR_DEV_1: begin
-                        rdata <= dev_caps[63:32];
-                    end
-                    ADDR_ISA_0: begin
-                        rdata <= isa_caps[31:0];
-                    end
-                    ADDR_ISA_1: begin
-                        rdata <= isa_caps[63:32];
-                    end
-                `ifdef SCOPE
-                    ADDR_SCP_0: begin
-                        rdata <= scope_bus_rdata[31:0];
-                    end
-                    ADDR_SCP_1: begin
-                        rdata <= scope_bus_rdata[63:32];
-                    end
-                `endif
-                    default:;
-                endcase
-            end
-        end
-    end
-
-    assign ap_reset  = ap_reset_r;
-    assign ap_start  = ap_start_r;
-    assign interrupt = gie_r & (| isr_r);
-
-    assign mem_base  = mem_r;
-
-    assign dcr_wr_valid = dcr_wr_valid_r;
-    assign dcr_wr_addr  = `VX_DCR_ADDR_WIDTH'(dcra_r);
-    assign dcr_wr_data  = `VX_DCR_DATA_WIDTH'(dcrv_r);    
-
-endmodule

hw/rtl/afu/xrt/VX_afu_wrap.sv

@@ -1,412 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "vortex_afu.vh"
-
-module VX_afu_wrap #( 
-	  parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
-	  parameter C_S_AXI_CTRL_DATA_WIDTH	= 32,
-	  parameter C_M_AXI_MEM_ID_WIDTH    = 16,
-	  parameter C_M_AXI_MEM_ADDR_WIDTH  = 32,
-	  parameter C_M_AXI_MEM_DATA_WIDTH  = 512
-) (
-    // System signals
-    input wire ap_clk,
-    input wire ap_rst_n,
-
-    // AXI4 master interface
-	`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
-
-    // AXI4-Lite slave interface
-    input  wire                                 s_axi_ctrl_awvalid,
-    output wire                                 s_axi_ctrl_awready,
-    input  wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0]   s_axi_ctrl_awaddr,
-    input  wire                                 s_axi_ctrl_wvalid,
-    output wire                                 s_axi_ctrl_wready,
-    input  wire [C_S_AXI_CTRL_DATA_WIDTH-1:0]   s_axi_ctrl_wdata,
-    input  wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
-    input  wire                                 s_axi_ctrl_arvalid,
-    output wire                                 s_axi_ctrl_arready,
-    input  wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0]   s_axi_ctrl_araddr,
-    output wire                                 s_axi_ctrl_rvalid,
-    input  wire                                 s_axi_ctrl_rready,
-    output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0]   s_axi_ctrl_rdata,
-    output wire [1:0]                           s_axi_ctrl_rresp,
-    output wire                                 s_axi_ctrl_bvalid,
-    input  wire                                 s_axi_ctrl_bready,
-    output wire [1:0]                           s_axi_ctrl_bresp,
-    
-    output wire                                 interrupt 
-);
-	localparam C_M_AXI_MEM_NUM_BANKS = `M_AXI_MEM_NUM_BANKS;
-
-	localparam STATE_IDLE = 0;
-    localparam STATE_RUN  = 1;
-
-	wire                                 m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_ADDR_WIDTH-1:0]    m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_ID_WIDTH-1:0]      m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [7:0]                           m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_DATA_WIDTH-1:0]    m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0]  m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];	
-    wire                                 m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_ID_WIDTH-1:0]      m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [1:0]                           m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_ADDR_WIDTH-1:0]    m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_ID_WIDTH-1:0]      m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [7:0]                           m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_DATA_WIDTH-1:0]    m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
-    wire                                 m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [C_M_AXI_MEM_ID_WIDTH-1:0]      m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS];
-    wire [1:0]                           m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS];
-
-	// convert memory interface to array
-	`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
-
-	wire clk = ap_clk;
-	wire reset = ~ap_rst_n;
-
-	reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
-	reg [15:0] vx_pending_writes;
-	reg vx_busy_wait;
-	reg vx_running;
-	
-	wire vx_busy;
-
-	wire [63:0] mem_base [C_M_AXI_MEM_NUM_BANKS];        
-
-	wire                          dcr_wr_valid;
-	wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr;
-	wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data;
-
-	reg state;
-
-	wire ap_reset;
-	wire ap_start;
-	wire ap_idle  = ~vx_running;
-	wire ap_done  = ~(state == STATE_RUN || vx_pending_writes != 0);
-	wire ap_ready = 1'b1;
-
-`ifdef SCOPE
-	wire scope_bus_in;
-	wire scope_bus_out;
-  	wire scope_reset = reset; 
-`endif
-
-	always @(posedge ap_clk) begin
-		if (reset || ap_reset) begin
-			state <= STATE_IDLE;
-			vx_busy_wait  <= 0;
-			vx_running    <= 0;
-		end else begin
-			case (state)
-			STATE_IDLE: begin
-				if (ap_start) begin	
-				`ifdef DBG_TRACE_AFU
-					`TRACE(2, ("%d: STATE RUN\n", $time));
-				`endif				
-					state <= STATE_RUN;
-					vx_running <= 0;
-				end
-			end
-			STATE_RUN: begin			
-				if (vx_running) begin
-					if (vx_busy_wait) begin
-						// wait until processor goes busy
-						if (vx_busy) begin
-							vx_busy_wait <= 0;
-						end
-					end else begin
-						// wait until the processor is not busy
-						if (~vx_busy) begin
-							state <= STATE_IDLE;
-						`ifdef DBG_TRACE_AFU
-							`TRACE(2, ("%d: AFU: End execution\n", $time));
-							`TRACE(2, ("%d: STATE IDLE\n", $time));
-						`endif
-						end
-					end
-				end else begin
-					// wait until the reset sequence is complete
-					if (vx_reset_ctr == (`RESET_DELAY-1)) begin
-					`ifdef DBG_TRACE_AFU
-						`TRACE(2, ("%d: AFU: Begin execution\n", $time));
-					`endif
-						vx_running    <= 1;					
-						vx_busy_wait  <= 1;
-					end
-				end
-			end
-			endcase
-		end
-	end
-
-	reg m_axi_mem_wfire;
-	reg m_axi_mem_bfire;
-
-	always @(*) begin
-		m_axi_mem_wfire = 0;
-		m_axi_mem_bfire = 0;
-		for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
-			m_axi_mem_wfire |= m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i];
-			m_axi_mem_bfire |= m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i];
-		end
-	end
-
-	always @(posedge ap_clk) begin
-		if (reset || ap_reset) begin
-			vx_pending_writes <= '0;
-		end else begin
-			if (m_axi_mem_wfire && ~m_axi_mem_bfire)
-				vx_pending_writes <= vx_pending_writes + 1;
-			if (~m_axi_mem_wfire && m_axi_mem_bfire)
-				vx_pending_writes <= vx_pending_writes - 1;
-		end
-	end
-
-	always @(posedge ap_clk) begin
-		if (state == STATE_RUN) begin
-			vx_reset_ctr <= vx_reset_ctr + 1;			
-		end else begin
-			vx_reset_ctr <= '0;
-		end
-	end
-
-	VX_afu_ctrl #(
-		.AXI_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
-		.AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
-		.AXI_NUM_BANKS  (C_M_AXI_MEM_NUM_BANKS)
-	) afu_ctrl (
-		.clk       		(ap_clk),
-		.reset     		(reset || ap_reset),	
-		.clk_en         (1'b1),
-		
-		.s_axi_awvalid  (s_axi_ctrl_awvalid),
-		.s_axi_awready  (s_axi_ctrl_awready),
-		.s_axi_awaddr   (s_axi_ctrl_awaddr),
-		.s_axi_wvalid   (s_axi_ctrl_wvalid),
-		.s_axi_wready   (s_axi_ctrl_wready),
-		.s_axi_wdata    (s_axi_ctrl_wdata),
-		.s_axi_wstrb    (s_axi_ctrl_wstrb),
-		.s_axi_arvalid  (s_axi_ctrl_arvalid),
-		.s_axi_arready  (s_axi_ctrl_arready),
-		.s_axi_araddr   (s_axi_ctrl_araddr),
-		.s_axi_rvalid   (s_axi_ctrl_rvalid),
-		.s_axi_rready   (s_axi_ctrl_rready),
-		.s_axi_rdata    (s_axi_ctrl_rdata),
-		.s_axi_rresp    (s_axi_ctrl_rresp),
-		.s_axi_bvalid   (s_axi_ctrl_bvalid),
-		.s_axi_bready   (s_axi_ctrl_bready),
-		.s_axi_bresp    (s_axi_ctrl_bresp),
-
-		.ap_reset  		(ap_reset),
-		.ap_start  		(ap_start),
-		.ap_done     	(ap_done),
-		.ap_ready       (ap_ready),
-		.ap_idle     	(ap_idle),
-		.interrupt 		(interrupt),
-
-	`ifdef SCOPE
-		.scope_bus_in   (scope_bus_out),	
-		.scope_bus_out  (scope_bus_in),
-	`endif	
-
-		.mem_base       (mem_base),
-
-		.dcr_wr_valid	(dcr_wr_valid),
-		.dcr_wr_addr	(dcr_wr_addr),
-		.dcr_wr_data	(dcr_wr_data)
-	);
-
-	wire [`XLEN-1:0] m_axi_mem_awaddr_w [C_M_AXI_MEM_NUM_BANKS];
-	wire [`XLEN-1:0] m_axi_mem_araddr_w [C_M_AXI_MEM_NUM_BANKS];
-
-	for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
-		assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
-		assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
-	end
-
-	`SCOPE_IO_SWITCH (2)
-
-	Vortex_axi #(
-		.AXI_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH),
-		.AXI_ADDR_WIDTH (`XLEN),
-		.AXI_TID_WIDTH  (C_M_AXI_MEM_ID_WIDTH),
-		.AXI_NUM_BANKS  (C_M_AXI_MEM_NUM_BANKS)
-	) vortex_axi (
-		`SCOPE_IO_BIND  (1)
-
-		.clk			(ap_clk),
-		.reset			(reset || ap_reset || ~vx_running),
-		
-		.m_axi_awvalid	(m_axi_mem_awvalid_a),
-		.m_axi_awready	(m_axi_mem_awready_a),
-		.m_axi_awaddr	(m_axi_mem_awaddr_w),
-		.m_axi_awid		(m_axi_mem_awid_a),
-		.m_axi_awlen    (m_axi_mem_awlen_a),
-		`UNUSED_PIN (m_axi_awsize),
-		`UNUSED_PIN (m_axi_awburst),
-		`UNUSED_PIN (m_axi_awlock),
-		`UNUSED_PIN (m_axi_awcache),
-		`UNUSED_PIN (m_axi_awprot),
-		`UNUSED_PIN (m_axi_awqos),		  
-    	`UNUSED_PIN (m_axi_awregion),
-
-		.m_axi_wvalid	(m_axi_mem_wvalid_a),
-		.m_axi_wready	(m_axi_mem_wready_a),
-		.m_axi_wdata	(m_axi_mem_wdata_a),
-		.m_axi_wstrb	(m_axi_mem_wstrb_a),
-		.m_axi_wlast	(m_axi_mem_wlast_a),
-
-		.m_axi_bvalid	(m_axi_mem_bvalid_a),
-		.m_axi_bready	(m_axi_mem_bready_a),
-		.m_axi_bid		(m_axi_mem_bid_a),
-		.m_axi_bresp	(m_axi_mem_bresp_a),		
-
-		.m_axi_arvalid	(m_axi_mem_arvalid_a),
-		.m_axi_arready	(m_axi_mem_arready_a),
-		.m_axi_araddr	(m_axi_mem_araddr_w),
-		.m_axi_arid		(m_axi_mem_arid_a),
-		.m_axi_arlen	(m_axi_mem_arlen_a),
-		`UNUSED_PIN (m_axi_arsize),
-		`UNUSED_PIN (m_axi_arburst),
-		`UNUSED_PIN (m_axi_arlock),
-		`UNUSED_PIN (m_axi_arcache),
-		`UNUSED_PIN (m_axi_arprot),
-		`UNUSED_PIN (m_axi_arqos),		
-        `UNUSED_PIN (m_axi_arregion),
-
-		.m_axi_rvalid	(m_axi_mem_rvalid_a),
-		.m_axi_rready	(m_axi_mem_rready_a),
-		.m_axi_rdata	(m_axi_mem_rdata_a),
-		.m_axi_rlast	(m_axi_mem_rlast_a),
-		.m_axi_rid    	(m_axi_mem_rid_a),
-		.m_axi_rresp	(m_axi_mem_rresp_a),
-
-		.dcr_wr_valid	(dcr_wr_valid),
-		.dcr_wr_addr	(dcr_wr_addr),
-		.dcr_wr_data	(dcr_wr_data),
-
-		.busy			(vx_busy)
-	);
-
-    // SCOPE //////////////////////////////////////////////////////////////////////
-
-`ifdef DBG_SCOPE_AFU
-`ifdef SCOPE
-	`define TRIGGERS { \
-		reset, \
-		ap_start, \
-		ap_done, \
-		ap_idle, \
-		interrupt, \
-		vx_busy_wait, \
-		vx_busy, \
-		vx_running \
-	}
-
-	`define PROBES { \
-		vx_pending_writes \
-	}
-
-    VX_scope_tap #(
-        .SCOPE_ID (0),
-        .TRIGGERW ($bits(`TRIGGERS)),
-        .PROBEW   ($bits(`PROBES))
-    ) scope_tap (
-        .clk(clk),
-        .reset(scope_reset_w[0]),
-        .start(1'b0),
-        .stop(1'b0),
-        .triggers(`TRIGGERS),
-        .probes(`PROBES),
-        .bus_in(scope_bus_in_w[0]),
-        .bus_out(scope_bus_out_w[0])
-    );
-`endif
-`ifdef CHIPSCOPE
-    ila_afu ila_afu_inst (
-      	.clk (ap_clk),
-		.probe0 ({
-        	ap_start,
-        	ap_done,
-			ap_idle,
-			interrupt
-		}),
-		.probe1 ({
-        	vx_pending_writes,
-			vx_busy_wait,
-			vx_busy,
-			vx_running
-		})
-    );
-`endif
-`else
-    `SCOPE_IO_UNUSED_W(0)
-`endif
-
-`ifdef SIMULATION
-`ifndef VERILATOR
-	// disable assertions until full reset
-	reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr;
-	reg assert_enabled;
-	initial begin
-		$assertoff(0, vortex_axi);  
-	end	
-	always @(posedge ap_clk) begin
-		if (reset) begin
-			assert_delay_ctr <= '0;
-			assert_enabled   <= 0;
-		end else begin			
-			if (~assert_enabled) begin
-				if (assert_delay_ctr == (`RESET_DELAY-1)) begin
-					assert_enabled <= 1;
-					$asserton(0, vortex_axi); // enable assertions
-				end else begin
-					assert_delay_ctr <= assert_delay_ctr + 1;
-				end
-			end
-		end
-	end
-`endif
-`endif
-
-`ifdef DBG_TRACE_AFU
-    always @(posedge ap_clk) begin
-		for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
-			if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
-				`TRACE(2, ("%d: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]));                
-			end
-			if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin
-				`TRACE(2, ("%d: AFU Wr Req [%0d]: data=0x%0h\n", $time, i, m_axi_mem_wdata_a[i]));                
-			end
-			if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin   
-				`TRACE(2, ("%d: AFU Rd Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]));
-			end
-			if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin
-				`TRACE(2, ("%d: AVS Rd Rsp [%0d]: data=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]));
-			end
-		end
-  	end
-`endif
-	
-endmodule

hw/rtl/afu/xrt/vortex_afu.v

@@ -1,85 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "vortex_afu.vh"
-
-module vortex_afu #(
-	parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
-	parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
-	parameter C_M_AXI_MEM_ID_WIDTH 	  = `M_AXI_MEM_ID_WIDTH,
-	parameter C_M_AXI_MEM_ADDR_WIDTH  = 64,
-	parameter C_M_AXI_MEM_DATA_WIDTH  = `VX_MEM_DATA_WIDTH    
-) (
-	// System signals
-	input wire 									ap_clk,
-	input wire 									ap_rst_n,
-	
-	// AXI4 master interface
-	`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
-
-    // AXI4-Lite slave interface
-    input  wire                                 s_axi_ctrl_awvalid,
-    output wire                                 s_axi_ctrl_awready,
-    input  wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0]   s_axi_ctrl_awaddr,
-    input  wire                                 s_axi_ctrl_wvalid,
-    output wire                                 s_axi_ctrl_wready,
-    input  wire [C_S_AXI_CTRL_DATA_WIDTH-1:0]   s_axi_ctrl_wdata,
-    input  wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
-    input  wire                                 s_axi_ctrl_arvalid,
-    output wire                                 s_axi_ctrl_arready,
-    input  wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0]   s_axi_ctrl_araddr,
-    output wire                                 s_axi_ctrl_rvalid,
-    input  wire                                 s_axi_ctrl_rready,
-    output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0]   s_axi_ctrl_rdata,
-    output wire [1:0]                           s_axi_ctrl_rresp,
-    output wire                                 s_axi_ctrl_bvalid,
-    input  wire                                 s_axi_ctrl_bready,
-    output wire [1:0]                           s_axi_ctrl_bresp,
-    
-    output wire                                 interrupt 
-);
-
-	VX_afu_wrap #(
-		.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
-		.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
-		.C_M_AXI_MEM_ID_WIDTH    (C_M_AXI_MEM_ID_WIDTH),
-		.C_M_AXI_MEM_ADDR_WIDTH  (C_M_AXI_MEM_ADDR_WIDTH),
-		.C_M_AXI_MEM_DATA_WIDTH  (C_M_AXI_MEM_DATA_WIDTH)
-	) afu_wrap (
-		.ap_clk             (ap_clk),
-		.ap_rst_n           (ap_rst_n),
-
-		`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
-		
-		.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
-		.s_axi_ctrl_awready (s_axi_ctrl_awready),
-		.s_axi_ctrl_awaddr  (s_axi_ctrl_awaddr),		
-		.s_axi_ctrl_wvalid  (s_axi_ctrl_wvalid),
-		.s_axi_ctrl_wready  (s_axi_ctrl_wready),
-		.s_axi_ctrl_wdata   (s_axi_ctrl_wdata),
-		.s_axi_ctrl_wstrb   (s_axi_ctrl_wstrb),
-		.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
-		.s_axi_ctrl_arready (s_axi_ctrl_arready),
-		.s_axi_ctrl_araddr  (s_axi_ctrl_araddr),
-		.s_axi_ctrl_rvalid  (s_axi_ctrl_rvalid),
-		.s_axi_ctrl_rready  (s_axi_ctrl_rready),
-		.s_axi_ctrl_rdata   (s_axi_ctrl_rdata),
-		.s_axi_ctrl_rresp   (s_axi_ctrl_rresp),
-		.s_axi_ctrl_bvalid  (s_axi_ctrl_bvalid),
-		.s_axi_ctrl_bready  (s_axi_ctrl_bready),
-		.s_axi_ctrl_bresp   (s_axi_ctrl_bresp),
-
-		.interrupt          (interrupt)
-	);
-	
-endmodule

hw/rtl/afu/xrt/vortex_afu.vh

@@ -1,108 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VORTEX_AFU_VH
-`define VORTEX_AFU_VH
-
-`ifndef M_AXI_MEM_NUM_BANKS
-`define M_AXI_MEM_NUM_BANKS 1
-`endif
-
-`ifndef M_AXI_MEM_ID_WIDTH
-`define M_AXI_MEM_ID_WIDTH 32
-`endif
-
-`define GEN_AXI_MEM(i) \
-	output wire                                 m_axi_mem_``i``_awvalid, \
-	input  wire                                 m_axi_mem_``i``_awready, \
-	output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] 	m_axi_mem_``i``_awaddr, \
-	output wire [C_M_AXI_MEM_ID_WIDTH-1:0]   	m_axi_mem_``i``_awid, \
-	output wire [7:0]                           m_axi_mem_``i``_awlen, \
-	output wire                                 m_axi_mem_``i``_wvalid, \
-	input  wire                                 m_axi_mem_``i``_wready, \
-	output wire [C_M_AXI_MEM_DATA_WIDTH-1:0]   	m_axi_mem_``i``_wdata, \
-	output wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] 	m_axi_mem_``i``_wstrb, \
-	output wire                                 m_axi_mem_``i``_wlast, \
-	output wire                                 m_axi_mem_``i``_arvalid, \
-	input  wire                                 m_axi_mem_``i``_arready, \
-	output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0]   	m_axi_mem_``i``_araddr, \
-	output wire [C_M_AXI_MEM_ID_WIDTH-1:0]     	m_axi_mem_``i``_arid, \
-	output wire [7:0]                           m_axi_mem_``i``_arlen, \
-	input  wire                                 m_axi_mem_``i``_rvalid, \
-	output wire                                 m_axi_mem_``i``_rready, \
-	input  wire [C_M_AXI_MEM_DATA_WIDTH-1:0] 	m_axi_mem_``i``_rdata, \
-	input  wire                                 m_axi_mem_``i``_rlast, \
-	input  wire [C_M_AXI_MEM_ID_WIDTH-1:0]   	m_axi_mem_``i``_rid, \
-	input  wire [1:0]                           m_axi_mem_``i``_rresp, \
-	input  wire                                 m_axi_mem_``i``_bvalid, \
-	output wire                                 m_axi_mem_``i``_bready, \
-	input  wire [1:0]                           m_axi_mem_``i``_bresp, \
-	input  wire [C_M_AXI_MEM_ID_WIDTH-1:0]   	m_axi_mem_``i``_bid
-
-`define AXI_MEM_ARGS(i) \
-    .m_axi_mem_``i``_awvalid(m_axi_mem_``i``_awvalid), \
-    .m_axi_mem_``i``_awready(m_axi_mem_``i``_awready), \
-    .m_axi_mem_``i``_awaddr(m_axi_mem_``i``_awaddr), \
-    .m_axi_mem_``i``_awid(m_axi_mem_``i``_awid), \
-    .m_axi_mem_``i``_awlen(m_axi_mem_``i``_awlen), \
-    .m_axi_mem_``i``_wvalid(m_axi_mem_``i``_wvalid), \
-    .m_axi_mem_``i``_wready(m_axi_mem_``i``_wready), \
-    .m_axi_mem_``i``_wdata(m_axi_mem_``i``_wdata), \
-    .m_axi_mem_``i``_wstrb(m_axi_mem_``i``_wstrb), \
-    .m_axi_mem_``i``_wlast(m_axi_mem_``i``_wlast), \
-    .m_axi_mem_``i``_arvalid(m_axi_mem_``i``_arvalid), \
-    .m_axi_mem_``i``_arready(m_axi_mem_``i``_arready), \
-    .m_axi_mem_``i``_araddr(m_axi_mem_``i``_araddr), \
-    .m_axi_mem_``i``_arid(m_axi_mem_``i``_arid), \
-    .m_axi_mem_``i``_arlen(m_axi_mem_``i``_arlen), \
-    .m_axi_mem_``i``_rvalid(m_axi_mem_``i``_rvalid), \
-    .m_axi_mem_``i``_rready(m_axi_mem_``i``_rready), \
-    .m_axi_mem_``i``_rdata(m_axi_mem_``i``_rdata), \
-    .m_axi_mem_``i``_rlast(m_axi_mem_``i``_rlast), \
-    .m_axi_mem_``i``_rid(m_axi_mem_``i``_rid), \
-    .m_axi_mem_``i``_rresp(m_axi_mem_``i``_rresp), \
-    .m_axi_mem_``i``_bvalid(m_axi_mem_``i``_bvalid), \
-    .m_axi_mem_``i``_bready(m_axi_mem_``i``_bready), \
-    .m_axi_mem_``i``_bresp(m_axi_mem_``i``_bresp), \
-    .m_axi_mem_``i``_bid(m_axi_mem_``i``_bid)
-
-`define AXI_MEM_TO_ARRAY(i) \
-	assign m_axi_mem_``i``_awvalid = m_axi_mem_awvalid_a[i]; \
-	assign m_axi_mem_awready_a[i] = m_axi_mem_``i``_awready; \
-	assign m_axi_mem_``i``_awaddr = m_axi_mem_awaddr_a[i]; \
-	assign m_axi_mem_``i``_awid = m_axi_mem_awid_a[i]; \
-	assign m_axi_mem_``i``_awlen = m_axi_mem_awlen_a[i]; \
-	assign m_axi_mem_``i``_wvalid = m_axi_mem_wvalid_a[i]; \
-	assign m_axi_mem_wready_a[i] = m_axi_mem_``i``_wready; \
-	assign m_axi_mem_``i``_wdata = m_axi_mem_wdata_a[i]; \
-	assign m_axi_mem_``i``_wstrb = m_axi_mem_wstrb_a[i]; \
-	assign m_axi_mem_``i``_wlast = m_axi_mem_wlast_a[i]; \
-	assign m_axi_mem_``i``_arvalid = m_axi_mem_arvalid_a[i]; \
-	assign m_axi_mem_arready_a[i] = m_axi_mem_``i``_arready; \
-	assign m_axi_mem_``i``_araddr = m_axi_mem_araddr_a[i]; \
-	assign m_axi_mem_``i``_arid = m_axi_mem_arid_a[i]; \
-	assign m_axi_mem_``i``_arlen = m_axi_mem_arlen_a[i]; \
-	assign m_axi_mem_rvalid_a[i] = m_axi_mem_``i``_rvalid; \
-	assign m_axi_mem_``i``_rready = m_axi_mem_rready_a[i]; \
-	assign m_axi_mem_rdata_a[i] = m_axi_mem_``i``_rdata; \
-	assign m_axi_mem_rlast_a[i] = m_axi_mem_``i``_rlast; \
-	assign m_axi_mem_rid_a[i] = m_axi_mem_``i``_rid; \
-	assign m_axi_mem_rresp_a[i] = m_axi_mem_``i``_rresp; \
-	assign m_axi_mem_bvalid_a[i] = m_axi_mem_``i``_bvalid; \
-	assign m_axi_mem_``i``_bready = m_axi_mem_bready_a[i]; \
-	assign m_axi_mem_bresp_a[i] = m_axi_mem_``i``_bresp; \
-	assign m_axi_mem_bid_a[i] = m_axi_mem_``i``_bid
-
-`include "VX_define.vh"
-
-`endif // VORTEX_AFU_VH

hw/rtl/cache/VX_cache.sv

@@ -1,598 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache import VX_gpu_pkg::*; #(
-    parameter `STRING INSTANCE_ID    = "",
-
-    // Number of Word requests per cycle
-    parameter NUM_REQS              = 4,
-
-    // Size of cache in bytes
-    parameter CACHE_SIZE            = 4096, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE             = 64, 
-    // Number of banks
-    parameter NUM_BANKS             = 1,
-    // Number of associative ways
-    parameter NUM_WAYS              = 1,
-    // Size of a word in bytes
-    parameter WORD_SIZE             = `XLEN/8,
-
-    // Core Response Queue Size
-    parameter CRSQ_SIZE             = 2,
-    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE             = 8, 
-    // Memory Response Queue Size
-    parameter MRSQ_SIZE             = 0,
-    // Memory Request Queue Size
-    parameter MREQ_SIZE             = 4,
-
-    // Enable cache writeable
-    parameter WRITE_ENABLE          = 1,
-
-    // Request debug identifier
-    parameter UUID_WIDTH            = 0,
-
-    // core request tag size
-    parameter TAG_WIDTH             = UUID_WIDTH + 1,
-
-    // Core response output register
-    parameter CORE_OUT_REG          = 0,
-
-    // Memory request output register
-    parameter MEM_OUT_REG           = 0
- ) (    
-    // PERF
-`ifdef PERF_ENABLE
-    output cache_perf_t     cache_perf,
-`endif
-    
-    input wire clk,
-    input wire reset,
-
-    VX_mem_bus_if.slave     core_bus_if [NUM_REQS],
-    VX_mem_bus_if.master    mem_bus_if
-);
-
-    `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter"))    
-    `STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter"))
-
-    localparam REQ_SEL_WIDTH   = `UP(`CS_REQ_SEL_BITS);
-    localparam WORD_SEL_WIDTH  = `UP(`CS_WORD_SEL_BITS);
-    localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE);
-    localparam MEM_TAG_WIDTH   = MSHR_ADDR_WIDTH + `CS_BANK_SEL_BITS;
-    localparam WORDS_PER_LINE  = LINE_SIZE / WORD_SIZE;
-    localparam WORD_WIDTH      = WORD_SIZE * 8;
-    localparam WORD_SEL_BITS   = `CLOG2(WORDS_PER_LINE);
-    localparam BANK_SEL_BITS   = `CLOG2(NUM_BANKS);
-    localparam BANK_SEL_WIDTH  = `UP(BANK_SEL_BITS);
-    localparam LINE_ADDR_WIDTH = (`CS_WORD_ADDR_WIDTH - BANK_SEL_BITS - WORD_SEL_BITS);
-    localparam CORE_REQ_DATAW  = LINE_ADDR_WIDTH + 1 + WORD_SEL_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH;
-    localparam CORE_RSP_DATAW  = WORD_WIDTH + TAG_WIDTH;
-
-    localparam CORE_REQ_BUF_ENABLE = (NUM_BANKS != 1) || (NUM_REQS != 1);
-    localparam MEM_REQ_BUF_ENABLE  = (NUM_BANKS != 1);
-
-`ifdef PERF_ENABLE
-    wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
-    wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
-    wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
-`endif
-
-    wire [NUM_REQS-1:0]                     core_req_valid;
-    wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr;
-    wire [NUM_REQS-1:0]                     core_req_rw;    
-    wire [NUM_REQS-1:0][WORD_SIZE-1:0]      core_req_byteen;
-    wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data;
-    wire [NUM_REQS-1:0][TAG_WIDTH-1:0]      core_req_tag;
-    wire [NUM_REQS-1:0]                     core_req_ready;
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_req_valid[i]  = core_bus_if[i].req_valid;
-        assign core_req_addr[i]   = core_bus_if[i].req_data.addr;
-        assign core_req_rw[i]     = core_bus_if[i].req_data.rw;
-        assign core_req_byteen[i] = core_bus_if[i].req_data.byteen;
-        assign core_req_data[i]   = core_bus_if[i].req_data.data;
-        assign core_req_tag[i]    = core_bus_if[i].req_data.tag;
-        assign core_bus_if[i].req_ready = core_req_ready[i];
-    end
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    // Core response buffering
-    wire [NUM_REQS-1:0]                  core_rsp_valid_s;
-    wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s;
-    wire [NUM_REQS-1:0][TAG_WIDTH-1:0]   core_rsp_tag_s;
-    wire [NUM_REQS-1:0]                  core_rsp_ready_s;
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-
-        `RESET_RELAY (core_rsp_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (`CS_WORD_WIDTH + TAG_WIDTH),
-            .SIZE    (CORE_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0),
-            .OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
-        ) core_rsp_buf (
-            .clk       (clk),
-            .reset     (core_rsp_reset),
-            .valid_in  (core_rsp_valid_s[i]),
-            .ready_in  (core_rsp_ready_s[i]),
-            .data_in   ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
-            .data_out  ({core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag}), 
-            .valid_out (core_bus_if[i].rsp_valid),
-            .ready_out (core_bus_if[i].rsp_ready)
-        );
-    end
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    // Memory request buffering
-    wire                             mem_req_valid_s;
-    wire [`CS_MEM_ADDR_WIDTH-1:0]    mem_req_addr_s;
-    wire                             mem_req_rw_s;
-    wire [LINE_SIZE-1:0]             mem_req_byteen_s;
-    wire [`CS_LINE_WIDTH-1:0]        mem_req_data_s;
-    wire [MEM_TAG_WIDTH-1:0]         mem_req_tag_s;
-    wire                             mem_req_ready_s;
-
-    `RESET_RELAY (mem_req_buf_reset, reset);
-
-    VX_elastic_buffer #(
-        .DATAW   (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH),
-        .SIZE    (MEM_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0),
-        .OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
-    ) mem_req_buf (
-        .clk       (clk),
-        .reset     (mem_req_buf_reset),
-        .valid_in  (mem_req_valid_s), 
-        .ready_in  (mem_req_ready_s), 
-        .data_in   ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
-        .data_out  ({mem_bus_if.req_data.rw, mem_bus_if.req_data.byteen, mem_bus_if.req_data.addr, mem_bus_if.req_data.data, mem_bus_if.req_data.tag}), 
-        .valid_out (mem_bus_if.req_valid), 
-        .ready_out (mem_bus_if.req_ready)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    // Memory response buffering
-    wire                         mem_rsp_valid_s;
-    wire [`CS_LINE_WIDTH-1:0]    mem_rsp_data_s;
-    wire [MEM_TAG_WIDTH-1:0]     mem_rsp_tag_s;
-    wire                         mem_rsp_ready_s;
-
-    `RESET_RELAY (mem_rsp_reset, reset);
-        
-    VX_elastic_buffer #(
-        .DATAW   (MEM_TAG_WIDTH + `CS_LINE_WIDTH), 
-        .SIZE    (MRSQ_SIZE),
-        .OUT_REG (MRSQ_SIZE > 2)
-    ) mem_rsp_queue (
-        .clk        (clk),
-        .reset      (mem_rsp_reset),
-        .valid_in   (mem_bus_if.rsp_valid),
-        .ready_in   (mem_bus_if.rsp_ready),
-        .data_in    ({mem_bus_if.rsp_data.tag, mem_bus_if.rsp_data.data}), 
-        .data_out   ({mem_rsp_tag_s, mem_rsp_data_s}), 
-        .valid_out  (mem_rsp_valid_s),
-        .ready_out  (mem_rsp_ready_s)
-    );
-
-    ///////////////////////////////////////////////////////////////////////
-
-    wire [`CS_LINE_SEL_BITS-1:0] init_line_sel;
-    wire init_enable;
-
-    `RESET_RELAY (init_reset, reset);
-
-    VX_cache_init #( 
-        .CACHE_SIZE (CACHE_SIZE),
-        .LINE_SIZE  (LINE_SIZE), 
-        .NUM_BANKS  (NUM_BANKS),
-        .NUM_WAYS   (NUM_WAYS)
-    ) cache_init (
-        .clk       (clk),
-        .reset     (init_reset),
-        .addr_out  (init_line_sel),
-        .valid_out (init_enable)
-    );
-
-    ///////////////////////////////////////////////////////////////////////
-    
-    wire [NUM_BANKS-1:0]                        per_bank_core_req_valid;
-    wire [NUM_BANKS-1:0][`CS_LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr;
-    wire [NUM_BANKS-1:0]                        per_bank_core_req_rw;
-    wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0]    per_bank_core_req_wsel;
-    wire [NUM_BANKS-1:0][WORD_SIZE-1:0]         per_bank_core_req_byteen;
-    wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0]    per_bank_core_req_data;
-    wire [NUM_BANKS-1:0][TAG_WIDTH-1:0]         per_bank_core_req_tag;
-    wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0]     per_bank_core_req_idx;
-    wire [NUM_BANKS-1:0]                        per_bank_core_req_ready;
-    
-    wire [NUM_BANKS-1:0]                        per_bank_core_rsp_valid;
-    wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0]    per_bank_core_rsp_data;
-    wire [NUM_BANKS-1:0][TAG_WIDTH-1:0]         per_bank_core_rsp_tag;
-    wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0]     per_bank_core_rsp_idx;
-    wire [NUM_BANKS-1:0]                        per_bank_core_rsp_ready;
-
-    wire [NUM_BANKS-1:0]                        per_bank_mem_req_valid;    
-    wire [NUM_BANKS-1:0][`CS_MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr;
-    wire [NUM_BANKS-1:0]                        per_bank_mem_req_rw;
-    wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0]    per_bank_mem_req_wsel;
-    wire [NUM_BANKS-1:0][WORD_SIZE-1:0]         per_bank_mem_req_byteen;
-    wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0]    per_bank_mem_req_data;
-    wire [NUM_BANKS-1:0][MSHR_ADDR_WIDTH-1:0]   per_bank_mem_req_id;
-    wire [NUM_BANKS-1:0]                        per_bank_mem_req_ready;
-
-    wire [NUM_BANKS-1:0]                        per_bank_mem_rsp_ready;
-    
-    if (NUM_BANKS == 1) begin
-        assign mem_rsp_ready_s = per_bank_mem_rsp_ready;
-    end else begin
-        assign mem_rsp_ready_s = per_bank_mem_rsp_ready[`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s)];
-    end
-
-    // Bank requests dispatch
-
-    wire [NUM_REQS-1:0][CORE_REQ_DATAW-1:0]  core_req_data_in;    
-    wire [NUM_BANKS-1:0][CORE_REQ_DATAW-1:0] core_req_data_out;
-    wire [NUM_REQS-1:0][LINE_ADDR_WIDTH-1:0] core_req_line_addr;
-    wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0]  core_req_bid;
-    wire [NUM_REQS-1:0][WORD_SEL_WIDTH-1:0]  core_req_wsel;
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        if (WORDS_PER_LINE > 1) begin
-            assign core_req_wsel[i] = core_req_addr[i][0 +: WORD_SEL_BITS];
-        end else begin
-            assign core_req_wsel[i] = '0;
-        end
-        assign core_req_line_addr[i] = core_req_addr[i][(BANK_SEL_BITS + WORD_SEL_BITS) +: LINE_ADDR_WIDTH];
-    end
-
-    if (NUM_BANKS > 1) begin
-        for (genvar i = 0; i < NUM_REQS; ++i) begin
-            assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS];
-        end
-    end else begin
-        assign core_req_bid = '0;
-    end
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_req_data_in[i] = {
-            core_req_line_addr[i],
-            core_req_rw[i],
-            core_req_wsel[i],
-            core_req_byteen[i],            
-            core_req_data[i],
-            core_req_tag[i]};
-    end
-
-`ifdef PERF_ENABLE
-    wire [`PERF_CTR_BITS-1:0] perf_collisions;
-`endif
-
-    `RESET_RELAY (req_xbar_reset, reset);
-
-     VX_stream_xbar #(
-        .NUM_INPUTS  (NUM_REQS),
-        .NUM_OUTPUTS (NUM_BANKS),
-        .DATAW       (CORE_REQ_DATAW),
-        .PERF_CTR_BITS (`PERF_CTR_BITS)
-    ) req_xbar (
-        .clk       (clk),
-        .reset     (req_xbar_reset),
-    `ifdef PERF_ENABLE
-        .collisions(perf_collisions),
-    `else
-        `UNUSED_PIN(collisions),
-    `endif
-        .valid_in  (core_req_valid),
-        .data_in   (core_req_data_in),
-        .sel_in    (core_req_bid),
-        .ready_in  (core_req_ready),
-        .valid_out (per_bank_core_req_valid),
-        .data_out  (core_req_data_out),
-        .sel_out   (per_bank_core_req_idx),
-        .ready_out (per_bank_core_req_ready)
-    );
-
-    for (genvar i = 0; i < NUM_BANKS; ++i) begin
-        assign {
-            per_bank_core_req_addr[i],
-            per_bank_core_req_rw[i],
-            per_bank_core_req_wsel[i],
-            per_bank_core_req_byteen[i],            
-            per_bank_core_req_data[i],
-            per_bank_core_req_tag[i]} = core_req_data_out[i];
-    end
-    
-    // Banks access
-    for (genvar i = 0; i < NUM_BANKS; ++i) begin
-        wire [`CS_LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr;
-        wire curr_bank_mem_rsp_valid;
-
-        if (NUM_BANKS == 1) begin
-            assign curr_bank_mem_rsp_valid = mem_rsp_valid_s;
-        end else begin
-            assign curr_bank_mem_rsp_valid = mem_rsp_valid_s && (`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s) == i);
-        end
-
-        `RESET_RELAY (bank_reset, reset);
-        
-        VX_cache_bank #(                
-            .BANK_ID      (i),
-            .INSTANCE_ID  (INSTANCE_ID),
-            .CACHE_SIZE   (CACHE_SIZE),
-            .LINE_SIZE    (LINE_SIZE),
-            .NUM_BANKS    (NUM_BANKS),
-            .NUM_WAYS     (NUM_WAYS),
-            .WORD_SIZE    (WORD_SIZE),
-            .NUM_REQS     (NUM_REQS),
-            .CRSQ_SIZE    (CRSQ_SIZE),
-            .MSHR_SIZE    (MSHR_SIZE),
-            .MREQ_SIZE    (MREQ_SIZE),
-            .WRITE_ENABLE (WRITE_ENABLE),
-            .UUID_WIDTH   (UUID_WIDTH),
-            .TAG_WIDTH    (TAG_WIDTH),
-            .CORE_OUT_REG (CORE_REQ_BUF_ENABLE ? 0 : CORE_OUT_REG),
-            .MEM_OUT_REG  (MEM_REQ_BUF_ENABLE ? 0 : MEM_OUT_REG)
-        ) bank (          
-            .clk                (clk),
-            .reset              (bank_reset),
-
-        `ifdef PERF_ENABLE
-            .perf_read_misses   (perf_read_miss_per_bank[i]),
-            .perf_write_misses  (perf_write_miss_per_bank[i]),
-            .perf_mshr_stalls   (perf_mshr_stall_per_bank[i]),
-        `endif
-                    
-            // Core request
-            .core_req_valid     (per_bank_core_req_valid[i]),
-            .core_req_addr      (per_bank_core_req_addr[i]),
-            .core_req_rw        (per_bank_core_req_rw[i]),
-            .core_req_wsel      (per_bank_core_req_wsel[i]),
-            .core_req_byteen    (per_bank_core_req_byteen[i]),
-            .core_req_data      (per_bank_core_req_data[i]),
-            .core_req_tag       (per_bank_core_req_tag[i]),
-            .core_req_idx       (per_bank_core_req_idx[i]),
-            .core_req_ready     (per_bank_core_req_ready[i]),
-
-            // Core response                
-            .core_rsp_valid     (per_bank_core_rsp_valid[i]),
-            .core_rsp_data      (per_bank_core_rsp_data[i]),
-            .core_rsp_tag       (per_bank_core_rsp_tag[i]),
-            .core_rsp_idx       (per_bank_core_rsp_idx[i]),
-            .core_rsp_ready     (per_bank_core_rsp_ready[i]),
-
-            // Memory request
-            .mem_req_valid      (per_bank_mem_req_valid[i]),
-            .mem_req_addr       (curr_bank_mem_req_addr),
-            .mem_req_rw         (per_bank_mem_req_rw[i]),
-            .mem_req_wsel       (per_bank_mem_req_wsel[i]),
-            .mem_req_byteen     (per_bank_mem_req_byteen[i]),
-            .mem_req_data       (per_bank_mem_req_data[i]),
-            .mem_req_id         (per_bank_mem_req_id[i]),
-            .mem_req_ready      (per_bank_mem_req_ready[i]),
-
-            // Memory response
-            .mem_rsp_valid      (curr_bank_mem_rsp_valid),
-            .mem_rsp_data       (mem_rsp_data_s),
-            .mem_rsp_id         (`CS_MEM_TAG_TO_REQ_ID(mem_rsp_tag_s)),
-            .mem_rsp_ready      (per_bank_mem_rsp_ready[i]),
-
-            // initialization    
-            .init_enable        (init_enable),
-            .init_line_sel      (init_line_sel)
-        );
-
-        if (NUM_BANKS == 1) begin
-            assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr;
-        end else begin
-            assign per_bank_mem_req_addr[i] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i);
-        end
-    end   
-
-    // Bank responses gather
-
-    wire [NUM_BANKS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_in;
-    wire [NUM_REQS-1:0][CORE_RSP_DATAW-1:0]  core_rsp_data_out;
-
-    for (genvar i = 0; i < NUM_BANKS; ++i) begin
-        assign core_rsp_data_in[i] = {per_bank_core_rsp_data[i], per_bank_core_rsp_tag[i]};
-    end
-
-    `RESET_RELAY (rsp_xbar_reset, reset);
-
-    VX_stream_xbar #(
-        .NUM_INPUTS  (NUM_BANKS),
-        .NUM_OUTPUTS (NUM_REQS),
-        .DATAW       (CORE_RSP_DATAW)
-    ) rsp_xbar (
-        .clk       (clk),
-        .reset     (rsp_xbar_reset),
-        `UNUSED_PIN (collisions),
-        .valid_in  (per_bank_core_rsp_valid),
-        .data_in   (core_rsp_data_in),
-        .sel_in    (per_bank_core_rsp_idx),
-        .ready_in  (per_bank_core_rsp_ready),
-        .valid_out (core_rsp_valid_s),
-        .data_out  (core_rsp_data_out),
-        .ready_out (core_rsp_ready_s),
-        `UNUSED_PIN (sel_out)
-    );
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign {core_rsp_data_s[i], core_rsp_tag_s[i]} = core_rsp_data_out[i];
-    end
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    wire                        mem_req_valid_p;
-    wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_p;
-    wire                        mem_req_rw_p;
-    wire [WORD_SEL_WIDTH-1:0]   mem_req_wsel_p;
-    wire [WORD_SIZE-1:0]        mem_req_byteen_p;
-    wire [`CS_WORD_WIDTH-1:0]   mem_req_data_p;
-    wire [MEM_TAG_WIDTH-1:0]    mem_req_tag_p;
-    wire [MSHR_ADDR_WIDTH-1:0]  mem_req_id_p;
-    wire                        mem_req_ready_p;
-
-    // Memory request arbitration
-
-    wire [NUM_BANKS-1:0][(`CS_MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH)-1:0] data_in;
-
-    for (genvar i = 0; i < NUM_BANKS; ++i) begin
-        assign data_in[i] = {per_bank_mem_req_addr[i],
-                             per_bank_mem_req_rw[i],
-                             per_bank_mem_req_wsel[i], 
-                             per_bank_mem_req_byteen[i],                              
-                             per_bank_mem_req_data[i],
-                             per_bank_mem_req_id[i]};
-    end
-
-    `RESET_RELAY (mem_req_arb_reset, reset);
-
-    VX_stream_arb #(
-        .NUM_INPUTS (NUM_BANKS),
-        .DATAW      (`CS_MEM_ADDR_WIDTH + 1  + WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + MSHR_ADDR_WIDTH),
-        .ARBITER    ("R")
-    ) mem_req_arb (
-        .clk       (clk),
-        .reset     (mem_req_arb_reset),
-        .valid_in  (per_bank_mem_req_valid),
-        .ready_in  (per_bank_mem_req_ready),
-        .data_in   (data_in),
-        .data_out  ({mem_req_addr_p, mem_req_rw_p, mem_req_wsel_p, mem_req_byteen_p, mem_req_data_p, mem_req_id_p}),
-        .valid_out (mem_req_valid_p),
-        .ready_out (mem_req_ready_p),
-        `UNUSED_PIN (sel_out)
-    );
-
-    if (NUM_BANKS > 1) begin
-        wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id = `CS_MEM_ADDR_TO_BANK_ID(mem_req_addr_p);
-        assign mem_req_tag_p = MEM_TAG_WIDTH'({mem_req_bank_id, mem_req_id_p});            
-    end else begin
-        assign mem_req_tag_p = MEM_TAG_WIDTH'(mem_req_id_p);
-    end   
-
-    // Memory request multi-port handling
-
-    assign mem_req_valid_s = mem_req_valid_p;
-    assign mem_req_addr_s  = mem_req_addr_p;
-    assign mem_req_tag_s   = mem_req_tag_p;
-    assign mem_req_ready_p = mem_req_ready_s;
-
-    if (WRITE_ENABLE != 0) begin
-        if (`CS_WORDS_PER_LINE > 1) begin
-            reg [LINE_SIZE-1:0]      mem_req_byteen_r;
-            reg [`CS_LINE_WIDTH-1:0] mem_req_data_r;
-
-            always @(*) begin
-                mem_req_byteen_r = '0;
-                mem_req_data_r   = 'x;
-                mem_req_byteen_r[mem_req_wsel_p * WORD_SIZE +: WORD_SIZE] = mem_req_byteen_p;
-                mem_req_data_r[mem_req_wsel_p * `CS_WORD_WIDTH +: `CS_WORD_WIDTH] = mem_req_data_p;
-            end            
-            assign mem_req_rw_s     = mem_req_rw_p;
-            assign mem_req_byteen_s = mem_req_byteen_r;
-            assign mem_req_data_s   = mem_req_data_r;
-        end else begin
-            `UNUSED_VAR (mem_req_wsel_p)
-            assign mem_req_rw_s     = mem_req_rw_p;
-            assign mem_req_byteen_s = mem_req_byteen_p;            
-            assign mem_req_data_s   = mem_req_data_p;            
-        end
-    end else begin
-        `UNUSED_VAR (mem_req_byteen_p)
-        `UNUSED_VAR (mem_req_wsel_p)
-        `UNUSED_VAR (mem_req_data_p)
-        `UNUSED_VAR (mem_req_rw_p)
-        
-        assign mem_req_rw_s     = 0;
-        assign mem_req_byteen_s = {LINE_SIZE{1'b1}};
-        assign mem_req_data_s   = '0;
-    end
-
-`ifdef PERF_ENABLE
-    // per cycle: core_reads, core_writes
-    wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle;
-    wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle;
-    
-    wire [NUM_REQS-1:0] perf_core_reads_per_req;
-    wire [NUM_REQS-1:0] perf_core_writes_per_req;
-        
-    // per cycle: read misses, write misses, msrq stalls, pipeline stalls
-    wire [`CLOG2(NUM_BANKS+1)-1:0] perf_read_miss_per_cycle;
-    wire [`CLOG2(NUM_BANKS+1)-1:0] perf_write_miss_per_cycle;
-    wire [`CLOG2(NUM_BANKS+1)-1:0] perf_mshr_stall_per_cycle;
-    wire [`CLOG2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle;
-
-    `BUFFER(perf_core_reads_per_req, core_req_valid & core_req_ready & ~core_req_rw);
-    `BUFFER(perf_core_writes_per_req, core_req_valid & core_req_ready & core_req_rw);
-    
-    `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_req);
-    `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_req);
-    `POP_COUNT(perf_read_miss_per_cycle, perf_read_miss_per_bank);
-    `POP_COUNT(perf_write_miss_per_cycle, perf_write_miss_per_bank);
-    `POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank);
-    
-    wire [NUM_REQS-1:0] perf_crsp_stall_per_req;
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign perf_crsp_stall_per_req[i] = core_bus_if[i].rsp_valid && ~core_bus_if[i].rsp_ready;
-    end
-
-    `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req);
-
-    wire perf_mem_stall_per_cycle = mem_bus_if.req_valid && ~mem_bus_if.req_ready;
-
-    reg [`PERF_CTR_BITS-1:0] perf_core_reads;
-    reg [`PERF_CTR_BITS-1:0] perf_core_writes;
-    reg [`PERF_CTR_BITS-1:0] perf_read_misses;
-    reg [`PERF_CTR_BITS-1:0] perf_write_misses;
-    reg [`PERF_CTR_BITS-1:0] perf_mshr_stalls;
-    reg [`PERF_CTR_BITS-1:0] perf_mem_stalls;
-    reg [`PERF_CTR_BITS-1:0] perf_crsp_stalls;    
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_core_reads   <= '0;
-            perf_core_writes  <= '0;
-            perf_read_misses  <= '0;
-            perf_write_misses <= '0;
-            perf_mshr_stalls  <= '0;
-            perf_mem_stalls   <= '0;
-            perf_crsp_stalls  <= '0;
-        end else begin
-            perf_core_reads   <= perf_core_reads   + `PERF_CTR_BITS'(perf_core_reads_per_cycle);
-            perf_core_writes  <= perf_core_writes  + `PERF_CTR_BITS'(perf_core_writes_per_cycle);
-            perf_read_misses  <= perf_read_misses  + `PERF_CTR_BITS'(perf_read_miss_per_cycle);
-            perf_write_misses <= perf_write_misses + `PERF_CTR_BITS'(perf_write_miss_per_cycle);
-            perf_mshr_stalls  <= perf_mshr_stalls  + `PERF_CTR_BITS'(perf_mshr_stall_per_cycle);
-            perf_mem_stalls   <= perf_mem_stalls   + `PERF_CTR_BITS'(perf_mem_stall_per_cycle);
-            perf_crsp_stalls  <= perf_crsp_stalls  + `PERF_CTR_BITS'(perf_crsp_stall_per_cycle);
-        end
-    end
-
-    assign cache_perf.reads        = perf_core_reads;
-    assign cache_perf.writes       = perf_core_writes;
-    assign cache_perf.read_misses  = perf_read_misses;
-    assign cache_perf.write_misses = perf_write_misses;
-    assign cache_perf.bank_stalls  = perf_collisions;
-    assign cache_perf.mshr_stalls  = perf_mshr_stalls;
-    assign cache_perf.mem_stalls   = perf_mem_stalls;
-    assign cache_perf.crsp_stalls  = perf_crsp_stalls;
-`endif
-
-endmodule

hw/rtl/cache/VX_cache_bank.sv

@@ -1,549 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_bank #(
-    parameter `STRING INSTANCE_ID= "",
-    parameter BANK_ID           = 0,
-
-    // Number of Word requests per cycle
-    parameter NUM_REQS          = 1, 
-
-    // Size of cache in bytes
-    parameter CACHE_SIZE        = 1024, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE         = 16, 
-    // Number of banks
-    parameter NUM_BANKS         = 1,
-    // Number of associative ways 
-    parameter NUM_WAYS          = 1, 
-    // Size of a word in bytes
-    parameter WORD_SIZE         = 4, 
-
-    // Core Response Queue Size
-    parameter CRSQ_SIZE         = 1,
-    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE         = 1, 
-    // Memory Request Queue Size
-    parameter MREQ_SIZE         = 1,
-
-    // Enable cache writeable
-    parameter WRITE_ENABLE      = 1,
-
-    // Request debug identifier
-    parameter UUID_WIDTH        = 0,
-
-    // core request tag size
-    parameter TAG_WIDTH         = UUID_WIDTH + 1,
-
-    // Core response output register
-    parameter CORE_OUT_REG      = 0,
-
-    // Memory request output register
-    parameter MEM_OUT_REG       = 0,
-
-    parameter MSHR_ADDR_WIDTH   = `LOG2UP(MSHR_SIZE),
-    parameter REQ_SEL_WIDTH     = `UP(`CS_REQ_SEL_BITS),
-    parameter WORD_SEL_WIDTH    = `UP(`CS_WORD_SEL_BITS)
-) (
-    input wire clk,
-    input wire reset,
-
-`ifdef PERF_ENABLE
-    output wire perf_read_misses,
-    output wire perf_write_misses,
-    output wire perf_mshr_stalls,
-`endif
-
-    // Core Request    
-    input wire                          core_req_valid,
-    input wire [`CS_LINE_ADDR_WIDTH-1:0] core_req_addr,
-    input wire                          core_req_rw, 
-    input wire [WORD_SEL_WIDTH-1:0]     core_req_wsel,
-    input wire [WORD_SIZE-1:0]          core_req_byteen,
-    input wire [`CS_WORD_WIDTH-1:0]     core_req_data, 
-    input wire [TAG_WIDTH-1:0]          core_req_tag,
-    input wire [REQ_SEL_WIDTH-1:0]      core_req_idx,
-    output wire                         core_req_ready,
-    
-    // Core Response    
-    output wire                         core_rsp_valid,
-    output wire [`CS_WORD_WIDTH-1:0]    core_rsp_data,
-    output wire [TAG_WIDTH-1:0]         core_rsp_tag,
-    output wire [REQ_SEL_WIDTH-1:0]     core_rsp_idx,
-    input  wire                         core_rsp_ready,
-
-    // Memory request
-    output wire                         mem_req_valid,
-    output wire [`CS_LINE_ADDR_WIDTH-1:0] mem_req_addr,
-    output wire                         mem_req_rw,
-    output wire [WORD_SEL_WIDTH-1:0]    mem_req_wsel,  
-    output wire [WORD_SIZE-1:0]         mem_req_byteen,
-    output wire [`CS_WORD_WIDTH-1:0]    mem_req_data,
-    output wire [MSHR_ADDR_WIDTH-1:0]   mem_req_id,
-    input  wire                         mem_req_ready,
-    
-    // Memory response
-    input wire                          mem_rsp_valid,
-    input wire [`CS_LINE_WIDTH-1:0]     mem_rsp_data,
-    input wire [MSHR_ADDR_WIDTH-1:0]    mem_rsp_id,
-    output wire                         mem_rsp_ready,
-
-    // initialization
-    input wire                          init_enable,
-    input wire [`CS_LINE_SEL_BITS-1:0]  init_line_sel
-);
-
-`IGNORE_UNUSED_BEGIN
-    wire [`UP(UUID_WIDTH)-1:0] req_uuid_sel, req_uuid_st0, req_uuid_st1;
-`IGNORE_UNUSED_END
-
-    wire                            crsq_stall;
-    wire                            mshr_alm_full;
-    wire                            mreq_alm_full;
-    
-    wire [`CS_LINE_ADDR_WIDTH-1:0]  mem_rsp_addr;
-        
-    wire                            replay_valid;
-    wire [`CS_LINE_ADDR_WIDTH-1:0]  replay_addr;
-    wire                            replay_rw;
-    wire [WORD_SEL_WIDTH-1:0]       replay_wsel;
-    wire [WORD_SIZE-1:0]            replay_byteen;
-    wire [`CS_WORD_WIDTH-1:0]       replay_data;
-    wire [TAG_WIDTH-1:0]            replay_tag;
-    wire [REQ_SEL_WIDTH-1:0]        replay_idx;
-    wire [MSHR_ADDR_WIDTH-1:0]      replay_id;
-    wire                            replay_ready;
-    
-    wire [`CS_LINE_ADDR_WIDTH-1:0]  addr_sel, addr_st0, addr_st1;
-    wire                            rw_st0, rw_st1;
-    wire [WORD_SEL_WIDTH-1:0]       wsel_st0, wsel_st1;
-    wire [WORD_SIZE-1:0]            byteen_st0, byteen_st1;
-    wire [REQ_SEL_WIDTH-1:0]        req_idx_st0, req_idx_st1;
-    wire [TAG_WIDTH-1:0]            tag_st0, tag_st1;
-    wire [`CS_WORD_WIDTH-1:0]       read_data_st1;
-    wire [`CS_LINE_WIDTH-1:0]       data_sel, data_st0, data_st1;
-    wire [MSHR_ADDR_WIDTH-1:0]      replay_id_st0, mshr_id_st0, mshr_id_st1;
-    wire                            valid_sel, valid_st0, valid_st1;
-    wire                            is_init_st0;
-    wire                            is_creq_st0, is_creq_st1;
-    wire                            is_fill_st0, is_fill_st1;
-    wire                            is_replay_st0, is_replay_st1;
-    wire [MSHR_ADDR_WIDTH-1:0]      mshr_alloc_id_st0;
-    wire [MSHR_ADDR_WIDTH-1:0]      mshr_tail_st0, mshr_tail_st1;
-    wire                            mshr_pending_st0, mshr_pending_st1;
-
-    wire rdw_hazard_st0;
-    reg rdw_hazard_st1;
-
-    wire pipe_stall = crsq_stall || rdw_hazard_st1;
-
-    // inputs arbitration:
-    // mshr replay has highest priority to maximize utilization since there is no miss.
-    // handle memory responses next to prevent deadlock with potential memory request from a miss.
-    wire replay_grant = ~init_enable;
-    wire replay_enable = replay_grant && replay_valid; 
-
-    wire fill_grant  = ~init_enable && ~replay_enable;
-    wire fill_enable = fill_grant && mem_rsp_valid;
-
-    wire creq_grant  = ~init_enable && ~replay_enable && ~fill_enable;
-    wire creq_enable = creq_grant && core_req_valid;
-
-    assign replay_ready = replay_grant
-                         && ~rdw_hazard_st0
-                         && ~pipe_stall;
-
-    assign mem_rsp_ready = fill_grant
-                        && ~pipe_stall;
-    
-    assign core_req_ready = creq_grant
-                        && ~mreq_alm_full
-                        && ~mshr_alm_full
-                        && ~pipe_stall;
-
-    wire init_fire     = init_enable;
-    wire replay_fire = replay_valid && replay_ready;
-    wire mem_rsp_fire  = mem_rsp_valid && mem_rsp_ready;
-    wire core_req_fire = core_req_valid && core_req_ready;
-
-    wire [TAG_WIDTH-1:0] mshr_creq_tag = replay_enable ? replay_tag : core_req_tag;
-    
-    if (UUID_WIDTH != 0) begin
-        assign req_uuid_sel = mshr_creq_tag[TAG_WIDTH-1 -: UUID_WIDTH];
-    end else begin
-        assign req_uuid_sel = 0;
-    end
-
-    `UNUSED_VAR (mshr_creq_tag)
-
-    assign valid_sel = init_fire || replay_fire || mem_rsp_fire || core_req_fire;
-
-    assign addr_sel = init_enable ? `CS_LINE_ADDR_WIDTH'(init_line_sel) :
-                        (replay_valid ? replay_addr : 
-                            (mem_rsp_valid ? mem_rsp_addr : core_req_addr));
-
-    assign data_sel[`CS_WORD_WIDTH-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[`CS_WORD_WIDTH-1:0] : (replay_valid ? replay_data : core_req_data);
-    for (genvar i = `CS_WORD_WIDTH; i < `CS_LINE_WIDTH; ++i) begin
-        assign data_sel[i] = mem_rsp_data[i];
-    end
-
-    VX_pipe_register #(
-        .DATAW  (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH),
-        .RESETW (1)
-    ) pipe_reg0 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (~pipe_stall),
-        .data_in  ({
-            valid_sel,
-            init_enable,
-            replay_enable,
-            fill_enable,
-            creq_enable,
-            addr_sel,
-            data_sel,
-            replay_valid ? replay_rw : core_req_rw,
-            replay_valid ? replay_byteen : core_req_byteen,
-            replay_valid ? replay_wsel : core_req_wsel, 
-            replay_valid ? replay_idx : core_req_idx,
-            replay_valid ? replay_tag : core_req_tag,
-            replay_id
-        }),
-        .data_out ({valid_st0, is_init_st0, is_replay_st0, is_fill_st0, is_creq_st0, addr_st0, data_st0, rw_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, replay_id_st0})
-    );
-
-    if (UUID_WIDTH != 0) begin
-        assign req_uuid_st0 = tag_st0[TAG_WIDTH-1 -: UUID_WIDTH];
-    end else begin
-        assign req_uuid_st0 = 0;
-    end
-
-    wire do_creq_rd_st0 = valid_st0 && is_creq_st0 && ~rw_st0;
-    wire do_fill_st0    = valid_st0 && is_fill_st0;
-    wire do_init_st0    = valid_st0 && is_init_st0;
-    wire do_lookup_st0  = valid_st0 && ~(is_fill_st0 || is_init_st0);
-
-    wire [`CS_WORD_WIDTH-1:0] write_data_st0 = data_st0[`CS_WORD_WIDTH-1:0];
-
-    wire [NUM_WAYS-1:0] tag_matches_st0, tag_matches_st1;
-    wire [NUM_WAYS-1:0] way_sel_st0, way_sel_st1;
-
-    `RESET_RELAY (tag_reset, reset);
-
-    VX_cache_tags #(
-        .INSTANCE_ID(INSTANCE_ID),
-        .BANK_ID    (BANK_ID), 
-        .CACHE_SIZE (CACHE_SIZE),
-        .LINE_SIZE  (LINE_SIZE),
-        .NUM_BANKS  (NUM_BANKS),
-        .NUM_WAYS   (NUM_WAYS),
-        .WORD_SIZE  (WORD_SIZE), 
-        .UUID_WIDTH (UUID_WIDTH)
-    ) cache_tags (
-        .clk        (clk),
-        .reset      (tag_reset),
-
-        .req_uuid   (req_uuid_st0),
-        
-        .stall      (pipe_stall),
-
-        // read/Fill
-        .lookup     (do_lookup_st0),
-        .line_addr  (addr_st0),
-        .fill       (do_fill_st0),
-        .init       (do_init_st0),
-        .way_sel    (way_sel_st0),
-        .tag_matches(tag_matches_st0)
-    );
-
-    assign mshr_id_st0 = is_creq_st0 ? mshr_alloc_id_st0 : replay_id_st0;
-
-    VX_pipe_register #(
-        .DATAW  (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_WAYS + NUM_WAYS + 1),
-        .RESETW (1)
-    ) pipe_reg1 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (~pipe_stall),
-        .data_in  ({valid_st0, is_replay_st0, is_fill_st0, is_creq_st0, rw_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, mshr_id_st0, mshr_tail_st0, tag_matches_st0, way_sel_st0, mshr_pending_st0}),
-        .data_out ({valid_st1, is_replay_st1, is_fill_st1, is_creq_st1, rw_st1, addr_st1, data_st1, byteen_st1, wsel_st1, req_idx_st1, tag_st1, mshr_id_st1, mshr_tail_st1, tag_matches_st1, way_sel_st1, mshr_pending_st1})
-    );
-
-    // we have a tag hit
-    wire is_hit_st1 = (| tag_matches_st1);
-
-    if (UUID_WIDTH != 0) begin
-        assign req_uuid_st1 = tag_st1[TAG_WIDTH-1 -: UUID_WIDTH];
-    end else begin
-        assign req_uuid_st1 = 0;
-    end
-
-    wire do_creq_rd_st1   = valid_st1 && is_creq_st1 && ~rw_st1;
-    wire do_creq_wr_st1   = valid_st1 && is_creq_st1 && rw_st1;
-    wire do_fill_st1      = valid_st1 && is_fill_st1;
-    wire do_replay_rd_st1 = valid_st1 && is_replay_st1 && ~rw_st1;
-    wire do_replay_wr_st1 = valid_st1 && is_replay_st1 && rw_st1;
-
-    wire do_read_hit_st1  = do_creq_rd_st1 && is_hit_st1;
-    wire do_read_miss_st1 = do_creq_rd_st1 && ~is_hit_st1;
-
-    wire do_write_hit_st1 = do_creq_wr_st1 && is_hit_st1;
-    wire do_write_miss_st1= do_creq_wr_st1 && ~is_hit_st1;
-
-    `UNUSED_VAR (do_write_miss_st1)
-
-    // ensure mshr replay always get a hit
-    `RUNTIME_ASSERT (~(valid_st1 && is_replay_st1) || is_hit_st1, ("runtime error: invalid mshr replay"));
-
-    // detect BRAM's read-during-write hazard
-    assign rdw_hazard_st0 = do_fill_st0; // after a fill
-    always @(posedge clk) begin
-        rdw_hazard_st1 <= (do_creq_rd_st0 && do_write_hit_st1 && (addr_st0 == addr_st1))
-                       && ~rdw_hazard_st1; // after a write to same address
-    end
-
-    wire [`CS_WORD_WIDTH-1:0] write_data_st1 = data_st1[`CS_WORD_WIDTH-1:0];
-    wire [`CS_LINE_WIDTH-1:0] fill_data_st1 = data_st1;
-
-    `RESET_RELAY (data_reset, reset);
- 
-    VX_cache_data #(
-        .INSTANCE_ID  (INSTANCE_ID),
-        .BANK_ID      (BANK_ID), 
-        .CACHE_SIZE   (CACHE_SIZE),
-        .LINE_SIZE    (LINE_SIZE),
-        .NUM_BANKS    (NUM_BANKS),
-        .NUM_WAYS     (NUM_WAYS),
-        .WORD_SIZE    (WORD_SIZE),
-        .WRITE_ENABLE (WRITE_ENABLE),
-        .UUID_WIDTH   (UUID_WIDTH)
-    ) cache_data (
-        .clk        (clk),
-        .reset      (data_reset),
-
-        .req_uuid   (req_uuid_st1),
-
-        .stall      (pipe_stall),
-
-        .read       (do_read_hit_st1 || do_replay_rd_st1), 
-        .fill       (do_fill_st1), 
-        .write      (do_write_hit_st1 || do_replay_wr_st1),
-        .way_sel    (way_sel_st1 | tag_matches_st1),
-        .line_addr  (addr_st1),
-        .wsel       (wsel_st1),
-        .byteen     (byteen_st1),
-        .fill_data  (fill_data_st1), 
-        .write_data (write_data_st1),
-        .read_data  (read_data_st1)
-    );
-    
-    wire [MSHR_SIZE-1:0] mshr_matches_st0;
-    wire mshr_allocate_st0 = valid_st0 && is_creq_st0 && ~pipe_stall;
-    wire mshr_lookup_st0   = mshr_allocate_st0;
-    wire mshr_finalize_st1 = valid_st1 && is_creq_st1 && ~pipe_stall;
-    wire mshr_release_st1  = is_hit_st1 || (rw_st1 && ~mshr_pending_st1);
-
-    VX_pending_size #( 
-        .SIZE (MSHR_SIZE)
-    ) mshr_pending_size (
-        .clk   (clk),
-        .reset (reset),
-        .incr  (core_req_fire),
-        .decr  (replay_fire || (mshr_finalize_st1 && mshr_release_st1)),
-        .full  (mshr_alm_full),
-        `UNUSED_PIN (size),
-        `UNUSED_PIN (empty)
-    );
-
-    `RESET_RELAY (mshr_reset, reset);
-
-    VX_cache_mshr #(
-        .INSTANCE_ID (INSTANCE_ID),
-        .BANK_ID     (BANK_ID), 
-        .LINE_SIZE   (LINE_SIZE),
-        .NUM_BANKS   (NUM_BANKS),
-        .MSHR_SIZE   (MSHR_SIZE),
-        .UUID_WIDTH  (UUID_WIDTH),
-        .DATA_WIDTH  (WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + TAG_WIDTH + REQ_SEL_WIDTH)
-    ) cache_mshr (
-        .clk            (clk),
-        .reset          (mshr_reset),
-
-        .deq_req_uuid   (req_uuid_sel),
-        .lkp_req_uuid   (req_uuid_st0),
-        .fin_req_uuid   (req_uuid_st1),
-
-        // memory fill
-        .fill_valid     (mem_rsp_fire),
-        .fill_id        (mem_rsp_id),
-        .fill_addr      (mem_rsp_addr),
-
-        // dequeue
-        .dequeue_valid  (replay_valid),
-        .dequeue_addr   (replay_addr),
-        .dequeue_rw     (replay_rw),        
-        .dequeue_data   ({replay_wsel, replay_byteen, replay_data, replay_tag, replay_idx}),
-        .dequeue_id     (replay_id),
-        .dequeue_ready  (replay_ready),
-
-        // allocate
-        .allocate_valid (mshr_allocate_st0),
-        .allocate_addr  (addr_st0),
-        .allocate_rw    (rw_st0),
-        .allocate_data  ({wsel_st0, byteen_st0, write_data_st0, tag_st0, req_idx_st0}),
-        .allocate_id    (mshr_alloc_id_st0),
-        .allocate_tail  (mshr_tail_st0),
-        `UNUSED_PIN     (allocate_ready),
-
-        // lookup
-        .lookup_valid   (mshr_lookup_st0),
-        .lookup_addr    (addr_st0),
-        .lookup_matches (mshr_matches_st0),
-
-        // finalize
-        .finalize_valid (mshr_finalize_st1),
-        .finalize_release(mshr_release_st1),
-        .finalize_pending(mshr_pending_st1),
-        .finalize_id    (mshr_id_st1),
-        .finalize_tail  (mshr_tail_st1)
-    );
-
-    // ignore allocated id from mshr matches
-    wire [MSHR_SIZE-1:0] lookup_matches;
-    for (genvar i = 0; i < MSHR_SIZE; ++i) begin
-        assign lookup_matches[i] = (i != mshr_alloc_id_st0) && mshr_matches_st0[i];
-    end
-    assign mshr_pending_st0 = (| lookup_matches);
-
-    // schedule core response
-    
-    wire crsq_valid, crsq_ready;
-    wire [`CS_WORD_WIDTH-1:0] crsq_data;
-    wire [REQ_SEL_WIDTH-1:0] crsq_idx;
-    wire [TAG_WIDTH-1:0] crsq_tag;
-
-    assign crsq_valid = do_read_hit_st1 || do_replay_rd_st1;
-    assign crsq_idx   = req_idx_st1;
-    assign crsq_data  = read_data_st1;
-    assign crsq_tag   = tag_st1;
-
-    `RESET_RELAY (crsp_reset, reset);
-
-    VX_elastic_buffer #(
-        .DATAW   (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH),
-        .SIZE    (CRSQ_SIZE),
-        .OUT_REG (CORE_OUT_REG)
-    ) core_rsp_queue (
-        .clk       (clk),
-        .reset     (crsp_reset),
-        .valid_in  (crsq_valid && ~rdw_hazard_st1),
-        .ready_in  (crsq_ready),
-        .data_in   ({crsq_tag, crsq_data, crsq_idx}), 
-        .data_out  ({core_rsp_tag, core_rsp_data, core_rsp_idx}),
-        .valid_out (core_rsp_valid),
-        .ready_out (core_rsp_ready)
-    );
-
-    assign crsq_stall = crsq_valid && ~crsq_ready;
-
-    // schedule memory request
-
-    wire mreq_push, mreq_pop, mreq_empty;
-    wire [`CS_WORD_WIDTH-1:0] mreq_data;
-    wire [WORD_SIZE-1:0] mreq_byteen;
-    wire [WORD_SEL_WIDTH-1:0] mreq_wsel;
-    wire [`CS_LINE_ADDR_WIDTH-1:0] mreq_addr;
-    wire [MSHR_ADDR_WIDTH-1:0] mreq_id;
-    wire mreq_rw;
-
-    assign mreq_push = (do_read_miss_st1 && ~mshr_pending_st1)
-                     || do_creq_wr_st1;
-
-    assign mreq_pop = mem_req_valid && mem_req_ready;
-
-    assign mreq_rw   = WRITE_ENABLE && rw_st1;
-    assign mreq_addr = addr_st1;
-    assign mreq_id   = mshr_id_st1;
-    assign mreq_wsel = wsel_st1;
-    assign mreq_byteen = byteen_st1;
-    assign mreq_data = write_data_st1;
-
-    `RESET_RELAY (mreq_reset, reset);
-
-    VX_fifo_queue #(
-        .DATAW    (1 + `CS_LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH), 
-        .DEPTH    (MREQ_SIZE),
-        .ALM_FULL (MREQ_SIZE-2),
-        .OUT_REG  (MEM_OUT_REG)
-    ) mem_req_queue (
-        .clk        (clk),
-        .reset      (mreq_reset),
-        .push       (mreq_push),
-        .pop        (mreq_pop),
-        .data_in    ({mreq_rw, mreq_addr, mreq_id, mreq_byteen, mreq_wsel, mreq_data}),
-        .data_out   ({mem_req_rw, mem_req_addr, mem_req_id, mem_req_byteen, mem_req_wsel, mem_req_data}),
-        .empty      (mreq_empty), 
-        .alm_full   (mreq_alm_full),
-        `UNUSED_PIN (full),
-        `UNUSED_PIN (alm_empty), 
-        `UNUSED_PIN (size)
-    );
-
-    assign mem_req_valid = ~mreq_empty;
-
-///////////////////////////////////////////////////////////////////////////////
-
-`ifdef PERF_ENABLE
-    assign perf_read_misses  = do_read_miss_st1;
-    assign perf_write_misses = do_write_miss_st1;
-    assign perf_mshr_stalls  = mshr_alm_full;
-`endif
-
-`ifdef DBG_TRACE_CACHE_BANK
-    wire crsq_fire = crsq_valid && crsq_ready;
-    wire pipeline_stall = (replay_valid || mem_rsp_valid || core_req_valid) 
-                       && ~(replay_fire || mem_rsp_fire || core_req_fire);
-    always @(posedge clk) begin
-        if (pipeline_stall) begin
-            `TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full));
-        end
-        if (init_enable) begin
-            `TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID)));
-        end
-        if (mem_rsp_fire) begin
-            `TRACE(2, ("%d: %s-bank%0d fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data));
-        end
-        if (replay_fire) begin
-            `TRACE(2, ("%d: %s-bank%0d mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel));
-        end
-        if (core_req_fire) begin
-            if (core_req_rw)
-                `TRACE(2, ("%d: %s-bank%0d core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel));
-            else
-                `TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel));
-        end
-        if (crsq_fire) begin
-            `TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_idx, crsq_data, req_uuid_st1));
-        end
-        if (mreq_push) begin
-            if (do_creq_wr_st1)
-                `TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_byteen, mreq_data, req_uuid_st1));
-            else
-                `TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_id, req_uuid_st1));
-        end
-    end    
-`endif
-
-endmodule

hw/rtl/cache/VX_cache_bypass.sv

@@ -1,348 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_platform.vh"
-
-module VX_cache_bypass #(
-    parameter NUM_REQS          = 1,
-    parameter NC_TAG_BIT        = 0,
-
-    parameter NC_ENABLE         = 0,
-    parameter PASSTHRU          = 0,
-
-    parameter CORE_ADDR_WIDTH   = 1,
-    parameter CORE_DATA_SIZE    = 1, 
-    parameter CORE_TAG_IN_WIDTH = 1,
-    
-    parameter MEM_ADDR_WIDTH    = 1,
-    parameter MEM_DATA_SIZE     = 1,
-    parameter MEM_TAG_IN_WIDTH  = 1,
-    parameter MEM_TAG_OUT_WIDTH = 1,
-
-    parameter UUID_WIDTH        = 0,
- 
-    parameter CORE_DATA_WIDTH   = CORE_DATA_SIZE * 8,
-    parameter MEM_DATA_WIDTH    = MEM_DATA_SIZE * 8,
-    parameter CORE_TAG_OUT_WIDTH= CORE_TAG_IN_WIDTH - NC_ENABLE
- ) ( 
-    input wire clk,
-    input wire reset,
-
-    // Core request in   
-    input wire [NUM_REQS-1:0]                       core_req_valid_in,
-    input wire [NUM_REQS-1:0]                       core_req_rw_in,
-    input wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0]  core_req_addr_in,
-    input wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0]   core_req_byteen_in,
-    input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0]  core_req_data_in,
-    input wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_req_tag_in,
-    output wire [NUM_REQS-1:0]                      core_req_ready_in,
-
-    // Core request out
-    output wire [NUM_REQS-1:0]                      core_req_valid_out,
-    output wire [NUM_REQS-1:0]                      core_req_rw_out,
-    output wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_out,
-    output wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0]  core_req_byteen_out,
-    output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_out,
-    output wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_req_tag_out,
-    input wire [NUM_REQS-1:0]                       core_req_ready_out,
-
-    // Core response in
-    input wire [NUM_REQS-1:0]                       core_rsp_valid_in,
-    input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0]  core_rsp_data_in,
-    input wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_rsp_tag_in,
-    output  wire [NUM_REQS-1:0]                     core_rsp_ready_in,   
-
-    // Core response out
-    output wire [NUM_REQS-1:0]                      core_rsp_valid_out,
-    output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out,
-    output wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out,
-    input  wire [NUM_REQS-1:0]                      core_rsp_ready_out,   
-
-    // Memory request in
-    input wire                          mem_req_valid_in,
-    input wire                          mem_req_rw_in,      
-    input wire [MEM_ADDR_WIDTH-1:0]     mem_req_addr_in,
-    input wire [MEM_DATA_SIZE-1:0]      mem_req_byteen_in,
-    input wire [MEM_DATA_WIDTH-1:0]     mem_req_data_in,
-    input wire [MEM_TAG_IN_WIDTH-1:0]   mem_req_tag_in,
-    output  wire                        mem_req_ready_in,
-
-    // Memory request out
-    output wire                         mem_req_valid_out,
-    output wire                         mem_req_rw_out,       
-    output wire [MEM_ADDR_WIDTH-1:0]    mem_req_addr_out,
-    output wire [MEM_DATA_SIZE-1:0]     mem_req_byteen_out, 
-    output wire [MEM_DATA_WIDTH-1:0]    mem_req_data_out,
-    output wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_out,
-    input  wire                         mem_req_ready_out,
-    
-    // Memory response in
-    input  wire                         mem_rsp_valid_in,    
-    input  wire [MEM_DATA_WIDTH-1:0]    mem_rsp_data_in,
-    input  wire [MEM_TAG_OUT_WIDTH-1:0] mem_rsp_tag_in,
-    output wire                         mem_rsp_ready_in,
-
-    // Memory response out
-    output  wire                        mem_rsp_valid_out,    
-    output  wire [MEM_DATA_WIDTH-1:0]   mem_rsp_data_out,
-    output  wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_out,
-    input wire                          mem_rsp_ready_out
-);
-    `UNUSED_VAR (clk)
-    `UNUSED_VAR (reset)    
-
-    localparam REQ_SEL_BITS     = `CLOG2(NUM_REQS);
-    localparam MUX_DATAW        = CORE_TAG_IN_WIDTH + CORE_DATA_WIDTH + CORE_DATA_SIZE + CORE_ADDR_WIDTH + 1;
-
-    localparam WORDS_PER_LINE   = MEM_DATA_SIZE / CORE_DATA_SIZE;
-    localparam WSEL_BITS        = `CLOG2(WORDS_PER_LINE);
-
-    localparam CORE_TAG_ID_BITS = CORE_TAG_IN_WIDTH - UUID_WIDTH;
-    localparam MEM_TAG_ID_BITS  = REQ_SEL_BITS + WSEL_BITS + CORE_TAG_ID_BITS;
-
-    localparam MEM_TAG_OUT_NC_WIDTH = MEM_TAG_OUT_WIDTH - 1 + NC_ENABLE;
-
-    // core request handling
-
-    wire [NUM_REQS-1:0] core_req_valid_in_nc;
-    wire [NUM_REQS-1:0] core_req_nc_idxs;    
-    wire [`UP(REQ_SEL_BITS)-1:0] core_req_nc_idx;
-    wire [NUM_REQS-1:0] core_req_nc_sel;
-    wire core_req_nc_valid;    
-    
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        if (PASSTHRU != 0) begin
-            assign core_req_nc_idxs[i] = 1'b1;
-        end else begin
-            assign core_req_nc_idxs[i] = core_req_tag_in[i][NC_TAG_BIT];
-        end
-    end
-
-    assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_idxs;
-
-    wire core_req_nc_ready = ~mem_req_valid_in && mem_req_ready_out;
-
-    VX_generic_arbiter #(
-        .NUM_REQS    (NUM_REQS),
-        .TYPE        (PASSTHRU ? "R" : "P"),
-        .LOCK_ENABLE (1)
-    ) core_req_nc_arb (
-        .clk          (clk),
-        .reset        (reset),        
-        .requests     (core_req_valid_in_nc),        
-        .grant_index  (core_req_nc_idx),
-        .grant_onehot (core_req_nc_sel),
-        .grant_valid  (core_req_nc_valid),
-        .grant_unlock (core_req_nc_ready)
-    );
-
-    assign core_req_valid_out  = core_req_valid_in & ~core_req_nc_idxs;
-    assign core_req_rw_out     = core_req_rw_in;
-    assign core_req_addr_out   = core_req_addr_in;
-    assign core_req_byteen_out = core_req_byteen_in;
-    assign core_req_data_out   = core_req_data_in;
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        VX_bits_remove #( 
-            .N   (CORE_TAG_IN_WIDTH),
-            .S   (NC_ENABLE),
-            .POS (NC_TAG_BIT)
-        ) core_req_tag_nc_remove (
-            .data_in  (core_req_tag_in[i]),
-            .data_out (core_req_tag_out[i])
-        );
-    end
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_req_ready_in[i] = core_req_valid_in_nc[i] ? (core_req_nc_ready && core_req_nc_sel[i]) 
-                                                              : core_req_ready_out[i];
-    end
-
-    // memory request handling
-
-    assign mem_req_valid_out = mem_req_valid_in || core_req_nc_valid;
-    assign mem_req_ready_in  = mem_req_ready_out;
-
-    wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel;
-    wire [CORE_DATA_WIDTH-1:0]   core_req_data_in_sel;
-    wire [CORE_DATA_SIZE-1:0]    core_req_byteen_in_sel;
-    wire [CORE_ADDR_WIDTH-1:0]   core_req_addr_in_sel;
-    wire                         core_req_rw_in_sel;
-
-    wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in;
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_req_nc_mux_in[i] = {core_req_tag_in[i], core_req_data_in[i], core_req_byteen_in[i], core_req_addr_in[i], core_req_rw_in[i]};
-    end
-    assign {core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel} = core_req_nc_mux_in[core_req_nc_idx];
-
-    wire [CORE_TAG_ID_BITS-1:0] core_req_in_id = core_req_tag_in_sel[CORE_TAG_ID_BITS-1:0];
-      
-    assign mem_req_rw_out   = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel;
-    assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[WSEL_BITS +: MEM_ADDR_WIDTH];
-
-    wire [MEM_TAG_ID_BITS-1:0] mem_req_tag_id_bypass;
-    
-    if (WORDS_PER_LINE > 1) begin
-        reg [WORDS_PER_LINE-1:0][CORE_DATA_SIZE-1:0]  mem_req_byteen_in_r;
-        reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r;
-        
-        wire [WSEL_BITS-1:0] req_wsel = core_req_addr_in_sel[WSEL_BITS-1:0];
-
-        always @(*) begin
-            mem_req_byteen_in_r = '0;
-            mem_req_byteen_in_r[req_wsel] = core_req_byteen_in_sel;
-
-            mem_req_data_in_r = 'x;
-            mem_req_data_in_r[req_wsel] = core_req_data_in_sel;
-        end
-
-        assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r;
-        assign mem_req_data_out   = mem_req_valid_in ? mem_req_data_in : mem_req_data_in_r;
-        if (NUM_REQS > 1) begin
-            assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, req_wsel, core_req_in_id});
-        end else begin 
-            assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({req_wsel, core_req_in_id});
-        end
-    end else begin
-        assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel;
-        assign mem_req_data_out   = mem_req_valid_in ? mem_req_data_in : core_req_data_in_sel;
-        if (NUM_REQS > 1) begin
-            assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, core_req_in_id});
-        end else begin
-            assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_in_id});
-        end
-    end
-
-    wire [MEM_TAG_OUT_NC_WIDTH-1:0] mem_req_tag_bypass;   
-
-    if (UUID_WIDTH != 0) begin
-        assign mem_req_tag_bypass = {core_req_tag_in_sel[CORE_TAG_ID_BITS +: UUID_WIDTH], mem_req_tag_id_bypass};
-    end else begin
-        assign mem_req_tag_bypass = mem_req_tag_id_bypass;
-    end
-
-    wire [MEM_TAG_OUT_WIDTH-1:0]      mem_req_tag_bypass_nc;
-    wire [(MEM_TAG_IN_WIDTH + 1)-1:0] mem_req_tag_in_nc;
-
-    VX_bits_insert #( 
-        .N   (MEM_TAG_OUT_NC_WIDTH),
-        .S   (NC_ENABLE ? 0 : 1),
-        .POS (NC_TAG_BIT)
-    ) mem_req_tag_bypass_nc_insert (
-        .data_in  (mem_req_tag_bypass),
-        .sel_in   (1'b0),
-        .data_out (mem_req_tag_bypass_nc)
-    );    
-
-    VX_bits_insert #( 
-        .N   (MEM_TAG_IN_WIDTH),
-        .POS (NC_TAG_BIT)
-    ) mem_req_tag_in_nc_insert (
-        .data_in  (mem_req_tag_in),
-        .sel_in   (1'b0),
-        .data_out (mem_req_tag_in_nc)
-    );
-
-    assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : mem_req_tag_bypass_nc;
-
-    // core response handling
-
-    wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_in_nc;
-
-    wire is_mem_rsp_nc;
-    if (PASSTHRU != 0) begin
-        assign is_mem_rsp_nc = mem_rsp_valid_in;
-    end else begin
-        assign is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT];
-    end
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        VX_bits_insert #( 
-            .N   (CORE_TAG_OUT_WIDTH),
-            .S   (NC_ENABLE),
-            .POS (NC_TAG_BIT)
-        ) core_rsp_tag_in_nc_insert (
-            .data_in  (core_rsp_tag_in[i]),
-            .sel_in   ('0),
-            .data_out (core_rsp_tag_in_nc[i])
-        );
-    end
-
-    wire [MEM_TAG_OUT_NC_WIDTH-1:0] mem_rsp_tag_in_nc;
-
-    VX_bits_remove #( 
-        .N   (MEM_TAG_OUT_WIDTH),
-        .S   (NC_ENABLE ? 0 : 1),
-        .POS (NC_TAG_BIT)
-    ) mem_rsp_tag_in_nc_remove (
-        .data_in  (mem_rsp_tag_in),
-        .data_out (mem_rsp_tag_in_nc)
-    );
-
-    wire [`UP(REQ_SEL_BITS)-1:0] rsp_idx;
-    if (NUM_REQS > 1) begin
-        assign rsp_idx = mem_rsp_tag_in_nc[(CORE_TAG_ID_BITS + WSEL_BITS) +: REQ_SEL_BITS];
-    end else begin 
-        assign rsp_idx = 1'b0;
-    end
-    
-    reg [NUM_REQS-1:0] rsp_nc_valid_r;
-    always @(*) begin
-        rsp_nc_valid_r = '0;
-        rsp_nc_valid_r[rsp_idx] = is_mem_rsp_nc;
-    end
-
-    assign core_rsp_valid_out = core_rsp_valid_in | rsp_nc_valid_r;
-    assign core_rsp_ready_in  = core_rsp_ready_out;
-
-    if (WORDS_PER_LINE > 1) begin
-        wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_in_nc[CORE_TAG_ID_BITS +: WSEL_BITS];        
-        for (genvar i = 0; i < NUM_REQS; ++i) begin
-            assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? 
-                core_rsp_data_in[i] : mem_rsp_data_in[rsp_wsel * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
-        end
-    end else begin
-        for (genvar i = 0; i < NUM_REQS; ++i) begin
-            assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? core_rsp_data_in[i] : mem_rsp_data_in;
-        end
-    end
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        if (UUID_WIDTH != 0) begin
-            assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_in_nc[i] : {mem_rsp_tag_in_nc[MEM_TAG_OUT_NC_WIDTH-1 -: UUID_WIDTH], mem_rsp_tag_in_nc[CORE_TAG_ID_BITS-1:0]};
-        end else begin
-            assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_in_nc[i] : mem_rsp_tag_in_nc[CORE_TAG_ID_BITS-1:0];
-        end
-    end
-
-    // memory response handling
-
-    if (PASSTHRU != 0) begin
-        assign mem_rsp_valid_out = 1'b0;
-    end else begin
-        assign mem_rsp_valid_out = mem_rsp_valid_in && ~mem_rsp_tag_in[NC_TAG_BIT];
-    end
-
-    assign mem_rsp_data_out  = mem_rsp_data_in;
-
-    VX_bits_remove #( 
-        .N   (MEM_TAG_IN_WIDTH + 1),
-        .POS (NC_TAG_BIT)
-    ) mem_rsp_tag_out_remove (
-        .data_in  (mem_rsp_tag_in[(MEM_TAG_IN_WIDTH + 1)-1:0]),
-        .data_out (mem_rsp_tag_out)
-    );
-
-    assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in[rsp_idx] && core_rsp_ready_out[rsp_idx]) : mem_rsp_ready_out;
-
-endmodule

hw/rtl/cache/VX_cache_cluster.sv

@@ -1,197 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_cluster import VX_gpu_pkg::*; #(
-    parameter `STRING INSTANCE_ID    = "",
-
-    parameter NUM_UNITS             = 1,
-    parameter NUM_INPUTS            = 1,
-    parameter TAG_SEL_IDX           = 0,
-
-    // Number of requests per cycle
-    parameter NUM_REQS              = 4,
-
-    // Size of cache in bytes
-    parameter CACHE_SIZE            = 16384, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE             = 64, 
-    // Number of banks
-    parameter NUM_BANKS             = 1,
-    // Number of associative ways
-    parameter NUM_WAYS              = 4,
-    // Size of a word in bytes
-    parameter WORD_SIZE             = 4, 
-
-    // Core Response Queue Size
-    parameter CRSQ_SIZE             = 2,
-    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE             = 8, 
-    // Memory Response Queue Size
-    parameter MRSQ_SIZE             = 0,
-    // Memory Request Queue Size
-    parameter MREQ_SIZE             = 4,
-
-    // Enable cache writeable
-    parameter WRITE_ENABLE          = 1,
-
-    // Request debug identifier
-    parameter UUID_WIDTH            = 0,
-
-    // core request tag size
-    parameter TAG_WIDTH             = UUID_WIDTH + 1,
-
-    // enable bypass for non-cacheable addresses
-    parameter NC_ENABLE             = 0,
-
-    // Core response output register
-    parameter CORE_OUT_REG          = 0,
-
-    // Memory request output register
-    parameter MEM_OUT_REG           = 0
- ) (    
-    input wire clk,
-    input wire reset,
-
-    // PERF
-`ifdef PERF_ENABLE
-    output cache_perf_t     cache_perf,
-`endif
-
-    VX_mem_bus_if.slave     core_bus_if [NUM_INPUTS * NUM_REQS],
-    VX_mem_bus_if.master    mem_bus_if
-);
-    localparam NUM_CACHES = `UP(NUM_UNITS);
-    localparam PASSTHRU   = (NUM_UNITS == 0);
-    localparam ARB_TAG_WIDTH = TAG_WIDTH + `ARB_SEL_BITS(NUM_INPUTS, NUM_CACHES);    
-    localparam MEM_TAG_WIDTH = PASSTHRU ? (NC_ENABLE ? `CACHE_NC_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH) : 
-                                                       `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH)) : 
-                                          (NC_ENABLE ? `CACHE_NC_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, NUM_REQS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH) :
-                                                       `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS));
-
-    `STATIC_ASSERT(NUM_INPUTS >= NUM_CACHES, ("invalid parameter"))
-
-`ifdef PERF_ENABLE
-    cache_perf_t perf_cache_tmp[1], perf_cache_unit[NUM_CACHES];
-    `PERF_CACHE_ADD (perf_cache_tmp, perf_cache_unit, 1, NUM_CACHES)
-    assign cache_perf = perf_cache_tmp[0];
-`endif
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (LINE_SIZE),
-        .TAG_WIDTH (MEM_TAG_WIDTH)
-    ) cache_mem_bus_if[NUM_CACHES]();
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (WORD_SIZE),
-        .TAG_WIDTH (ARB_TAG_WIDTH)
-    ) arb_core_bus_if[NUM_CACHES * NUM_REQS]();
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        VX_mem_bus_if #(
-            .DATA_SIZE (WORD_SIZE),
-            .TAG_WIDTH (TAG_WIDTH)
-        ) core_bus_tmp_if[NUM_INPUTS]();
-
-        VX_mem_bus_if #(
-            .DATA_SIZE (WORD_SIZE),
-            .TAG_WIDTH (ARB_TAG_WIDTH)
-        ) arb_core_bus_tmp_if[NUM_CACHES]();
-
-        for (genvar j = 0; j < NUM_INPUTS; ++j) begin
-            `ASSIGN_VX_MEM_BUS_IF (core_bus_tmp_if[j], core_bus_if[j * NUM_REQS + i]);
-        end
-
-        `RESET_RELAY (cache_arb_reset, reset);
-
-        VX_mem_arb #(
-            .NUM_INPUTS   (NUM_INPUTS),
-            .NUM_OUTPUTS  (NUM_CACHES),
-            .DATA_SIZE    (WORD_SIZE),
-            .TAG_WIDTH    (TAG_WIDTH),
-            .TAG_SEL_IDX  (TAG_SEL_IDX),
-            .ARBITER      ("R"),
-            .OUT_REG_REQ  ((NUM_INPUTS != NUM_CACHES) ? 2 : 0),
-            .OUT_REG_RSP  ((NUM_INPUTS != NUM_CACHES) ? 2 : 0)
-        ) cache_arb (
-            .clk        (clk),
-            .reset      (cache_arb_reset),
-            .bus_in_if  (core_bus_tmp_if),
-            .bus_out_if (arb_core_bus_tmp_if)
-        );
-
-        for (genvar k = 0; k < NUM_CACHES; ++k) begin
-            `ASSIGN_VX_MEM_BUS_IF (arb_core_bus_if[k * NUM_REQS + i], arb_core_bus_tmp_if[k]);
-        end
-    end
-
-    for (genvar i = 0; i < NUM_CACHES; ++i) begin
-
-        `RESET_RELAY (cache_reset, reset);
-
-        VX_cache_wrap #(
-            .INSTANCE_ID  ($sformatf("%s%0d", INSTANCE_ID, i)),
-            .CACHE_SIZE   (CACHE_SIZE),
-            .LINE_SIZE    (LINE_SIZE),
-            .NUM_BANKS    (NUM_BANKS),
-            .NUM_WAYS     (NUM_WAYS),
-            .WORD_SIZE    (WORD_SIZE),
-            .NUM_REQS     (NUM_REQS),
-            .CRSQ_SIZE    (CRSQ_SIZE),
-            .MSHR_SIZE    (MSHR_SIZE),
-            .MRSQ_SIZE    (MRSQ_SIZE),
-            .MREQ_SIZE    (MREQ_SIZE),
-            .WRITE_ENABLE (WRITE_ENABLE),
-            .UUID_WIDTH   (UUID_WIDTH),
-            .TAG_WIDTH    (ARB_TAG_WIDTH),
-            .CORE_OUT_REG ((NUM_INPUTS != NUM_CACHES) ? 2 : CORE_OUT_REG),
-            .MEM_OUT_REG  ((NUM_CACHES > 1) ? 2 : MEM_OUT_REG),
-            .NC_ENABLE    (NC_ENABLE),
-            .PASSTHRU     (PASSTHRU)
-        ) cache_wrap (
-        `ifdef PERF_ENABLE
-            .cache_perf  (perf_cache_unit[i]),
-        `endif
-            .clk         (clk),
-            .reset       (cache_reset),
-            .core_bus_if (arb_core_bus_if[i * NUM_REQS +: NUM_REQS]),
-            .mem_bus_if  (cache_mem_bus_if[i])
-        );
-    end
-
-    `RESET_RELAY (mem_arb_reset, reset);
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (LINE_SIZE),
-        .TAG_WIDTH (MEM_TAG_WIDTH + `ARB_SEL_BITS(NUM_CACHES, 1))
-    ) mem_bus_tmp_if[1]();
-
-    VX_mem_arb #(
-        .NUM_INPUTS   (NUM_CACHES),
-        .DATA_SIZE    (LINE_SIZE),
-        .TAG_WIDTH    (MEM_TAG_WIDTH),
-        .TAG_SEL_IDX  (1), // Skip 0 for NC flag
-        .ARBITER      ("R"),
-        .OUT_REG_REQ ((NUM_CACHES > 1) ? 2 : 0),
-        .OUT_REG_RSP ((NUM_CACHES > 1) ? 2 : 0)
-    ) mem_arb (
-        .clk        (clk),
-        .reset      (mem_arb_reset),
-        .bus_in_if  (cache_mem_bus_if),
-        .bus_out_if (mem_bus_tmp_if)
-    );
-
-    `ASSIGN_VX_MEM_BUS_IF (mem_bus_if, mem_bus_tmp_if[0]);
-
-endmodule

hw/rtl/cache/VX_cache_data.sv

@@ -1,152 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_data #(
-    parameter `STRING INSTANCE_ID= "",
-    parameter BANK_ID           = 0,
-    // Size of cache in bytes
-    parameter CACHE_SIZE        = 1024, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE         = 16, 
-    // Number of banks
-    parameter NUM_BANKS         = 1, 
-    // Number of associative ways
-    parameter NUM_WAYS          = 1,
-    // Size of a word in bytes
-    parameter WORD_SIZE         = 1,
-    // Enable cache writeable
-    parameter WRITE_ENABLE      = 1,
-    // Request debug identifier
-    parameter UUID_WIDTH        = 0
-) (
-    input wire                          clk,
-    input wire                          reset,
-
-`IGNORE_UNUSED_BEGIN
-    input wire[`UP(UUID_WIDTH)-1:0]     req_uuid,
-`IGNORE_UNUSED_END
-
-    input wire                          stall,
-
-    input wire                          read,
-    input wire                          fill, 
-    input wire                          write,
-    input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr,
-    input wire [`UP(`CS_WORD_SEL_BITS)-1:0] wsel,
-    input wire [WORD_SIZE-1:0]          byteen,
-    input wire [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] fill_data,
-    input wire [`CS_WORD_WIDTH-1:0]     write_data,
-    input wire [NUM_WAYS-1:0]           way_sel,
-
-    output wire [`CS_WORD_WIDTH-1:0]    read_data
-);
-    `UNUSED_SPARAM (INSTANCE_ID)
-    `UNUSED_PARAM (BANK_ID)
-    `UNUSED_PARAM (WORD_SIZE)
-    `UNUSED_VAR (reset)
-    `UNUSED_VAR (line_addr)
-    `UNUSED_VAR (read)
-
-    localparam BYTEENW = (WRITE_ENABLE != 0 || (NUM_WAYS > 1)) ? (LINE_SIZE * NUM_WAYS) : 1;
-
-    wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] wdata;
-    wire [BYTEENW-1:0] wren;
-
-    if (WRITE_ENABLE != 0 || (NUM_WAYS > 1)) begin
-        reg [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] wdata_r;
-        reg [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wren_r;
-
-        always @(*) begin
-            wdata_r = {`CS_WORDS_PER_LINE{write_data}};
-            wren_r  = '0;
-            wren_r[wsel] = byteen;
-        end
-        
-        // order the data layout to perform ways multiplexing last 
-        // this allows performing onehot encoding of the way index in parallel with BRAM read.
-        wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][WORD_SIZE-1:0] wren_w;
-        for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin
-            assign wdata[i] = fill ? {NUM_WAYS{fill_data[i]}} : {NUM_WAYS{wdata_r[i]}};            
-            for (genvar j = 0; j < NUM_WAYS; ++j) begin
-                assign wren_w[i][j] = (fill ? {WORD_SIZE{1'b1}} : wren_r[i])
-                                    & {WORD_SIZE{((NUM_WAYS == 1) || way_sel[j])}};
-            end
-        end
-        assign wren = wren_w;
-    end else begin
-        `UNUSED_VAR (write)
-        `UNUSED_VAR (byteen)
-        `UNUSED_VAR (write_data)
-        assign wdata = fill_data;
-        assign wren  = fill;
-    end
-    
-    wire [`LOG2UP(NUM_WAYS)-1:0] way_idx;
-
-    VX_onehot_encoder #(
-        .N (NUM_WAYS)
-    ) way_enc (
-        .data_in  (way_sel),
-        .data_out (way_idx),
-        `UNUSED_PIN (valid_out)
-    );
-
-    wire [`CS_WORDS_PER_LINE-1:0][NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] rdata;
-
-    wire [`CS_LINE_SEL_BITS-1:0] line_sel = line_addr[`CS_LINE_SEL_BITS-1:0];
-    
-    VX_sp_ram #(
-        .DATAW (`CS_LINE_WIDTH * NUM_WAYS),
-        .SIZE  (`CS_LINES_PER_BANK),
-        .WRENW (BYTEENW),
-        .NO_RWCHECK (1)
-    ) data_store (
-        .clk   (clk),
-        .read  (1'b1),
-        .write (write || fill),
-        .wren  (wren),
-        .addr  (line_sel),
-        .wdata (wdata),
-        .rdata (rdata) 
-    );
-
-    wire [NUM_WAYS-1:0][`CS_WORD_WIDTH-1:0] per_way_rdata;
-
-    if (`CS_WORDS_PER_LINE > 1) begin
-        assign per_way_rdata = rdata[wsel];
-    end else begin
-        `UNUSED_VAR (wsel)
-        assign per_way_rdata = rdata;
-    end    
-
-    assign read_data = per_way_rdata[way_idx];
-
-    `UNUSED_VAR (stall)
-
-`ifdef DBG_TRACE_CACHE_DATA
-    always @(posedge clk) begin 
-        if (fill && ~stall) begin
-            `TRACE(3, ("%d: %s-bank%0d data-fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, fill_data));
-        end
-        if (read && ~stall) begin
-            `TRACE(3, ("%d: %s-bank%0d data-read: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, read_data, req_uuid));
-        end 
-        if (write && ~stall) begin
-            `TRACE(3, ("%d: %s-bank%0d data-write: addr=0x%0h, way=%b, blk_addr=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, byteen, write_data, req_uuid));
-        end      
-    end    
-`endif
-
-endmodule

hw/rtl/cache/VX_cache_define.vh

@@ -1,77 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_CACHE_DEFINE_VH
-`define VX_CACHE_DEFINE_VH
-
-`include "VX_define.vh"   
-
-`define CS_REQ_SEL_BITS         `CLOG2(NUM_REQS)
-
-`define CS_WORD_WIDTH           (8 * WORD_SIZE)
-`define CS_LINE_WIDTH           (8 * LINE_SIZE)
-`define CS_BANK_SIZE            (CACHE_SIZE / NUM_BANKS)
-`define CS_WAY_SEL_BITS         `CLOG2(NUM_WAYS)
-
-`define CS_LINES_PER_BANK       (`CS_BANK_SIZE / (LINE_SIZE * NUM_WAYS))
-`define CS_WORDS_PER_LINE       (LINE_SIZE / WORD_SIZE)
-
-`define CS_WORD_ADDR_WIDTH      (`MEM_ADDR_WIDTH-`CLOG2(WORD_SIZE))
-`define CS_MEM_ADDR_WIDTH       (`MEM_ADDR_WIDTH-`CLOG2(LINE_SIZE))
-`define CS_LINE_ADDR_WIDTH      (`CS_MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS))
-
-// Word select
-`define CS_WORD_SEL_BITS        `CLOG2(`CS_WORDS_PER_LINE)
-`define CS_WORD_SEL_ADDR_START  0
-`define CS_WORD_SEL_ADDR_END    (`CS_WORD_SEL_ADDR_START+`CS_WORD_SEL_BITS-1)
-
-// Bank select
-`define CS_BANK_SEL_BITS        `CLOG2(NUM_BANKS)
-`define CS_BANK_SEL_ADDR_START  (1+`CS_WORD_SEL_ADDR_END)
-`define CS_BANK_SEL_ADDR_END    (`CS_BANK_SEL_ADDR_START+`CS_BANK_SEL_BITS-1)
-
-// Line select
-`define CS_LINE_SEL_BITS        `CLOG2(`CS_LINES_PER_BANK)
-`define CS_LINE_SEL_ADDR_START  (1+`CS_BANK_SEL_ADDR_END)
-`define CS_LINE_SEL_ADDR_END    (`CS_LINE_SEL_ADDR_START+`CS_LINE_SEL_BITS-1)
-
-// Tag select
-`define CS_TAG_SEL_BITS         (`CS_WORD_ADDR_WIDTH-1-`CS_LINE_SEL_ADDR_END)
-`define CS_TAG_SEL_ADDR_START   (1+`CS_LINE_SEL_ADDR_END)
-`define CS_TAG_SEL_ADDR_END     (`CS_WORD_ADDR_WIDTH-1)
-
-`define CS_LINE_TAG_ADDR(x)     x[`CS_LINE_ADDR_WIDTH-1 : `CS_LINE_SEL_BITS]
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define CS_LINE_TO_MEM_ADDR(x, i)  {x, `CS_BANK_SEL_BITS'(i)}
-`define CS_MEM_ADDR_TO_BANK_ID(x)  x[0 +: `CS_BANK_SEL_BITS]
-`define CS_MEM_TAG_TO_REQ_ID(x)    x[MSHR_ADDR_WIDTH-1:0]
-`define CS_MEM_TAG_TO_BANK_ID(x)   x[MSHR_ADDR_WIDTH +: `CS_BANK_SEL_BITS]
-
-`define CS_LINE_TO_FULL_ADDR(x, i) {x, (`XLEN-$bits(x))'(i << (`XLEN-$bits(x)-`CS_BANK_SEL_BITS))}
-`define CS_MEM_TO_FULL_ADDR(x)     {x, (`XLEN-$bits(x))'(0)}
-
-///////////////////////////////////////////////////////////////////////////////
-
-`define PERF_CACHE_ADD(dst, src, dcount, scount) \
-    `PERF_COUNTER_ADD (dst, src, reads, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, writes, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, read_misses, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, write_misses, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, bank_stalls, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, mshr_stalls, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, mem_stalls, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1)) \
-    `PERF_COUNTER_ADD (dst, src, crsp_stalls, `PERF_CTR_BITS, dcount, scount, (((scount + dcount - 1) / dcount) > 1))
-
-`endif // VX_CACHE_DEFINE_VH

hw/rtl/cache/VX_cache_init.sv

@@ -1,51 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_init #(
-    // Size of cache in bytes
-    parameter CACHE_SIZE    = 1024, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE     = 16, 
-    // Number of banks
-    parameter NUM_BANKS     = 1,
-    // Number of associative ways
-    parameter NUM_WAYS      = 1
-) (
-    input  wire clk,
-    input  wire reset,    
-    output wire [`CS_LINE_SEL_BITS-1:0] addr_out,
-    output wire valid_out
-);
-    reg enabled;
-    reg [`CS_LINE_SEL_BITS-1:0] line_ctr;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            enabled  <= 1;
-            line_ctr <= '0;
-        end else begin
-            if (enabled) begin
-                if (line_ctr == ((2 ** `CS_LINE_SEL_BITS)-1)) begin
-                    enabled <= 0;
-                end
-                line_ctr <= line_ctr + `CS_LINE_SEL_BITS'(1);           
-            end
-        end
-    end
-
-    assign addr_out  = line_ctr;
-    assign valid_out = enabled;
-
-endmodule

hw/rtl/cache/VX_cache_mshr.sv

@@ -1,271 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-// this is an implementation of a pipelined multi-banked cache
-// we allocate a free slot from the MSHR before processing a core request
-// and release the slot when we get a cache hit.
-// during a memory fill response we initiate the replay sequence 
-// and dequeue all associated pending entries.
-
-// Warning: This MSHR implementation is strongly coupled with the bank pipeline
-// and as such changes to either module requires careful evaluation.
-// This implementation makes the following assumptions:
-// (1) two-cycle pipeline: st0 and st1.
-// (2) core request flow: st0: allocate / lookup, st1: finalize.
-// (3) the first dequeue after the fill should happen in st0, when the fill is in st1
-//     this is enforced inside the bank by "rdw_hazard_st0".
-
-module VX_cache_mshr #(
-    parameter `STRING INSTANCE_ID= "",
-    parameter BANK_ID           = 0,
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE         = 16, 
-    // Number of banks
-    parameter NUM_BANKS         = 1,
-    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE         = 4,
-    // Request debug identifier
-    parameter UUID_WIDTH        = 0,
-    // MSHR parameters
-    parameter DATA_WIDTH        = 1,
-    parameter MSHR_ADDR_WIDTH   = `LOG2UP(MSHR_SIZE)
-) (
-    input wire clk,
-    input wire reset,
-
-`IGNORE_UNUSED_BEGIN
-    input wire[`UP(UUID_WIDTH)-1:0]     deq_req_uuid,
-    input wire[`UP(UUID_WIDTH)-1:0]     lkp_req_uuid,
-    input wire[`UP(UUID_WIDTH)-1:0]     fin_req_uuid,
-`IGNORE_UNUSED_END
-
-    // allocate
-    input wire                          allocate_valid,
-    input wire [`CS_LINE_ADDR_WIDTH-1:0] allocate_addr,
-    input wire                          allocate_rw,
-    input wire [DATA_WIDTH-1:0]         allocate_data,
-    output wire [MSHR_ADDR_WIDTH-1:0]   allocate_id,
-    output wire [MSHR_ADDR_WIDTH-1:0]   allocate_tail,
-    output wire                         allocate_ready,
-
-    // lookup
-    input wire                          lookup_valid,
-    input wire [`CS_LINE_ADDR_WIDTH-1:0] lookup_addr,
-    output wire [MSHR_SIZE-1:0]         lookup_matches,
-
-    // memory fill
-    input wire                          fill_valid,
-    input wire [MSHR_ADDR_WIDTH-1:0]    fill_id,
-    output wire [`CS_LINE_ADDR_WIDTH-1:0] fill_addr,
-    
-    // dequeue    
-    output wire                         dequeue_valid,
-    output wire [`CS_LINE_ADDR_WIDTH-1:0] dequeue_addr,
-    output wire                         dequeue_rw,
-    output wire [DATA_WIDTH-1:0]        dequeue_data,
-    output wire [MSHR_ADDR_WIDTH-1:0]   dequeue_id,
-    input wire                          dequeue_ready,
-
-    // finalize
-    input wire                          finalize_valid,
-    input wire                          finalize_release,
-    input wire                          finalize_pending,
-    input wire [MSHR_ADDR_WIDTH-1:0]    finalize_id,
-    input wire [MSHR_ADDR_WIDTH-1:0]    finalize_tail
-);
-    `UNUSED_PARAM (BANK_ID)    
-    
-    reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
-    reg [MSHR_ADDR_WIDTH-1:0] next_index [MSHR_SIZE-1:0];
-
-    reg [MSHR_SIZE-1:0] valid_table, valid_table_n;
-    reg [MSHR_SIZE-1:0] next_table, next_table_x, next_table_n;
-    reg [MSHR_SIZE-1:0] write_table;
-    
-    reg allocate_rdy, allocate_rdy_n;
-    reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n;
-    
-    reg dequeue_val, dequeue_val_n;
-    reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n;
-
-    wire [MSHR_ADDR_WIDTH-1:0] tail_idx;
-    
-    wire allocate_fire = allocate_valid && allocate_ready;
-    wire dequeue_fire = dequeue_valid && dequeue_ready;
-
-    wire [MSHR_SIZE-1:0] addr_matches;
-    for (genvar i = 0; i < MSHR_SIZE; ++i) begin
-        assign addr_matches[i] = valid_table[i] && (addr_table[i] == lookup_addr);
-    end
-
-    VX_lzc #(
-        .N (MSHR_SIZE),
-        .REVERSE (1)
-    ) allocate_sel (
-        .data_in   (~valid_table_n),
-        .data_out  (allocate_id_n),
-        .valid_out (allocate_rdy_n)
-    );
-
-    VX_onehot_encoder #(
-        .N (MSHR_SIZE)
-    ) tail_sel (
-        .data_in (addr_matches & ~next_table_x),
-        .data_out (tail_idx),
-        `UNUSED_PIN (valid_out)
-    );
-
-    always @(*) begin
-        valid_table_n = valid_table;
-        next_table_x  = next_table;
-        dequeue_val_n = dequeue_val;
-        dequeue_id_n  = dequeue_id;
-
-        if (fill_valid) begin
-            dequeue_val_n = 1;
-            dequeue_id_n = fill_id;
-        end
-
-        if (dequeue_fire) begin
-            valid_table_n[dequeue_id] = 0;
-            if (next_table[dequeue_id]) begin
-                dequeue_id_n = next_index[dequeue_id];
-            end else begin
-                dequeue_val_n = 0;
-            end
-        end
-
-        if (finalize_valid) begin
-            if (finalize_release) begin
-                valid_table_n[finalize_id] = 0;
-            end
-            if (finalize_pending) begin
-                next_table_x[finalize_tail] = 1;
-            end
-        end
-
-        next_table_n = next_table_x;
-        if (allocate_fire) begin
-            valid_table_n[allocate_id] = 1;
-            next_table_n[allocate_id] = 0;
-        end
-    end
-
-    always @(posedge clk) begin
-        if (reset) begin
-            valid_table  <= '0;
-            allocate_rdy <= 0;
-            dequeue_val  <= 0;
-        end else begin
-            valid_table  <= valid_table_n;
-            allocate_rdy <= allocate_rdy_n;
-            dequeue_val  <= dequeue_val_n;
-        end
-
-        if (allocate_fire) begin
-            addr_table[allocate_id]  <= allocate_addr;
-            write_table[allocate_id] <= allocate_rw;
-        end
-
-        if (finalize_valid && finalize_pending) begin
-            next_index[finalize_tail] <= finalize_id;
-        end
-
-        dequeue_id_r  <= dequeue_id_n;
-        allocate_id_r <= allocate_id_n;
-        next_table    <= next_table_n;
-    end
-    
-    `RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s-bank%0d inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID, 
-        `CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id_r, lkp_req_uuid))
-
-    `RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s-bank%0d invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID, 
-        `CS_LINE_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid))
-    
-    `RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s-bank%0d invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID, BANK_ID, 
-        `CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id))
-
-    VX_dp_ram #(
-        .DATAW  (DATA_WIDTH),
-        .SIZE   (MSHR_SIZE),
-        .LUTRAM (1)
-    ) entries (
-        .clk   (clk),
-        .read  (1'b1),
-        .write (allocate_valid),
-        `UNUSED_PIN (wren),               
-        .waddr (allocate_id_r),     
-        .wdata (allocate_data),
-        .raddr (dequeue_id_r),
-        .rdata (dequeue_data)
-    );
-
-    assign fill_addr = addr_table[fill_id];
-
-    assign allocate_ready = allocate_rdy;
-    assign allocate_id    = allocate_id_r;
-    assign allocate_tail  = tail_idx;
-
-    assign dequeue_valid  = dequeue_val;
-    assign dequeue_addr   = addr_table[dequeue_id_r];
-    assign dequeue_rw     = write_table[dequeue_id_r];
-    assign dequeue_id     = dequeue_id_r;
-
-    assign lookup_matches = addr_matches & ~write_table;
-
-    `UNUSED_VAR (lookup_valid)
-
-`ifdef DBG_TRACE_CACHE_MSHR        
-    reg show_table;
-    always @(posedge clk) begin
-        if (reset) begin
-            show_table <= 0;
-        end else begin
-            show_table <= allocate_fire || lookup_valid || finalize_valid || fill_valid || dequeue_fire;
-        end
-        if (allocate_fire)
-            `TRACE(3, ("%d: %s-bank%0d mshr-allocate: addr=0x%0h, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
-                `CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_tail, allocate_id, lkp_req_uuid));
-        if (lookup_valid)
-            `TRACE(3, ("%d: %s-bank%0d mshr-lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID, BANK_ID, 
-                `CS_LINE_TO_FULL_ADDR(lookup_addr, BANK_ID), lookup_matches, lkp_req_uuid));
-        if (finalize_valid)
-            `TRACE(3, ("%d: %s-bank%0d mshr-finalize release=%b, pending=%b, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, 
-                finalize_release, finalize_pending, finalize_tail, finalize_id, fin_req_uuid));
-        if (fill_valid)
-            `TRACE(3, ("%d: %s-bank%0d mshr-fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID, BANK_ID, 
-                `CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), `CS_LINE_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id));
-        if (dequeue_fire)
-            `TRACE(3, ("%d: %s-bank%0d mshr-dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, 
-                `CS_LINE_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid));
-        if (show_table) begin
-            `TRACE(3, ("%d: %s-bank%0d mshr-table", $time, INSTANCE_ID, BANK_ID));
-            for (integer i = 0; i < MSHR_SIZE; ++i) begin
-                if (valid_table[i]) begin
-                    `TRACE(3, (" %0d=0x%0h", i, `CS_LINE_TO_FULL_ADDR(addr_table[i], BANK_ID)));
-                    if (write_table[i])
-                        `TRACE(3, ("(w)"));
-                    else
-                        `TRACE(3, ("(r)"));
-                    if (next_table[i])
-                        `TRACE(3, ("->%0d", next_index[i]));
-                end
-            end
-            `TRACE(3, ("\n"));
-        end        
-    end
-`endif
-
-endmodule

hw/rtl/cache/VX_cache_tags.sv

@@ -1,116 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_tags #(
-    parameter `STRING INSTANCE_ID = "",
-    parameter BANK_ID       = 0,
-    // Size of cache in bytes
-    parameter CACHE_SIZE    = 1024, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE     = 16, 
-    // Number of banks
-    parameter NUM_BANKS     = 1, 
-    // Number of associative ways
-    parameter NUM_WAYS      = 1, 
-    // Size of a word in bytes
-    parameter WORD_SIZE     = 1, 
-    // Request debug identifier
-    parameter UUID_WIDTH    = 0
-) (
-    input wire                          clk,
-    input wire                          reset,
-
-`IGNORE_UNUSED_BEGIN
-    input wire [`UP(UUID_WIDTH)-1:0]    req_uuid,
-`IGNORE_UNUSED_END
-
-    input wire                          stall,
-
-    // read/fill
-    input wire                          lookup,
-    input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr,
-    input wire                          fill,    
-    input wire                          init,
-    output wire [NUM_WAYS-1:0]          way_sel,
-    output wire [NUM_WAYS-1:0]          tag_matches
-);
-    `UNUSED_SPARAM (INSTANCE_ID)
-    `UNUSED_PARAM (BANK_ID)
-    `UNUSED_VAR (reset)
-    `UNUSED_VAR (lookup)
-
-    localparam TAG_WIDTH = 1 + `CS_TAG_SEL_BITS;
-
-    wire [`CS_LINE_SEL_BITS-1:0] line_sel = line_addr[`CS_LINE_SEL_BITS-1:0];
-    wire [`CS_TAG_SEL_BITS-1:0] line_tag = `CS_LINE_TAG_ADDR(line_addr);
-
-    if (NUM_WAYS > 1)  begin
-        reg [NUM_WAYS-1:0] repl_way;
-        // cyclic assignment of replacement way
-        always @(posedge clk) begin
-            if (reset) begin
-                repl_way <= 1;
-            end else if (~stall) begin // hold the value on stalls prevent filling different slots twice
-                repl_way <= {repl_way[NUM_WAYS-2:0], repl_way[NUM_WAYS-1]};
-            end
-        end        
-        for (genvar i = 0; i < NUM_WAYS; ++i) begin
-            assign way_sel[i] = fill && repl_way[i];
-        end
-    end else begin
-        `UNUSED_VAR (stall)
-        assign way_sel = fill;
-    end
-
-    for (genvar i = 0; i < NUM_WAYS; ++i) begin
-        wire [`CS_TAG_SEL_BITS-1:0] read_tag;
-        wire read_valid;
-
-        VX_sp_ram #(
-            .DATAW (TAG_WIDTH),
-            .SIZE  (`CS_LINES_PER_BANK),
-            .NO_RWCHECK (1)
-        ) tag_store (
-            .clk   (clk),
-            .read  (1'b1),
-            .write (way_sel[i] || init),
-            `UNUSED_PIN (wren),                
-            .addr  (line_sel),
-            .wdata ({~init, line_tag}), 
-            .rdata ({read_valid, read_tag})
-        );
-        
-        assign tag_matches[i] = read_valid && (line_tag == read_tag);
-    end
-    
-`ifdef DBG_TRACE_CACHE_TAG
-    always @(posedge clk) begin
-        if (fill && ~stall) begin
-            `TRACE(3, ("%d: %s-bank%0d tag-fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag));
-        end
-        if (init) begin
-            `TRACE(3, ("%d: %s-bank%0d tag-init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel));
-        end
-        if (lookup && ~stall) begin
-            if (tag_matches != 0) begin
-                `TRACE(3, ("%d: %s-bank%0d tag-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_sel, line_sel, line_tag, req_uuid));
-            end else begin
-                `TRACE(3, ("%d: %s-bank%0d tag-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid));
-            end
-        end          
-    end    
-`endif
-
-endmodule

hw/rtl/cache/VX_cache_top.sv

@@ -1,168 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_top import VX_gpu_pkg::*; #(
-    parameter `STRING INSTANCE_ID    = "",
-
-    // Number of Word requests per cycle
-    parameter NUM_REQS              = 4,
-
-    // Size of cache in bytes
-    parameter CACHE_SIZE            = 16384, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE             = 64, 
-    // Number of banks
-    parameter NUM_BANKS             = 4,
-    // Number of associative ways
-    parameter NUM_WAYS              = 4,
-    // Size of a word in bytes
-    parameter WORD_SIZE             = 4, 
-
-    // Core Response Queue Size
-    parameter CRSQ_SIZE             = 2,
-    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE             = 16, 
-    // Memory Response Queue Size
-    parameter MRSQ_SIZE             = 0,
-    // Memory Request Queue Size
-    parameter MREQ_SIZE             = 4,
-
-    // Enable cache writeable
-    parameter WRITE_ENABLE          = 1,
-
-    // Request debug identifier
-    parameter UUID_WIDTH            = 0,
-
-    // core request tag size
-    parameter TAG_WIDTH             = 16,
-
-    // Core response output register
-    parameter CORE_OUT_REG          = 2,
-
-    // Memory request output register
-    parameter MEM_OUT_REG           = 2,
-
-    parameter MEM_TAG_WIDTH = `CLOG2(MSHR_SIZE) + `CLOG2(NUM_BANKS)
- ) (    
-    input wire clk,
-    input wire reset,
-
-// PERF
-`ifdef PERF_ENABLE
-    output cache_perf_t cache_perf,
-`endif
-
-    // Core request
-    input  wire [NUM_REQS-1:0]                 core_req_valid,
-    input  wire [NUM_REQS-1:0]                 core_req_rw,
-    input  wire [NUM_REQS-1:0][WORD_SIZE-1:0]  core_req_byteen,
-    input  wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr,
-    input  wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data,
-    input  wire [NUM_REQS-1:0][TAG_WIDTH-1:0]  core_req_tag,
-    output wire [NUM_REQS-1:0]                 core_req_ready,
-
-    // Core response
-    output wire [NUM_REQS-1:0]                 core_rsp_valid,
-    output wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data,
-    output wire [NUM_REQS-1:0][TAG_WIDTH-1:0]  core_rsp_tag,
-    input  wire [NUM_REQS-1:0]                 core_rsp_ready,
-
-    // Memory request
-    output wire                    mem_req_valid,
-    output wire                    mem_req_rw, 
-    output wire [LINE_SIZE-1:0]    mem_req_byteen,
-    output wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr,
-    output wire [`CS_LINE_WIDTH-1:0] mem_req_data, 
-    output wire [MEM_TAG_WIDTH-1:0] mem_req_tag, 
-    input  wire                    mem_req_ready,
-    
-    // Memory response
-    input  wire                    mem_rsp_valid, 
-    input  wire [`CS_LINE_WIDTH-1:0] mem_rsp_data,
-    input  wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag, 
-    output wire                    mem_rsp_ready
-);
-    VX_mem_bus_if #(
-        .DATA_SIZE (WORD_SIZE),
-        .TAG_WIDTH (TAG_WIDTH)
-    ) core_bus_if[NUM_REQS]();
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (LINE_SIZE),
-        .TAG_WIDTH (MEM_TAG_WIDTH)
-    ) mem_bus_if();
-
-    // Core request
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_bus_if[i].req_valid = core_req_valid[i];
-        assign core_bus_if[i].req_data.rw = core_req_rw[i];
-        assign core_bus_if[i].req_data.byteen = core_req_byteen[i];
-        assign core_bus_if[i].req_data.addr = core_req_addr[i];
-        assign core_bus_if[i].req_data.data = core_req_data[i];
-        assign core_bus_if[i].req_data.tag = core_req_tag[i];
-        assign core_req_ready[i] = core_bus_if[i].req_ready;
-    end
-
-    // Core response
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_rsp_valid[i] = core_bus_if[i].rsp_valid;
-        assign core_rsp_data[i] = core_bus_if[i].rsp_data.data;
-        assign core_rsp_tag[i] = core_bus_if[i].rsp_data.tag;
-        assign core_bus_if[i].rsp_ready = core_rsp_ready[i];
-    end
-
-    // Memory request
-    assign mem_req_valid = mem_bus_if.req_valid;
-    assign mem_req_rw = mem_bus_if.req_data.rw; 
-    assign mem_req_byteen = mem_bus_if.req_data.byteen;
-    assign mem_req_addr = mem_bus_if.req_data.addr;
-    assign mem_req_data = mem_bus_if.req_data.data;  
-    assign mem_req_tag = mem_bus_if.req_data.tag; 
-    assign mem_bus_if.req_ready = mem_req_ready;
-    
-    // Memory response
-    assign mem_bus_if.rsp_valid = mem_rsp_valid;    
-    assign mem_bus_if.rsp_data.data = mem_rsp_data;
-    assign mem_bus_if.rsp_data.tag = mem_rsp_tag; 
-    assign mem_rsp_ready = mem_bus_if.rsp_ready;
-
-    VX_cache #(
-        .INSTANCE_ID    (INSTANCE_ID),
-        .CACHE_SIZE     (CACHE_SIZE),
-        .LINE_SIZE      (LINE_SIZE),
-        .NUM_BANKS      (NUM_BANKS),
-        .NUM_WAYS       (NUM_WAYS),
-        .WORD_SIZE      (WORD_SIZE),
-        .NUM_REQS       (NUM_REQS),
-        .CRSQ_SIZE      (CRSQ_SIZE),
-        .MSHR_SIZE      (MSHR_SIZE),
-        .MRSQ_SIZE      (MRSQ_SIZE),
-        .MREQ_SIZE      (MREQ_SIZE),
-        .TAG_WIDTH      (TAG_WIDTH),
-        .UUID_WIDTH     (UUID_WIDTH),
-        .WRITE_ENABLE   (WRITE_ENABLE),
-        .CORE_OUT_REG   (CORE_OUT_REG),
-        .MEM_OUT_REG    (MEM_OUT_REG)
-    ) cache (
-    `ifdef PERF_ENABLE
-        .cache_perf     (cache_perf),
-    `endif
-        .clk            (clk),
-        .reset          (reset),
-        .core_bus_if    (core_bus_if),
-        .mem_bus_if     (mem_bus_if)
-    );
-
-endmodule

hw/rtl/cache/VX_cache_wrap.sv

@@ -1,494 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_cache_define.vh"
-
-module VX_cache_wrap import VX_gpu_pkg::*; #(
-    parameter `STRING INSTANCE_ID    = "",
-
-    // Number of Word requests per cycle
-    parameter NUM_REQS              = 4,
-
-    // Size of cache in bytes
-    parameter CACHE_SIZE            = 4096, 
-    // Size of line inside a bank in bytes
-    parameter LINE_SIZE             = 64, 
-    // Number of banks
-    parameter NUM_BANKS             = 1,
-    // Number of associative ways
-    parameter NUM_WAYS              = 1,
-    // Size of a word in bytes
-    parameter WORD_SIZE             = 4, 
-
-    // Core Response Queue Size
-    parameter CRSQ_SIZE             = 2,
-    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE             = 8, 
-    // Memory Response Queue Size
-    parameter MRSQ_SIZE             = 0,
-    // Memory Request Queue Size
-    parameter MREQ_SIZE             = 4,
-
-    // Enable cache writeable
-    parameter WRITE_ENABLE          = 1,
-
-    // Request debug identifier
-    parameter UUID_WIDTH            = 0,
-
-    // core request tag size
-    parameter TAG_WIDTH             = UUID_WIDTH + 1,
-
-    // enable bypass for non-cacheable addresses
-    parameter NC_TAG_BIT            = 0,
-    parameter NC_ENABLE             = 0,
-
-    // Force bypass for all requests
-    parameter PASSTHRU              = 0,
-
-    // Core response output register
-    parameter CORE_OUT_REG          = 0,
-
-    // Memory request output register
-    parameter MEM_OUT_REG           = 0
- ) (
-    
-    input wire clk,
-    input wire reset,
-
-    // PERF
-`ifdef PERF_ENABLE
-    output cache_perf_t     cache_perf,
-`endif
-
-    VX_mem_bus_if.slave     core_bus_if [NUM_REQS],
-    VX_mem_bus_if.master    mem_bus_if
-);
-
-    `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter: NUM_BANKS=%d, NUM_REQS=%d", NUM_BANKS, NUM_REQS))    
-    `STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter"))
-
-    localparam MSHR_ADDR_WIDTH  = `LOG2UP(MSHR_SIZE);    
-    localparam CORE_TAG_X_WIDTH = TAG_WIDTH - NC_ENABLE;
-    localparam MEM_TAG_X_WIDTH  = MSHR_ADDR_WIDTH + `CS_BANK_SEL_BITS;
-    localparam MEM_TAG_WIDTH    = PASSTHRU ? (NC_ENABLE ? `CACHE_NC_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH) : 
-                                                          `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH)) : 
-                                             (NC_ENABLE ? `CACHE_NC_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, NUM_REQS, LINE_SIZE, WORD_SIZE, TAG_WIDTH) :
-                                                          `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS));
-
-    localparam NC_BYPASS = (NC_ENABLE || PASSTHRU);
-    localparam DIRECT_PASSTHRU = PASSTHRU && (`CS_WORD_SEL_BITS == 0) && (NUM_REQS == 1);
-
-    wire [NUM_REQS-1:0]                     core_req_valid;
-    wire [NUM_REQS-1:0]                     core_req_rw;
-    wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr;
-    wire [NUM_REQS-1:0][WORD_SIZE-1:0]      core_req_byteen;
-    wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data;
-    wire [NUM_REQS-1:0][TAG_WIDTH-1:0]      core_req_tag;
-    wire [NUM_REQS-1:0]                     core_req_ready;
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        assign core_req_valid[i]  = core_bus_if[i].req_valid;
-        assign core_req_rw[i]     = core_bus_if[i].req_data.rw;
-        assign core_req_addr[i]   = core_bus_if[i].req_data.addr;
-        assign core_req_byteen[i] = core_bus_if[i].req_data.byteen;
-        assign core_req_data[i]   = core_bus_if[i].req_data.data;
-        assign core_req_tag[i]    = core_bus_if[i].req_data.tag;
-        assign core_bus_if[i].req_ready = core_req_ready[i];
-    end
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    // Core response buffering
-    wire [NUM_REQS-1:0]                  core_rsp_valid_s;
-    wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s;
-    wire [NUM_REQS-1:0][TAG_WIDTH-1:0]   core_rsp_tag_s;
-    wire [NUM_REQS-1:0]                  core_rsp_ready_s;
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        
-        `RESET_RELAY (core_rsp_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (`CS_WORD_WIDTH + TAG_WIDTH),
-            .SIZE    ((NC_BYPASS && !DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0),
-            .OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
-        ) core_rsp_buf (
-            .clk       (clk),
-            .reset     (core_rsp_reset),
-            .valid_in  (core_rsp_valid_s[i]),
-            .ready_in  (core_rsp_ready_s[i]),
-            .data_in   ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
-            .data_out  ({core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag}), 
-            .valid_out (core_bus_if[i].rsp_valid),
-            .ready_out (core_bus_if[i].rsp_ready)
-        );
-    end
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    // Memory request buffering
-    wire                             mem_req_valid_s;
-    wire                             mem_req_rw_s;
-    wire [LINE_SIZE-1:0]             mem_req_byteen_s;   
-    wire [`CS_MEM_ADDR_WIDTH-1:0]    mem_req_addr_s;
-    wire [`CS_LINE_WIDTH-1:0]        mem_req_data_s;
-    wire [MEM_TAG_WIDTH-1:0]         mem_req_tag_s;
-    wire                             mem_req_ready_s;
-
-    VX_elastic_buffer #(
-        .DATAW   (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH),
-        .SIZE    ((NC_BYPASS && !DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0),
-        .OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
-    ) mem_req_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (mem_req_valid_s), 
-        .ready_in  (mem_req_ready_s), 
-        .data_in   ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
-        .data_out  ({mem_bus_if.req_data.rw, mem_bus_if.req_data.byteen, mem_bus_if.req_data.addr, mem_bus_if.req_data.data, mem_bus_if.req_data.tag}), 
-        .valid_out (mem_bus_if.req_valid), 
-        .ready_out (mem_bus_if.req_ready)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    // Core request    
-    wire [NUM_REQS-1:0]                     core_req_valid_b;
-    wire [NUM_REQS-1:0]                     core_req_rw_b;
-    wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr_b;
-    wire [NUM_REQS-1:0][WORD_SIZE-1:0]      core_req_byteen_b;
-    wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data_b;
-    wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_req_tag_b;
-    wire [NUM_REQS-1:0]                     core_req_ready_b;
-
-    // Core response
-    wire [NUM_REQS-1:0]                     core_rsp_valid_b;
-    wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_b;
-    wire [NUM_REQS-1:0][CORE_TAG_X_WIDTH-1:0] core_rsp_tag_b;
-    wire [NUM_REQS-1:0]                     core_rsp_ready_b;
-
-    // Memory request
-    wire                            mem_req_valid_b;
-    wire                            mem_req_rw_b;
-    wire [`CS_MEM_ADDR_WIDTH-1:0]   mem_req_addr_b;
-    wire [LINE_SIZE-1:0]            mem_req_byteen_b;
-    wire [`CS_LINE_WIDTH-1:0]       mem_req_data_b;
-    wire [MEM_TAG_X_WIDTH-1:0]      mem_req_tag_b;
-    wire                            mem_req_ready_b;
-    
-    // Memory response
-    wire                            mem_rsp_valid_b;
-    wire [`CS_LINE_WIDTH-1:0]       mem_rsp_data_b;
-    wire [MEM_TAG_X_WIDTH-1:0]      mem_rsp_tag_b;
-    wire                            mem_rsp_ready_b;
-
-    if (NC_BYPASS) begin
-       
-        `RESET_RELAY (nc_bypass_reset, reset);
-
-        VX_cache_bypass #(
-            .NUM_REQS          (NUM_REQS),
-            .NC_TAG_BIT        (NC_TAG_BIT),
-
-            .NC_ENABLE         (NC_ENABLE),
-            .PASSTHRU          (PASSTHRU),
-
-            .CORE_ADDR_WIDTH   (`CS_WORD_ADDR_WIDTH),
-            .CORE_DATA_SIZE    (WORD_SIZE), 
-            .CORE_TAG_IN_WIDTH (TAG_WIDTH),
-                
-            .MEM_ADDR_WIDTH    (`CS_MEM_ADDR_WIDTH),
-            .MEM_DATA_SIZE     (LINE_SIZE),
-            .MEM_TAG_IN_WIDTH  (MEM_TAG_X_WIDTH),
-            .MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH),
-
-            .UUID_WIDTH        (UUID_WIDTH)
-        ) cache_bypass (
-            .clk                (clk),
-            .reset              (nc_bypass_reset),
-
-            // Core request in
-            .core_req_valid_in  (core_req_valid),
-            .core_req_rw_in     (core_req_rw),
-            .core_req_byteen_in (core_req_byteen),
-            .core_req_addr_in   (core_req_addr),
-            .core_req_data_in   (core_req_data), 
-            .core_req_tag_in    (core_req_tag),
-            .core_req_ready_in  (core_req_ready),
-
-            // Core request out
-            .core_req_valid_out (core_req_valid_b),
-            .core_req_rw_out    (core_req_rw_b),
-            .core_req_byteen_out(core_req_byteen_b),
-            .core_req_addr_out  (core_req_addr_b),
-            .core_req_data_out  (core_req_data_b), 
-            .core_req_tag_out   (core_req_tag_b),
-            .core_req_ready_out (core_req_ready_b),
-
-            // Core response in
-            .core_rsp_valid_in  (core_rsp_valid_b),
-            .core_rsp_data_in   (core_rsp_data_b),
-            .core_rsp_tag_in    (core_rsp_tag_b),
-            .core_rsp_ready_in  (core_rsp_ready_b),
-
-            // Core response out
-            .core_rsp_valid_out (core_rsp_valid_s),
-            .core_rsp_data_out  (core_rsp_data_s),
-            .core_rsp_tag_out   (core_rsp_tag_s),
-            .core_rsp_ready_out (core_rsp_ready_s),
-
-            // Memory request in
-            .mem_req_valid_in   (mem_req_valid_b),
-            .mem_req_rw_in      (mem_req_rw_b), 
-            .mem_req_addr_in    (mem_req_addr_b),
-            .mem_req_byteen_in  (mem_req_byteen_b),
-            .mem_req_data_in    (mem_req_data_b),
-            .mem_req_tag_in     (mem_req_tag_b),
-            .mem_req_ready_in   (mem_req_ready_b),
-
-            // Memory request out
-            .mem_req_valid_out  (mem_req_valid_s),
-            .mem_req_addr_out   (mem_req_addr_s),
-            .mem_req_rw_out     (mem_req_rw_s),
-            .mem_req_byteen_out (mem_req_byteen_s),
-            .mem_req_data_out   (mem_req_data_s),
-            .mem_req_tag_out    (mem_req_tag_s),
-            .mem_req_ready_out  (mem_req_ready_s),
-
-            // Memory response in
-            .mem_rsp_valid_in   (mem_bus_if.rsp_valid), 
-            .mem_rsp_data_in    (mem_bus_if.rsp_data.data),
-            .mem_rsp_tag_in     (mem_bus_if.rsp_data.tag),
-            .mem_rsp_ready_in   (mem_bus_if.rsp_ready),
-
-            // Memory response out
-            .mem_rsp_valid_out  (mem_rsp_valid_b), 
-            .mem_rsp_data_out   (mem_rsp_data_b),
-            .mem_rsp_tag_out    (mem_rsp_tag_b),
-            .mem_rsp_ready_out  (mem_rsp_ready_b)
-        );
-    end else begin        
-        assign core_req_valid_b = core_req_valid;
-        assign core_req_rw_b    = core_req_rw;
-        assign core_req_addr_b  = core_req_addr;
-        assign core_req_byteen_b= core_req_byteen;
-        assign core_req_data_b  = core_req_data;
-        assign core_req_tag_b   = core_req_tag;
-        assign core_req_ready   = core_req_ready_b;
-
-        assign core_rsp_valid_s = core_rsp_valid_b;
-        assign core_rsp_data_s  = core_rsp_data_b;
-        assign core_rsp_tag_s   = core_rsp_tag_b;
-        assign core_rsp_ready_b = core_rsp_ready_s;
-
-        assign mem_req_valid_s  = mem_req_valid_b;
-        assign mem_req_addr_s   = mem_req_addr_b;
-        assign mem_req_rw_s     = mem_req_rw_b;
-        assign mem_req_byteen_s = mem_req_byteen_b;
-        assign mem_req_data_s   = mem_req_data_b;
-        assign mem_req_ready_b  = mem_req_ready_s;
-
-        // Add explicit NC=0 flag to the memory request tag
-
-        VX_bits_insert #( 
-            .N   (MEM_TAG_WIDTH-1),
-            .POS (NC_TAG_BIT)
-        ) mem_req_tag_insert (
-            .data_in  (mem_req_tag_b),
-            .sel_in   (1'b0),
-            .data_out (mem_req_tag_s)
-        );
-
-        assign mem_rsp_valid_b = mem_bus_if.rsp_valid;
-        assign mem_rsp_data_b  = mem_bus_if.rsp_data.data;
-        assign mem_bus_if.rsp_ready = mem_rsp_ready_b;
-
-        // Remove NC flag from the memory response tag
-
-        VX_bits_remove #( 
-            .N   (MEM_TAG_WIDTH),
-            .POS (NC_TAG_BIT)
-        ) mem_rsp_tag_remove (
-            .data_in  (mem_bus_if.rsp_data.tag),
-            .data_out (mem_rsp_tag_b)
-        );
-    end 
-
-    if (PASSTHRU != 0) begin
-
-        `UNUSED_VAR (core_req_valid_b)
-        `UNUSED_VAR (core_req_rw_b)
-        `UNUSED_VAR (core_req_addr_b)
-        `UNUSED_VAR (core_req_byteen_b)
-        `UNUSED_VAR (core_req_data_b)
-        `UNUSED_VAR (core_req_tag_b)
-        assign core_req_ready_b = '0;
-
-        assign core_rsp_valid_b = '0;
-        assign core_rsp_data_b  = '0;
-        assign core_rsp_tag_b   = '0;
-        `UNUSED_VAR (core_rsp_ready_b)
-
-        assign mem_req_valid_b  = 0;
-        assign mem_req_addr_b   = '0;
-        assign mem_req_rw_b     = '0;
-        assign mem_req_byteen_b = '0;
-        assign mem_req_data_b   = '0;
-        assign mem_req_tag_b    = '0;
-        `UNUSED_VAR (mem_req_ready_b)
-
-        `UNUSED_VAR (mem_rsp_valid_b)
-        `UNUSED_VAR (mem_rsp_data_b)
-        `UNUSED_VAR (mem_rsp_tag_b)
-        assign mem_rsp_ready_b = 0;
-
-    `ifdef PERF_ENABLE
-        assign cache_perf = '0;
-    `endif
-
-    end else begin
-
-        VX_mem_bus_if #(
-            .DATA_SIZE (WORD_SIZE),
-            .TAG_WIDTH (CORE_TAG_X_WIDTH)
-        ) core_bus_wrap_if[NUM_REQS]();
-
-        VX_mem_bus_if #(
-            .DATA_SIZE (LINE_SIZE), 
-            .TAG_WIDTH (MEM_TAG_X_WIDTH)
-        ) mem_bus_wrap_if();
-
-        for (genvar i = 0; i < NUM_REQS; ++i) begin
-            assign core_bus_wrap_if[i].req_valid  = core_req_valid_b[i];
-            assign core_bus_wrap_if[i].req_data.rw     = core_req_rw_b[i];
-            assign core_bus_wrap_if[i].req_data.addr   = core_req_addr_b[i];
-            assign core_bus_wrap_if[i].req_data.byteen = core_req_byteen_b[i];
-            assign core_bus_wrap_if[i].req_data.data   = core_req_data_b[i];
-            assign core_bus_wrap_if[i].req_data.tag    = core_req_tag_b[i];
-            assign core_req_ready_b[i] = core_bus_wrap_if[i].req_ready;
-        end
-
-        for (genvar i = 0; i < NUM_REQS; ++i) begin
-            assign core_rsp_valid_b[i] = core_bus_wrap_if[i].rsp_valid;
-            assign core_rsp_data_b[i]  = core_bus_wrap_if[i].rsp_data.data;
-            assign core_rsp_tag_b[i]   = core_bus_wrap_if[i].rsp_data.tag;
-            assign core_bus_wrap_if[i].rsp_ready = core_rsp_ready_b[i];
-        end
-
-        assign mem_req_valid_b  = mem_bus_wrap_if.req_valid;
-        assign mem_req_addr_b   = mem_bus_wrap_if.req_data.addr;
-        assign mem_req_rw_b     = mem_bus_wrap_if.req_data.rw;
-        assign mem_req_byteen_b = mem_bus_wrap_if.req_data.byteen;
-        assign mem_req_data_b   = mem_bus_wrap_if.req_data.data;
-        assign mem_req_tag_b    = mem_bus_wrap_if.req_data.tag;
-        assign mem_bus_wrap_if.req_ready = mem_req_ready_b;
-
-        assign mem_bus_wrap_if.rsp_valid = mem_rsp_valid_b;
-        assign mem_bus_wrap_if.rsp_data.data  = mem_rsp_data_b;
-        assign mem_bus_wrap_if.rsp_data.tag   = mem_rsp_tag_b;
-        assign mem_rsp_ready_b = mem_bus_wrap_if.rsp_ready;
-
-        `RESET_RELAY (cache_reset, reset);
-
-        VX_cache #(
-            .INSTANCE_ID  (INSTANCE_ID),
-            .CACHE_SIZE   (CACHE_SIZE),
-            .LINE_SIZE    (LINE_SIZE),
-            .NUM_BANKS    (NUM_BANKS),
-            .NUM_WAYS     (NUM_WAYS),
-            .WORD_SIZE    (WORD_SIZE),
-            .NUM_REQS     (NUM_REQS),
-            .CRSQ_SIZE    (CRSQ_SIZE),
-            .MSHR_SIZE    (MSHR_SIZE),
-            .MRSQ_SIZE    (MRSQ_SIZE),
-            .MREQ_SIZE    (MREQ_SIZE),
-            .WRITE_ENABLE (WRITE_ENABLE),
-            .UUID_WIDTH   (UUID_WIDTH),
-            .TAG_WIDTH    (CORE_TAG_X_WIDTH),
-            .CORE_OUT_REG (NC_BYPASS ? 1 : CORE_OUT_REG),
-            .MEM_OUT_REG  (NC_BYPASS ? 1 : MEM_OUT_REG)
-        ) cache (
-            .clk            (clk),
-            .reset          (cache_reset),
-
-        `ifdef PERF_ENABLE
-            .cache_perf     (cache_perf),
-        `endif
-
-            .core_bus_if    (core_bus_wrap_if),
-            .mem_bus_if     (mem_bus_wrap_if)
-        );
-        
-    end
-
-`ifdef DBG_TRACE_CACHE_BANK
-
-    for (genvar i = 0; i < NUM_REQS; ++i) begin
-        wire [`UP(UUID_WIDTH)-1:0] core_req_uuid;
-        wire [`UP(UUID_WIDTH)-1:0] core_rsp_uuid;
-
-        if (UUID_WIDTH != 0) begin
-            assign core_req_uuid = core_bus_if[i].req_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
-            assign core_rsp_uuid = core_bus_if[i].rsp_data.tag[TAG_WIDTH-1 -: UUID_WIDTH];
-        end else begin
-            assign core_req_uuid = 0;
-            assign core_rsp_uuid = 0;
-        end
-
-        wire core_req_fire = core_bus_if[i].req_valid && core_bus_if[i].req_ready;
-        wire core_rsp_fire = core_bus_if[i].rsp_valid && core_bus_if[i].rsp_ready;
-
-        always @(posedge clk) begin
-            if (core_req_fire) begin
-                if (core_bus_if[i].req_data.rw)
-                    `TRACE(1, ("%d: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_bus_if[i].req_data.byteen, core_bus_if[i].req_data.data, core_req_uuid));
-                else
-                    `TRACE(1, ("%d: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_req_uuid));
-            end
-            if (core_rsp_fire) begin
-                `TRACE(1, ("%d: %s core-rd-rsp: tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, core_bus_if[i].rsp_data.tag, i, core_bus_if[i].rsp_data.data, core_rsp_uuid));
-            end        
-        end
-    end   
-
-    wire [`UP(UUID_WIDTH)-1:0] mem_req_uuid;
-    wire [`UP(UUID_WIDTH)-1:0] mem_rsp_uuid;
-
-    if ((UUID_WIDTH != 0) && (NC_BYPASS != 0)) begin
-        assign mem_req_uuid = mem_bus_if.req_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
-        assign mem_rsp_uuid = mem_bus_if.rsp_data.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
-    end else begin
-        assign mem_req_uuid = 0;
-        assign mem_rsp_uuid = 0;
-    end
-
-    wire mem_req_fire = mem_bus_if.req_valid && mem_bus_if.req_ready;
-    wire mem_rsp_fire = mem_bus_if.rsp_valid && mem_bus_if.rsp_ready;
-
-    always @(posedge clk) begin
-        if (mem_req_fire) begin
-            if (mem_bus_if.req_data.rw)
-                `TRACE(1, ("%d: %s mem-wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", 
-                    $time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_bus_if.req_data.byteen, mem_bus_if.req_data.data, mem_req_uuid));
-            else
-                `TRACE(1, ("%d: %s mem-rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n", 
-                    $time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_req_uuid));
-        end
-        if (mem_rsp_fire) begin
-            `TRACE(1, ("%d: %s mem-rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n", 
-                $time, INSTANCE_ID, mem_bus_if.rsp_data.tag, mem_bus_if.rsp_data.data, mem_rsp_uuid));
-        end
-    end    
-`endif
-
-endmodule

hw/rtl/core/VX_alu_unit.sv

@@ -1,172 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_alu_unit #(
-    parameter CORE_ID = 0
-) (
-    input wire              clk,
-    input wire              reset,
-    
-    // Inputs
-    VX_dispatch_if.slave    dispatch_if [`ISSUE_WIDTH],
-
-    // Outputs
-    VX_commit_if.master     commit_if [`ISSUE_WIDTH],
-    VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS]
-);   
-
-    `UNUSED_PARAM (CORE_ID)
-    localparam BLOCK_SIZE   = `NUM_ALU_BLOCKS;
-    localparam NUM_LANES    = `NUM_ALU_LANES;
-    localparam PID_BITS     = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH    = `UP(PID_BITS);
-    localparam RSP_ARB_DATAW= `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1;
-    localparam RSP_ARB_SIZE = 1 + `EXT_M_ENABLED;
-    localparam PARTIAL_BW   = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `NUM_THREADS);
-
-    VX_execute_if #(
-        .NUM_LANES (NUM_LANES)
-    ) execute_if[BLOCK_SIZE]();
-
-    `RESET_RELAY (dispatch_reset, reset);
-
-    VX_dispatch_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (PARTIAL_BW ? 1 : 0)
-    ) dispatch_unit (
-        .clk        (clk),
-        .reset      (dispatch_reset),
-        .dispatch_if(dispatch_if),
-        .execute_if (execute_if)
-    );
-
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) commit_block_if[BLOCK_SIZE]();
-
-    for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
-
-        wire is_muldiv_op;
-
-        VX_execute_if #(
-            .NUM_LANES (NUM_LANES)
-        ) int_execute_if();
-
-        assign int_execute_if.valid = execute_if[block_idx].valid && ~is_muldiv_op;
-        assign int_execute_if.data = execute_if[block_idx].data;
-
-        VX_commit_if #(
-            .NUM_LANES (NUM_LANES)
-        ) int_commit_if();
-
-        `RESET_RELAY (int_reset, reset);
-
-        VX_int_unit #(
-            .CORE_ID   (CORE_ID),
-            .BLOCK_IDX (block_idx),
-            .NUM_LANES (NUM_LANES)
-        ) int_unit (
-            .clk        (clk),
-            .reset      (int_reset),
-            .execute_if (int_execute_if),
-            .branch_ctl_if (branch_ctl_if[block_idx]),
-            .commit_if  (int_commit_if)
-        );
-
-    `ifdef EXT_M_ENABLE
-
-        assign is_muldiv_op = `INST_ALU_IS_M(execute_if[block_idx].data.op_mod);
-
-        `RESET_RELAY (mdv_reset, reset);
-
-        VX_execute_if #(
-            .NUM_LANES (NUM_LANES)
-        ) mdv_execute_if();
-        
-        assign mdv_execute_if.valid = execute_if[block_idx].valid && is_muldiv_op;
-        assign mdv_execute_if.data = execute_if[block_idx].data;
-
-        VX_commit_if #(
-            .NUM_LANES (NUM_LANES)
-        ) mdv_commit_if();
-
-        VX_muldiv_unit #(
-            .CORE_ID   (CORE_ID),
-            .NUM_LANES (NUM_LANES)
-        ) mdv_unit (
-            .clk        (clk),
-            .reset      (mdv_reset),
-            .execute_if (mdv_execute_if),
-            .commit_if  (mdv_commit_if)
-        );       
-       
-        assign execute_if[block_idx].ready = is_muldiv_op ? mdv_execute_if.ready : int_execute_if.ready;
-
-    `else
-
-        assign is_muldiv_op = 0;
-        assign execute_if[block_idx].ready = int_execute_if.ready;
-
-    `endif
-
-        // send response
-
-        VX_stream_arb #(
-            .NUM_INPUTS (RSP_ARB_SIZE),
-            .DATAW      (RSP_ARB_DATAW),
-            .OUT_REG    (PARTIAL_BW ? 1 : 3)
-        ) rsp_arb (
-            .clk       (clk),
-            .reset     (reset),
-            .valid_in  ({                
-            `ifdef EXT_M_ENABLE
-                mdv_commit_if.valid,
-            `endif
-                int_commit_if.valid
-            }),
-            .ready_in  ({
-            `ifdef EXT_M_ENABLE
-                mdv_commit_if.ready,
-            `endif
-                int_commit_if.ready
-            }),
-            .data_in   ({
-            `ifdef EXT_M_ENABLE
-                mdv_commit_if.data,
-            `endif
-                int_commit_if.data
-            }),
-            .data_out  (commit_block_if[block_idx].data),
-            .valid_out (commit_block_if[block_idx].valid), 
-            .ready_out (commit_block_if[block_idx].ready),            
-            `UNUSED_PIN (sel_out)
-        );
-    end
-
-    `RESET_RELAY (commit_reset, reset);
-
-    VX_gather_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (PARTIAL_BW ? 3 : 0)
-    ) gather_unit (
-        .clk           (clk),
-        .reset         (commit_reset),
-        .commit_in_if  (commit_block_if),
-        .commit_out_if (commit_if)
-    );
-
-endmodule

hw/rtl/core/VX_commit.sv

@@ -1,226 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_commit import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input wire              clk,
-    input wire              reset,
-
-    // inputs
-    VX_commit_if.slave      alu_commit_if [`ISSUE_WIDTH],
-    VX_commit_if.slave      lsu_commit_if [`ISSUE_WIDTH],
-`ifdef EXT_F_ENABLE
-    VX_commit_if.slave      fpu_commit_if [`ISSUE_WIDTH],
-`endif
-    VX_commit_if.slave      sfu_commit_if [`ISSUE_WIDTH],
-
-    // outputs
-    VX_writeback_if.master  writeback_if  [`ISSUE_WIDTH],
-    VX_commit_csr_if.master commit_csr_if,
-    VX_commit_sched_if.master commit_sched_if,
-
-    // simulation helper signals
-    output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `XLEN + 1 + `NR_BITS + `NUM_THREADS * `XLEN + 1 + 1 + 1;
-    localparam COMMIT_SIZEW = `CLOG2(`NUM_THREADS + 1);
-    localparam COMMIT_ALL_SIZEW = COMMIT_SIZEW + `ISSUE_WIDTH - 1;
-
-    // commit arbitration
-
-    VX_commit_if commit_if[`ISSUE_WIDTH]();
-
-    wire [`ISSUE_WIDTH-1:0] commit_fire;
-    wire [`ISSUE_WIDTH-1:0][`NW_WIDTH-1:0] commit_wid;
-    wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] commit_tmask;
-    wire [`ISSUE_WIDTH-1:0] commit_eop;
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-
-        `RESET_RELAY (arb_reset, reset);
-
-        VX_stream_arb #(
-            .NUM_INPUTS (`NUM_EX_UNITS),
-            .DATAW      (DATAW),
-            .ARBITER    ("R"),
-            .OUT_REG    (1)
-        ) commit_arb (
-            .clk       (clk),
-            .reset     (arb_reset),
-            .valid_in  ({            
-                sfu_commit_if[i].valid,
-            `ifdef EXT_F_ENABLE
-                fpu_commit_if[i].valid,
-            `endif
-                alu_commit_if[i].valid,
-                lsu_commit_if[i].valid
-            }),
-            .ready_in  ({           
-                sfu_commit_if[i].ready,
-            `ifdef EXT_F_ENABLE
-                fpu_commit_if[i].ready,
-            `endif
-                alu_commit_if[i].ready,
-                lsu_commit_if[i].ready                
-            }),
-            .data_in   ({
-                sfu_commit_if[i].data,
-            `ifdef EXT_F_ENABLE
-                fpu_commit_if[i].data,
-            `endif
-                alu_commit_if[i].data,
-                lsu_commit_if[i].data       
-            }),
-            .data_out  (commit_if[i].data),
-            .valid_out (commit_if[i].valid),
-            .ready_out (commit_if[i].ready),
-            `UNUSED_PIN (sel_out)
-        );
-
-        assign commit_fire[i] = commit_if[i].valid && commit_if[i].ready;        
-        assign commit_tmask[i]= {`NUM_THREADS{commit_fire[i]}} & commit_if[i].data.tmask;
-        assign commit_wid[i]  = commit_if[i].data.wid;
-        assign commit_eop[i]  = commit_if[i].data.eop;
-    end
-
-    // CSRs update
-    
-    wire [`ISSUE_WIDTH-1:0][COMMIT_SIZEW-1:0] commit_size, commit_size_r;
-    wire [COMMIT_ALL_SIZEW-1:0] commit_size_all_r, commit_size_all_rr;
-    wire commit_fire_any, commit_fire_any_r, commit_fire_any_rr;
-
-    assign commit_fire_any = (| commit_fire);
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        wire [COMMIT_SIZEW-1:0] count;
-        `POP_COUNT(count, commit_tmask[i]);
-        assign commit_size[i] = count;
-    end
-
-    VX_pipe_register #(
-        .DATAW  (1 + `ISSUE_WIDTH * COMMIT_SIZEW),
-        .RESETW (1)
-    ) commit_size_reg1 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (1'b1),
-        .data_in  ({commit_fire_any, commit_size}),
-        .data_out ({commit_fire_any_r, commit_size_r})
-    );
-
-    VX_reduce #(
-        .DATAW_IN (COMMIT_SIZEW),
-        .DATAW_OUT (COMMIT_ALL_SIZEW),
-        .N  (`ISSUE_WIDTH),
-        .OP ("+")
-    ) commit_size_reduce (
-        .data_in  (commit_size_r),
-        .data_out (commit_size_all_r)
-    );
-
-    VX_pipe_register #(
-        .DATAW  (1 + COMMIT_ALL_SIZEW),
-        .RESETW (1)
-    ) commit_size_reg2 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (1'b1),
-        .data_in  ({commit_fire_any_r, commit_size_all_r}),
-        .data_out ({commit_fire_any_rr, commit_size_all_rr})
-    );
-
-    reg [`PERF_CTR_BITS-1:0] instret;
-    always @(posedge clk) begin
-       if (reset) begin
-            instret <= '0;
-        end else begin
-            if (commit_fire_any_rr) begin
-                instret <= instret + `PERF_CTR_BITS'(commit_size_all_rr);
-            end
-        end
-    end
-    assign commit_csr_if.instret = instret;
-
-    // Committed instructions
-
-    wire [`ISSUE_WIDTH-1:0] committed = commit_fire & commit_eop;
-
-    VX_pipe_register #(
-        .DATAW  (`ISSUE_WIDTH * (1 + `NW_WIDTH)),
-        .RESETW (`ISSUE_WIDTH)
-    ) committed_pipe_reg (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (1'b1),
-        .data_in  ({committed, commit_wid}),
-        .data_out ({commit_sched_if.committed, commit_sched_if.committed_wid})
-    );
-
-    // Writeback
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign writeback_if[i].valid     = commit_if[i].valid && commit_if[i].data.wb;
-        assign writeback_if[i].data.uuid = commit_if[i].data.uuid; 
-        assign writeback_if[i].data.wis  = wid_to_wis(commit_if[i].data.wid);
-        assign writeback_if[i].data.PC   = commit_if[i].data.PC; 
-        assign writeback_if[i].data.tmask= commit_if[i].data.tmask; 
-        assign writeback_if[i].data.rd   = commit_if[i].data.rd; 
-        assign writeback_if[i].data.data = commit_if[i].data.data; 
-        assign writeback_if[i].data.sop  = commit_if[i].data.sop; 
-        assign writeback_if[i].data.eop  = commit_if[i].data.eop;
-        assign commit_if[i].ready = 1'b1; // writeback has no backpressure
-    end
-    
-    // simulation helper signal to get RISC-V tests Pass/Fail status
-    reg [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value_r;
-    always @(posedge clk) begin
-        if (writeback_if[0].valid) begin
-            sim_wb_value_r[writeback_if[0].data.rd] <= writeback_if[0].data.data[0];
-        end
-    end
-    assign sim_wb_value = sim_wb_value_r;
-    
-`ifdef DBG_TRACE_CORE_PIPELINE
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        always @(posedge clk) begin
-            if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", alu_commit_if[i].data.uuid));
-            end
-            if (lsu_commit_if[i].valid && lsu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, lsu_commit_if[i].data.wid, lsu_commit_if[i].data.PC, lsu_commit_if[i].data.tmask, lsu_commit_if[i].data.wb, lsu_commit_if[i].data.rd, lsu_commit_if[i].data.sop, lsu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, lsu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", lsu_commit_if[i].data.uuid));
-            end
-        `ifdef EXT_F_ENABLE
-            if (fpu_commit_if[i].valid && fpu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, fpu_commit_if[i].data.wid, fpu_commit_if[i].data.PC, fpu_commit_if[i].data.tmask, fpu_commit_if[i].data.wb, fpu_commit_if[i].data.rd, fpu_commit_if[i].data.sop, fpu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, fpu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", fpu_commit_if[i].data.uuid));
-            end
-        `endif
-            if (sfu_commit_if[i].valid && sfu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=SFU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, sfu_commit_if[i].data.wid, sfu_commit_if[i].data.PC, sfu_commit_if[i].data.tmask, sfu_commit_if[i].data.wb, sfu_commit_if[i].data.rd, sfu_commit_if[i].data.sop, sfu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, sfu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", sfu_commit_if[i].data.uuid));
-            end
-        end
-    end
-`endif
-
-endmodule

hw/rtl/core/VX_core.sv

@@ -1,388 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-`ifdef EXT_F_ENABLE
-`include "VX_fpu_define.vh"
-`endif
-
-module VX_core import VX_gpu_pkg::*; #( 
-    parameter CORE_ID = 0
-) (        
-    `SCOPE_IO_DECL
-    
-    // Clock
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave    mem_perf_if,
-`endif
-
-    VX_dcr_bus_if.slave     dcr_bus_if,
-
-    VX_mem_bus_if.master    dcache_bus_if [DCACHE_NUM_REQS],
-
-    VX_mem_bus_if.master    icache_bus_if,
-
-`ifdef GBAR_ENABLE
-    VX_gbar_bus_if.master   gbar_bus_if,
-`endif
-
-    // simulation helper signals
-    output wire             sim_ebreak,
-    output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
-
-    // Status
-    output wire             busy    //stays 1 when busy, 0 when done (termination) detect the negative edge
-);
-    VX_schedule_if      schedule_if();
-    VX_fetch_if         fetch_if();
-    VX_decode_if        decode_if();
-    VX_sched_csr_if     sched_csr_if();
-    VX_decode_sched_if  decode_sched_if();
-    VX_commit_sched_if  commit_sched_if();
-    VX_commit_csr_if    commit_csr_if();
-    VX_branch_ctl_if    branch_ctl_if[`NUM_ALU_BLOCKS]();
-    VX_warp_ctl_if      warp_ctl_if();    
-    
-    VX_dispatch_if      alu_dispatch_if[`ISSUE_WIDTH]();
-    VX_commit_if        alu_commit_if[`ISSUE_WIDTH]();
-
-    VX_dispatch_if      lsu_dispatch_if[`ISSUE_WIDTH]();
-    VX_commit_if        lsu_commit_if[`ISSUE_WIDTH]();
-`ifdef EXT_F_ENABLE 
-    VX_dispatch_if      fpu_dispatch_if[`ISSUE_WIDTH]();
-    VX_commit_if        fpu_commit_if[`ISSUE_WIDTH]();
-`endif
-    VX_dispatch_if      sfu_dispatch_if[`ISSUE_WIDTH]();
-    VX_commit_if        sfu_commit_if[`ISSUE_WIDTH]();    
-    
-    VX_writeback_if     writeback_if[`ISSUE_WIDTH]();
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (DCACHE_WORD_SIZE), 
-        .TAG_WIDTH (DCACHE_TAG_WIDTH)
-    ) dcache_bus_tmp_if[DCACHE_NUM_REQS]();
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if mem_perf_tmp_if();
-    VX_pipeline_perf_if pipeline_perf_if();    
-
-    assign mem_perf_tmp_if.icache  = mem_perf_if.icache;
-    assign mem_perf_tmp_if.dcache  = mem_perf_if.dcache;
-    assign mem_perf_tmp_if.l2cache = mem_perf_if.l2cache;
-    assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
-    assign mem_perf_tmp_if.mem     = mem_perf_if.mem;
-`endif
-
-    `RESET_RELAY (dcr_data_reset, reset);
-    `RESET_RELAY (schedule_reset, reset);
-    `RESET_RELAY (fetch_reset, reset);
-    `RESET_RELAY (decode_reset, reset);
-    `RESET_RELAY (issue_reset, reset);
-    `RESET_RELAY (execute_reset, reset);
-    `RESET_RELAY (commit_reset, reset);
-
-    base_dcrs_t base_dcrs;
-
-    VX_dcr_data dcr_data (
-        .clk        (clk),
-        .reset      (dcr_data_reset),
-        .dcr_bus_if (dcr_bus_if),
-        .base_dcrs  (base_dcrs)
-    );
-
-    `SCOPE_IO_SWITCH (3)
-
-    VX_schedule #(
-        .CORE_ID (CORE_ID)
-    ) schedule (
-        .clk            (clk),
-        .reset          (schedule_reset),
-
-    `ifdef PERF_ENABLE
-        .perf_schedule_if (pipeline_perf_if.schedule),
-    `endif 
-
-        .base_dcrs      (base_dcrs),  
-
-        .warp_ctl_if    (warp_ctl_if),        
-        .branch_ctl_if  (branch_ctl_if),
-        .decode_sched_if(decode_sched_if),
-        .commit_sched_if(commit_sched_if),
-
-        .schedule_if    (schedule_if),
-    `ifdef GBAR_ENABLE
-        .gbar_bus_if    (gbar_bus_if),
-    `endif
-        .sched_csr_if   (sched_csr_if),        
-
-        .busy           (busy)
-    );
-
-    VX_fetch #(
-        .CORE_ID (CORE_ID)
-    ) fetch (
-        `SCOPE_IO_BIND  (0)
-        .clk            (clk),
-        .reset          (fetch_reset),
-        .icache_bus_if  (icache_bus_if),
-        .schedule_if    (schedule_if),
-        .fetch_if       (fetch_if)
-    );
-
-    VX_decode #(
-        .CORE_ID (CORE_ID)
-    ) decode (
-        .clk            (clk),
-        .reset          (decode_reset),
-        .fetch_if       (fetch_if),
-        .decode_if      (decode_if),
-        .decode_sched_if(decode_sched_if)
-    );
-
-    VX_issue #(
-        .CORE_ID (CORE_ID)
-    ) issue (
-        `SCOPE_IO_BIND  (1)
-
-        .clk            (clk),
-        .reset          (issue_reset),
-
-    `ifdef PERF_ENABLE
-        .perf_issue_if  (pipeline_perf_if.issue),
-    `endif
-
-        .decode_if      (decode_if),
-        .writeback_if   (writeback_if),
-
-        .alu_dispatch_if(alu_dispatch_if),
-        .lsu_dispatch_if(lsu_dispatch_if),
-    `ifdef EXT_F_ENABLE
-        .fpu_dispatch_if(fpu_dispatch_if),
-    `endif
-        .sfu_dispatch_if(sfu_dispatch_if)
-    );
-
-    VX_execute #(
-        .CORE_ID (CORE_ID)
-    ) execute (
-        `SCOPE_IO_BIND  (2)
-        
-        .clk            (clk),
-        .reset          (execute_reset),
-
-        .base_dcrs      (base_dcrs),
-
-    `ifdef PERF_ENABLE
-        .mem_perf_if    (mem_perf_tmp_if),        
-        .pipeline_perf_if(pipeline_perf_if),
-    `endif 
-
-        .dcache_bus_if  (dcache_bus_tmp_if),
-    
-    `ifdef EXT_F_ENABLE
-        .fpu_dispatch_if(fpu_dispatch_if),
-        .fpu_commit_if  (fpu_commit_if),
-    `endif
-
-        .commit_csr_if  (commit_csr_if),
-        .sched_csr_if   (sched_csr_if),
-        
-        .alu_dispatch_if(alu_dispatch_if),
-        .lsu_dispatch_if(lsu_dispatch_if),
-        .sfu_dispatch_if(sfu_dispatch_if),
-
-        .warp_ctl_if    (warp_ctl_if),
-        .branch_ctl_if  (branch_ctl_if),
-
-        .alu_commit_if  (alu_commit_if),
-        .lsu_commit_if  (lsu_commit_if),
-        .sfu_commit_if  (sfu_commit_if),
-
-        .sim_ebreak     (sim_ebreak)
-    );    
-
-    VX_commit #(
-        .CORE_ID (CORE_ID)
-    ) commit (
-        .clk            (clk),
-        .reset          (commit_reset),
-
-        .alu_commit_if  (alu_commit_if),
-        .lsu_commit_if  (lsu_commit_if),
-    `ifdef EXT_F_ENABLE
-        .fpu_commit_if  (fpu_commit_if),
-    `endif
-        .sfu_commit_if  (sfu_commit_if),
-        
-        .writeback_if   (writeback_if),
-        
-        .commit_csr_if  (commit_csr_if),
-        .commit_sched_if(commit_sched_if),
-
-        .sim_wb_value   (sim_wb_value)
-    );
-
-`ifdef SM_ENABLE
-
-    VX_smem_unit #(
-        .CORE_ID (CORE_ID)
-    ) smem_unit (
-        .clk                (clk),
-        .reset              (reset),
-    `ifdef PERF_ENABLE
-        .cache_perf         (mem_perf_tmp_if.smem),
-    `endif
-        .dcache_bus_in_if   (dcache_bus_tmp_if),
-        .dcache_bus_out_if  (dcache_bus_if)
-    );
-
-`else
-
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-        `ASSIGN_VX_MEM_BUS_IF (dcache_bus_if[i], dcache_bus_tmp_if[i]);
-    end
-
-`endif
-
-`ifdef PERF_ENABLE  // expose these perf counter to console using $display, %time; flag: --perf=0?
-
-    wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rd_req_per_cycle;
-    wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_wr_req_per_cycle;
-    wire [`CLOG2(DCACHE_NUM_REQS+1)-1:0] perf_dcache_rsp_per_cycle;    
-
-    wire [1:0] perf_icache_pending_read_cycle;
-    wire [`CLOG2(DCACHE_NUM_REQS+1)+1-1:0] perf_dcache_pending_read_cycle;
-
-    reg [`PERF_CTR_BITS-1:0] perf_icache_pending_reads;
-    reg [`PERF_CTR_BITS-1:0] perf_dcache_pending_reads;
-
-    reg [`PERF_CTR_BITS-1:0] perf_ifetches;
-    reg [`PERF_CTR_BITS-1:0] perf_loads;
-    reg [`PERF_CTR_BITS-1:0] perf_stores;
-
-    wire perf_icache_req_fire = icache_bus_if.req_valid && icache_bus_if.req_ready;
-    wire perf_icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
-
-    wire [DCACHE_NUM_REQS-1:0] perf_dcache_rd_req_fire, perf_dcache_rd_req_fire_r;
-    wire [DCACHE_NUM_REQS-1:0] perf_dcache_wr_req_fire, perf_dcache_wr_req_fire_r;
-    wire [DCACHE_NUM_REQS-1:0] perf_dcache_rsp_fire;
-
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-        assign perf_dcache_rd_req_fire[i] = dcache_bus_if[i].req_valid && dcache_bus_if[i].req_ready && ~dcache_bus_if[i].req_data.rw;
-        assign perf_dcache_wr_req_fire[i] = dcache_bus_if[i].req_valid && dcache_bus_if[i].req_ready && dcache_bus_if[i].req_data.rw;
-        assign perf_dcache_rsp_fire[i] = dcache_bus_if[i].rsp_valid && dcache_bus_if[i].rsp_ready;
-    end
-
-    `BUFFER(perf_dcache_rd_req_fire_r, perf_dcache_rd_req_fire);
-    `BUFFER(perf_dcache_wr_req_fire_r, perf_dcache_wr_req_fire);
-
-    `POP_COUNT(perf_dcache_rd_req_per_cycle, perf_dcache_rd_req_fire_r);
-    `POP_COUNT(perf_dcache_wr_req_per_cycle, perf_dcache_wr_req_fire_r);
-    `POP_COUNT(perf_dcache_rsp_per_cycle, perf_dcache_rsp_fire);
-      
-    assign perf_icache_pending_read_cycle = perf_icache_req_fire - perf_icache_rsp_fire;
-    assign perf_dcache_pending_read_cycle = perf_dcache_rd_req_per_cycle - perf_dcache_rsp_per_cycle;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_icache_pending_reads <= '0;
-            perf_dcache_pending_reads <= '0;
-        end else begin
-            perf_icache_pending_reads <= $signed(perf_icache_pending_reads) + `PERF_CTR_BITS'($signed(perf_icache_pending_read_cycle));
-            perf_dcache_pending_reads <= $signed(perf_dcache_pending_reads) + `PERF_CTR_BITS'($signed(perf_dcache_pending_read_cycle));
-        end
-    end
-    
-    reg [`PERF_CTR_BITS-1:0] perf_icache_lat;
-    reg [`PERF_CTR_BITS-1:0] perf_dcache_lat;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_ifetches   <= '0;
-            perf_loads      <= '0;
-            perf_stores     <= '0;
-            perf_icache_lat <= '0;
-            perf_dcache_lat <= '0;
-        end else begin
-            perf_ifetches   <= perf_ifetches   + `PERF_CTR_BITS'(perf_icache_req_fire);
-            perf_loads      <= perf_loads      + `PERF_CTR_BITS'(perf_dcache_rd_req_per_cycle);
-            perf_stores     <= perf_stores     + `PERF_CTR_BITS'(perf_dcache_wr_req_per_cycle);
-            perf_icache_lat <= perf_icache_lat + perf_icache_pending_reads;
-            perf_dcache_lat <= perf_dcache_lat + perf_dcache_pending_reads;
-        end
-    end
-
-    assign pipeline_perf_if.ifetches = perf_ifetches;
-    assign pipeline_perf_if.loads = perf_loads;
-    assign pipeline_perf_if.stores = perf_stores;
-    assign pipeline_perf_if.load_latency = perf_dcache_lat;
-    assign pipeline_perf_if.ifetch_latency = perf_icache_lat;
-    real instrs = commit_csr_if.instret;
-    real cycles = sched_csr_if.cycles;
-    real icache_lat = perf_icache_lat;
-    real ifetches = perf_ifetches;
-    real dcache_lat = perf_dcache_lat;
-    real loads = perf_loads;
-    real scheduler_idles = pipeline_perf_if.sched_idles;
-    real scheduler_stalls = pipeline_perf_if.sched_stalls;
-    real ibuf_stalls = pipeline_perf_if.ibf_stalls;
-    real scrb_alu_per_core = pipeline_perf_if.units_uses[`EX_ALU];
-    real scrb_fpu_per_core = pipeline_perf_if.units_uses[`EX_FPU];
-    real scrb_lsu_per_core = pipeline_perf_if.units_uses[`EX_LSU];
-    real scrb_sfu_per_core = pipeline_perf_if.units_uses[`EX_SFU];
-    real scrb_tot = scrb_alu_per_core+scrb_fpu_per_core+scrb_lsu_per_core+scrb_sfu_per_core;
-
-    real scrb_wctl_per_core = pipeline_perf_if.sfu_uses[`SFU_WCTL];
-    real scrb_csrs_per_core = pipeline_perf_if.sfu_uses[`SFU_CSRS];
-    real sfu_tot = scrb_wctl_per_core+scrb_csrs_per_core;
-    
-    always @(negedge busy) begin
-        if (!reset) begin
-        $display("====================CORE : %d===================",CORE_ID);
-        $display("time : %t", $time);
-        $display("perf_dcache_rd_req_per_cycle: %d", perf_dcache_rd_req_per_cycle);
-        $display("perf_dcache_wr_req_per_cycle: %d", perf_dcache_wr_req_per_cycle);
-        $display("perf_dcache_rsp_per_cycle: %d", perf_dcache_rsp_per_cycle);
-        $display("perf_icache_pending_read_cycle: %d", perf_icache_pending_read_cycle);
-        $display("perf_dcache_pending_read_cycle: %d", perf_dcache_pending_read_cycle);
-        $display("perf_icache_pending_reads: %d", perf_icache_pending_reads);
-        $display("perf_dcache_pending_reads: %d", perf_dcache_pending_reads);
-        $display("perf_icache_req_fire: %b", perf_icache_req_fire);
-        $display("perf_icache_rsp_fire: %b", perf_icache_rsp_fire);
-        $display("perf_dcache_rd_req_fire: %b", perf_dcache_rd_req_fire);
-        $display("perf_dcache_rd_req_fire_r: %b", perf_dcache_rd_req_fire_r);
-        $display("perf_dcache_wr_req_fire: %b", perf_dcache_wr_req_fire);
-        $display("perf_dcache_wr_req_fire_r: %b", perf_dcache_wr_req_fire_r);
-        $display("perf_dcache_rsp_fire: %b", perf_dcache_rsp_fire);
-
-        $display("Instructions: %d, Cycles: %d, IPC: %f", commit_csr_if.instret, sched_csr_if.cycles, instrs/cycles);
-        $display("scheduler idle: %d (%f)", pipeline_perf_if.sched_idles, scheduler_idles/cycles);
-        $display("scheduler stalls: %d (%f)", pipeline_perf_if.sched_stalls, scheduler_stalls/cycles);
-        $display("ibuffer stalls: %d (%f)",pipeline_perf_if.ibf_stalls, ibuf_stalls/cycles);
-        $display("issue stalls: %d(alu=%f, fpu=%f, lsu=%f, sfu=%f)",pipeline_perf_if.scb_stalls, scrb_alu_per_core/scrb_tot, scrb_fpu_per_core/scrb_tot, scrb_lsu_per_core/scrb_tot, scrb_sfu_per_core/scrb_tot);
-        $display("sfu stalls: %d (scrs=%f, wctl=%f)",pipeline_perf_if.units_uses[`EX_SFU], scrb_csrs_per_core/sfu_tot, scrb_wctl_per_core/sfu_tot);
-        $display("ifetches: %d", perf_ifetches);
-        $display("ifetch latency: %f Cycles", icache_lat/ifetches);
-        $display("loads: %d", perf_loads);
-        $display("load latency: %f Cycles", dcache_lat/loads);
-        $display("stores: %d", perf_stores);
-        end
-    end
-
-`endif
-
-endmodule

hw/rtl/core/VX_core_top.sv

@@ -1,174 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-`ifdef EXT_F_ENABLE
-`include "VX_fpu_define.vh"
-`endif
-
-module VX_core_top import VX_gpu_pkg::*; #( 
-    parameter CORE_ID = 0
-) (  
-    // Clock
-    input wire                              clk,
-    input wire                              reset,
-
-    input wire                              dcr_write_valid,
-    input wire [`VX_DCR_ADDR_WIDTH-1:0]     dcr_write_addr,
-    input wire [`VX_DCR_DATA_WIDTH-1:0]     dcr_write_data,
-
-    output wire [DCACHE_NUM_REQS-1:0]       dcache_req_valid,
-    output wire [DCACHE_NUM_REQS-1:0]       dcache_req_rw,
-    output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] dcache_req_byteen,
-    output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] dcache_req_addr,
-    output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_req_data,
-    output wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_req_tag,
-    input  wire [DCACHE_NUM_REQS-1:0]       dcache_req_ready,
-
-    input wire  [DCACHE_NUM_REQS-1:0]       dcache_rsp_valid,
-    input wire  [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_rsp_data,
-    input wire  [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] dcache_rsp_tag,
-    output wire [DCACHE_NUM_REQS-1:0]       dcache_rsp_ready,
-
-    output wire                             icache_req_valid,
-    output wire                             icache_req_rw,
-    output wire [ICACHE_WORD_SIZE-1:0]      icache_req_byteen,
-    output wire [ICACHE_ADDR_WIDTH-1:0]     icache_req_addr,
-    output wire [ICACHE_WORD_SIZE*8-1:0]    icache_req_data,
-    output wire [ICACHE_TAG_WIDTH-1:0]      icache_req_tag,
-    input  wire                             icache_req_ready,
-
-    input wire                              icache_rsp_valid,
-    input wire  [ICACHE_WORD_SIZE*8-1:0]    icache_rsp_data,
-    input wire  [ICACHE_TAG_WIDTH-1:0]      icache_rsp_tag,
-    output wire                             icache_rsp_ready,
-
-`ifdef GBAR_ENABLE
-    output wire                             gbar_req_valid,
-    output wire [`NB_WIDTH-1:0]             gbar_req_id,
-    output wire [`NC_WIDTH-1:0]             gbar_req_size_m1,    
-    output wire [`NC_WIDTH-1:0]             gbar_req_core_id,
-    input wire                              gbar_req_ready,
-    input wire                              gbar_rsp_valid,
-    input wire [`NB_WIDTH-1:0]              gbar_rsp_id,
-`endif
-
-    // simulation helper signals
-    output wire                             sim_ebreak,
-    output wire [`NUM_REGS-1:0][`XLEN-1:0]  sim_wb_value,
-
-    // Status
-    output wire                             busy
-);
-    
-`ifdef GBAR_ENABLE
-    VX_gbar_bus_if gbar_bus_if();
-
-    assign gbar_req_valid = gbar_bus_if.req_valid;
-    assign gbar_req_id = gbar_bus_if.req_id;
-    assign gbar_req_size_m1 = gbar_bus_if.req_size_m1;   
-    assign gbar_req_core_id =  gbar_bus_if.req_core_id;
-    assign gbar_bus_if.req_ready = gbar_req_ready;
-    assign gbar_bus_if.rsp_valid = gbar_rsp_valid;
-    assign gbar_bus_if.rsp_id = gbar_rsp_id;
-`endif
-
-    VX_dcr_bus_if dcr_bus_if(); 
-
-    assign dcr_bus_if.write_valid = dcr_write_valid;
-    assign dcr_bus_if.write_addr = dcr_write_addr;
-    assign dcr_bus_if.write_data = dcr_write_data;
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (DCACHE_WORD_SIZE),
-        .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
-    ) dcache_bus_if[DCACHE_NUM_REQS]();
-
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-        assign dcache_req_valid[i] = dcache_bus_if[i].req_valid;
-        assign dcache_req_rw[i] = dcache_bus_if[i].req_data.rw;
-        assign dcache_req_byteen[i] = dcache_bus_if[i].req_data.byteen;
-        assign dcache_req_addr[i] = dcache_bus_if[i].req_data.addr;
-        assign dcache_req_data[i] = dcache_bus_if[i].req_data.data;
-        assign dcache_req_tag[i] = dcache_bus_if[i].req_data.tag;
-        assign dcache_bus_if[i].req_ready = dcache_req_ready[i];
-
-        assign dcache_bus_if[i].rsp_valid = dcache_rsp_valid[i];
-        assign dcache_bus_if[i].rsp_data.tag = dcache_rsp_tag[i];
-        assign dcache_bus_if[i].rsp_data.data = dcache_rsp_data[i];
-        assign dcache_rsp_ready[i] = dcache_bus_if[i].rsp_ready;
-    end
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (ICACHE_WORD_SIZE),
-        .TAG_WIDTH (ICACHE_TAG_WIDTH)
-    ) icache_bus_if();
-
-    assign icache_req_valid = icache_bus_if.req_valid;
-    assign icache_req_rw = icache_bus_if.req_data.rw;
-    assign icache_req_byteen = icache_bus_if.req_data.byteen;
-    assign icache_req_addr = icache_bus_if.req_data.addr;
-    assign icache_req_data = icache_bus_if.req_data.data;
-    assign icache_req_tag = icache_bus_if.req_data.tag;
-    assign icache_bus_if.req_ready = icache_req_ready;
-
-    assign icache_bus_if.rsp_valid = icache_rsp_valid;
-    assign icache_bus_if.rsp_data.tag = icache_rsp_tag;
-    assign icache_bus_if.rsp_data.data = icache_rsp_data;
-    assign icache_rsp_ready = icache_bus_if.rsp_ready;
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if mem_perf_if();    
-    assign mem_perf_if.icache  = '0;
-    assign mem_perf_if.dcache  = '0;
-    assign mem_perf_if.l2cache = '0;
-    assign mem_perf_if.l3cache = '0;
-    assign mem_perf_if.smem    = '0;
-    assign mem_perf_if.mem     = '0;
-`endif
-
-`ifdef SCOPE
-    wire [0:0] scope_reset_w = 1'b0; 
-    wire [0:0] scope_bus_in_w = 1'b0; 
-    wire [0:0] scope_bus_out_w;
-    `UNUSED_VAR (scope_bus_out_w)
-`endif
-
-    VX_core #(
-        .CORE_ID (CORE_ID)
-    ) core (
-        `SCOPE_IO_BIND (0)
-        .clk            (clk),
-        .reset          (reset),
-        
-    `ifdef PERF_ENABLE
-        .mem_perf_if    (mem_perf_if),
-    `endif
-        
-        .dcr_bus_if     (dcr_bus_if),
-
-        .dcache_bus_if  (dcache_bus_if),
-
-        .icache_bus_if  (icache_bus_if),
-
-    `ifdef GBAR_ENABLE
-        .gbar_bus_if    (gbar_bus_if),
-    `endif
-
-        .sim_ebreak     (sim_ebreak),
-        .sim_wb_value   (sim_wb_value),
-        .busy           (busy)
-    );
-
-endmodule

hw/rtl/core/VX_csr_data.sv

@@ -1,313 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-`ifdef EXT_F_ENABLE
-`include "VX_fpu_define.vh"
-`endif
-
-module VX_csr_data
-import VX_gpu_pkg::*;
-`ifdef EXT_F_ENABLE
-import VX_fpu_pkg::*;
-`endif
-#(
-    parameter CORE_ID = 0
-) (
-    input wire                          clk,
-    input wire                          reset,
-
-    input base_dcrs_t                   base_dcrs,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave                mem_perf_if,
-    VX_pipeline_perf_if.slave           pipeline_perf_if,
-`endif
-
-    VX_commit_csr_if.slave              commit_csr_if,
-
-`ifdef EXT_F_ENABLE
-    VX_fpu_to_csr_if.slave              fpu_to_csr_if [`NUM_FPU_BLOCKS],
-`endif
-
-    input wire [`PERF_CTR_BITS-1:0]     cycles,
-    input wire [`NUM_WARPS-1:0]         active_warps,
-    input wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks,
-
-    input wire                          read_enable,
-    input wire [`UUID_WIDTH-1:0]        read_uuid,
-    input wire [`NW_WIDTH-1:0]          read_wid,
-    input wire [`VX_CSR_ADDR_BITS-1:0]  read_addr,
-    output wire [31:0]                  read_data_ro,
-    output wire [31:0]                  read_data_rw,
-
-    input wire                          write_enable, 
-    input wire [`UUID_WIDTH-1:0]        write_uuid,
-    input wire [`NW_WIDTH-1:0]          write_wid,
-    input wire [`VX_CSR_ADDR_BITS-1:0]  write_addr,
-    input wire [31:0]                   write_data
-);
-
-    `UNUSED_VAR (reset)
-    `UNUSED_VAR (write_wid)
-    `UNUSED_VAR (write_data)
-
-    // CSRs Write /////////////////////////////////////////////////////////////
-
-`ifdef EXT_F_ENABLE    
-    reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr, fcsr_n;
-    wire [`NUM_FPU_BLOCKS-1:0]              fpu_write_enable;
-    wire [`NUM_FPU_BLOCKS-1:0][`NW_WIDTH-1:0] fpu_write_wid;
-    fflags_t [`NUM_FPU_BLOCKS-1:0]          fpu_write_fflags;
-    for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
-        assign fpu_write_enable[i] = fpu_to_csr_if[i].write_enable;
-        assign fpu_write_wid[i]    = fpu_to_csr_if[i].write_wid;
-        assign fpu_write_fflags[i] = fpu_to_csr_if[i].write_fflags;
-    end
-    always @(*) begin
-        fcsr_n = fcsr;
-        for (integer i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
-            if (fpu_write_enable[i]) begin
-                fcsr_n[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] = fcsr[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0]
-                                                             | fpu_write_fflags[i];
-            end
-        end            
-        if (write_enable) begin
-            case (write_addr)
-                `VX_CSR_FFLAGS: fcsr_n[write_wid][`FP_FLAGS_BITS-1:0] = write_data[`FP_FLAGS_BITS-1:0];
-                `VX_CSR_FRM:    fcsr_n[write_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS] = write_data[`INST_FRM_BITS-1:0];
-                `VX_CSR_FCSR:   fcsr_n[write_wid] = write_data[`FP_FLAGS_BITS+`INST_FRM_BITS-1:0];
-            default:;
-            endcase
-        end
-    end
-    
-    for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
-        assign fpu_to_csr_if[i].read_frm = fcsr[fpu_to_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
-    end
-
-    always @(posedge clk) begin
-        if (reset) begin
-            fcsr <= '0;
-        end else begin
-            fcsr <= fcsr_n;
-        end
-    end
-`endif
-
-    always @(posedge clk) begin
-        if (write_enable) begin
-            case (write_addr)
-            `ifdef EXT_F_ENABLE
-                `VX_CSR_FFLAGS,
-                `VX_CSR_FRM,
-                `VX_CSR_FCSR,
-            `endif
-                `VX_CSR_SATP,
-                `VX_CSR_MSTATUS,
-                `VX_CSR_MNSTATUS,
-                `VX_CSR_MEDELEG,
-                `VX_CSR_MIDELEG,
-                `VX_CSR_MIE,
-                `VX_CSR_MTVEC,
-                `VX_CSR_MEPC,
-                `VX_CSR_PMPCFG0,
-                `VX_CSR_PMPADDR0: /* do nothing!*/;
-                default: begin
-                    `ASSERT(0, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
-                end
-            endcase
-        end
-    end
-
-    // CSRs read //////////////////////////////////////////////////////////////
-
-    reg [31:0] read_data_ro_r;
-    reg [31:0] read_data_rw_r;
-    reg read_addr_valid_r;
-
-    always @(*) begin
-        read_data_ro_r    = '0;
-        read_data_rw_r    = '0;
-        read_addr_valid_r = 1;
-        case (read_addr)            
-            `VX_CSR_MVENDORID  : read_data_ro_r = 32'(`VENDOR_ID);
-            `VX_CSR_MARCHID    : read_data_ro_r = 32'(`ARCHITECTURE_ID);
-            `VX_CSR_MIMPID     : read_data_ro_r = 32'(`IMPLEMENTATION_ID);
-            `VX_CSR_MISA       : read_data_ro_r = (((`CLOG2(`XLEN)-4) << (`XLEN-2)) | `MISA_STD);
-        `ifdef EXT_F_ENABLE
-            `VX_CSR_FFLAGS     : read_data_rw_r = 32'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
-            `VX_CSR_FRM        : read_data_rw_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
-            `VX_CSR_FCSR       : read_data_rw_r = 32'(fcsr[read_wid]);
-        `endif
-            `VX_CSR_WARP_ID    : read_data_ro_r = 32'(read_wid);
-            `VX_CSR_CORE_ID    : read_data_ro_r = 32'(CORE_ID);
-            `VX_CSR_THREAD_MASK: read_data_ro_r = 32'(thread_masks[read_wid]);
-            `VX_CSR_WARP_MASK  : read_data_ro_r = 32'(active_warps);
-            `VX_CSR_NUM_THREADS: read_data_ro_r = 32'(`NUM_THREADS);
-            `VX_CSR_NUM_WARPS  : read_data_ro_r = 32'(`NUM_WARPS);
-            `VX_CSR_NUM_CORES  : read_data_ro_r = 32'(`NUM_CORES * `NUM_CLUSTERS);           
-            `VX_CSR_MCYCLE     : read_data_ro_r = 32'(cycles[31:0]);
-            `VX_CSR_MCYCLE_H   : read_data_ro_r = 32'(cycles[`PERF_CTR_BITS-1:32]);
-            `VX_CSR_MPM_RESERVED : read_data_ro_r = 'x;
-            `VX_CSR_MPM_RESERVED_H : read_data_ro_r = 'x;  
-            `VX_CSR_MINSTRET   : read_data_ro_r = 32'(commit_csr_if.instret[31:0]);
-            `VX_CSR_MINSTRET_H : read_data_ro_r = 32'(commit_csr_if.instret[`PERF_CTR_BITS-1:32]);       
-            
-            `VX_CSR_SATP,
-            `VX_CSR_MSTATUS,
-            `VX_CSR_MNSTATUS,
-            `VX_CSR_MEDELEG,
-            `VX_CSR_MIDELEG,
-            `VX_CSR_MIE,
-            `VX_CSR_MTVEC,
-            `VX_CSR_MEPC,
-            `VX_CSR_PMPCFG0,
-            `VX_CSR_PMPADDR0   : read_data_ro_r = 32'(0);
-
-            default: begin
-                read_addr_valid_r = 0;
-                if ((read_addr >= `VX_CSR_MPM_USER   && read_addr < (`VX_CSR_MPM_USER + 32))
-                 || (read_addr >= `VX_CSR_MPM_USER_H && read_addr < (`VX_CSR_MPM_USER_H + 32))) begin
-                    read_addr_valid_r = 1;
-                `ifdef PERF_ENABLE
-                    case (base_dcrs.mpm_class)
-                    `VX_DCR_MPM_CLASS_CORE: begin
-                        case (read_addr)
-                        // PERF: pipeline
-                        `VX_CSR_MPM_SCHED_ID        : read_data_ro_r = pipeline_perf_if.sched_idles[31:0];
-                        `VX_CSR_MPM_SCHED_ID_H      : read_data_ro_r = 32'(pipeline_perf_if.sched_idles[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SCHED_ST        : read_data_ro_r = pipeline_perf_if.sched_stalls[31:0];
-                        `VX_CSR_MPM_SCHED_ST_H      : read_data_ro_r = 32'(pipeline_perf_if.sched_stalls[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_IBUF_ST         : read_data_ro_r = pipeline_perf_if.ibf_stalls[31:0];
-                        `VX_CSR_MPM_IBUF_ST_H       : read_data_ro_r = 32'(pipeline_perf_if.ibf_stalls[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SCRB_ST         : read_data_ro_r = pipeline_perf_if.scb_stalls[31:0];
-                        `VX_CSR_MPM_SCRB_ST_H       : read_data_ro_r = 32'(pipeline_perf_if.scb_stalls[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SCRB_ALU        : read_data_ro_r = pipeline_perf_if.units_uses[`EX_ALU][31:0];
-                        `VX_CSR_MPM_SCRB_ALU_H      : read_data_ro_r = 32'(pipeline_perf_if.units_uses[`EX_ALU][`PERF_CTR_BITS-1:32]);
-                    `ifdef EXT_F_ENABLE
-                        `VX_CSR_MPM_SCRB_FPU        : read_data_ro_r = pipeline_perf_if.units_uses[`EX_FPU][31:0];
-                        `VX_CSR_MPM_SCRB_FPU_H      : read_data_ro_r = 32'(pipeline_perf_if.units_uses[`EX_FPU][`PERF_CTR_BITS-1:32]);
-                    `else
-                        `VX_CSR_MPM_SCRB_FPU        : read_data_ro_r = '0;
-                        `VX_CSR_MPM_SCRB_FPU_H      : read_data_ro_r = '0;
-                    `endif
-                        `VX_CSR_MPM_SCRB_LSU        : read_data_ro_r = pipeline_perf_if.units_uses[`EX_LSU][31:0];
-                        `VX_CSR_MPM_SCRB_LSU_H      : read_data_ro_r = 32'(pipeline_perf_if.units_uses[`EX_LSU][`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SCRB_SFU        : read_data_ro_r = pipeline_perf_if.units_uses[`EX_SFU][31:0];
-                        `VX_CSR_MPM_SCRB_SFU_H      : read_data_ro_r = 32'(pipeline_perf_if.units_uses[`EX_SFU][`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SCRB_CSRS       : read_data_ro_r = pipeline_perf_if.sfu_uses[`SFU_CSRS][31:0];
-                        `VX_CSR_MPM_SCRB_CSRS_H     : read_data_ro_r = 32'(pipeline_perf_if.sfu_uses[`SFU_CSRS][`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SCRB_WCTL       : read_data_ro_r = pipeline_perf_if.sfu_uses[`SFU_WCTL][31:0];
-                        `VX_CSR_MPM_SCRB_WCTL_H     : read_data_ro_r = 32'(pipeline_perf_if.sfu_uses[`SFU_WCTL][`PERF_CTR_BITS-1:32]);
-                        // PERF: memory
-                        `VX_CSR_MPM_IFETCHES        : read_data_ro_r = pipeline_perf_if.ifetches[31:0];
-                        `VX_CSR_MPM_IFETCHES_H      : read_data_ro_r = 32'(pipeline_perf_if.ifetches[`PERF_CTR_BITS-1:32]); 
-                        `VX_CSR_MPM_LOADS           : read_data_ro_r = pipeline_perf_if.loads[31:0];
-                        `VX_CSR_MPM_LOADS_H         : read_data_ro_r = 32'(pipeline_perf_if.loads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_STORES          : read_data_ro_r = pipeline_perf_if.stores[31:0];
-                        `VX_CSR_MPM_STORES_H        : read_data_ro_r = 32'(pipeline_perf_if.stores[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_IFETCH_LT       : read_data_ro_r = pipeline_perf_if.ifetch_latency[31:0];
-                        `VX_CSR_MPM_IFETCH_LT_H     : read_data_ro_r = 32'(pipeline_perf_if.ifetch_latency[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_LOAD_LT         : read_data_ro_r = pipeline_perf_if.load_latency[31:0];
-                        `VX_CSR_MPM_LOAD_LT_H       : read_data_ro_r = 32'(pipeline_perf_if.load_latency[`PERF_CTR_BITS-1:32]);            
-                        default:;
-                        endcase
-                    end
-                    `VX_DCR_MPM_CLASS_MEM: begin
-                        case (read_addr)
-                        // PERF: icache
-                        `VX_CSR_MPM_ICACHE_READS    : read_data_ro_r = mem_perf_if.icache.reads[31:0];
-                        `VX_CSR_MPM_ICACHE_READS_H  : read_data_ro_r = 32'(mem_perf_if.icache.reads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_ICACHE_MISS_R   : read_data_ro_r = mem_perf_if.icache.read_misses[31:0];
-                        `VX_CSR_MPM_ICACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.icache.read_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_ICACHE_MSHR_ST  : read_data_ro_r = mem_perf_if.icache.mshr_stalls[31:0];
-                        `VX_CSR_MPM_ICACHE_MSHR_ST_H: read_data_ro_r = 32'(mem_perf_if.icache.mshr_stalls[`PERF_CTR_BITS-1:32]);
-                        // PERF: dcache
-                        `VX_CSR_MPM_DCACHE_READS    : read_data_ro_r = mem_perf_if.dcache.reads[31:0];
-                        `VX_CSR_MPM_DCACHE_READS_H  : read_data_ro_r = 32'(mem_perf_if.dcache.reads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_DCACHE_WRITES   : read_data_ro_r = mem_perf_if.dcache.writes[31:0];
-                        `VX_CSR_MPM_DCACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.dcache.writes[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_DCACHE_MISS_R   : read_data_ro_r = mem_perf_if.dcache.read_misses[31:0];
-                        `VX_CSR_MPM_DCACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.dcache.read_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_DCACHE_MISS_W   : read_data_ro_r = mem_perf_if.dcache.write_misses[31:0];
-                        `VX_CSR_MPM_DCACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.dcache.write_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_DCACHE_BANK_ST  : read_data_ro_r = mem_perf_if.dcache.bank_stalls[31:0];
-                        `VX_CSR_MPM_DCACHE_BANK_ST_H: read_data_ro_r = 32'(mem_perf_if.dcache.bank_stalls[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_DCACHE_MSHR_ST  : read_data_ro_r = mem_perf_if.dcache.mshr_stalls[31:0];
-                        `VX_CSR_MPM_DCACHE_MSHR_ST_H: read_data_ro_r = 32'(mem_perf_if.dcache.mshr_stalls[`PERF_CTR_BITS-1:32]);
-                        // PERF: smem          
-                        `VX_CSR_MPM_SMEM_READS      : read_data_ro_r = mem_perf_if.smem.reads[31:0];
-                        `VX_CSR_MPM_SMEM_READS_H    : read_data_ro_r = 32'(mem_perf_if.smem.reads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SMEM_WRITES     : read_data_ro_r = mem_perf_if.smem.writes[31:0];
-                        `VX_CSR_MPM_SMEM_WRITES_H   : read_data_ro_r = 32'(mem_perf_if.smem.writes[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_SMEM_BANK_ST    : read_data_ro_r = mem_perf_if.smem.bank_stalls[31:0];
-                        `VX_CSR_MPM_SMEM_BANK_ST_H  : read_data_ro_r = 32'(mem_perf_if.smem.bank_stalls[`PERF_CTR_BITS-1:32]);
-                        // PERF: l2cache                        
-                        `VX_CSR_MPM_L2CACHE_READS   : read_data_ro_r = mem_perf_if.l2cache.reads[31:0];
-                        `VX_CSR_MPM_L2CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l2cache.reads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L2CACHE_WRITES  : read_data_ro_r = mem_perf_if.l2cache.writes[31:0];
-                        `VX_CSR_MPM_L2CACHE_WRITES_H: read_data_ro_r = 32'(mem_perf_if.l2cache.writes[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L2CACHE_MISS_R  : read_data_ro_r = mem_perf_if.l2cache.read_misses[31:0];
-                        `VX_CSR_MPM_L2CACHE_MISS_R_H: read_data_ro_r = 32'(mem_perf_if.l2cache.read_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L2CACHE_MISS_W  : read_data_ro_r = mem_perf_if.l2cache.write_misses[31:0];
-                        `VX_CSR_MPM_L2CACHE_MISS_W_H: read_data_ro_r = 32'(mem_perf_if.l2cache.write_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L2CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l2cache.bank_stalls[31:0];
-                        `VX_CSR_MPM_L2CACHE_BANK_ST_H: read_data_ro_r = 32'(mem_perf_if.l2cache.bank_stalls[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L2CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l2cache.mshr_stalls[31:0];
-                        `VX_CSR_MPM_L2CACHE_MSHR_ST_H: read_data_ro_r = 32'(mem_perf_if.l2cache.mshr_stalls[`PERF_CTR_BITS-1:32]);      
-                        // PERF: l3cache
-                        `VX_CSR_MPM_L3CACHE_READS   : read_data_ro_r = mem_perf_if.l3cache.reads[31:0];
-                        `VX_CSR_MPM_L3CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l3cache.reads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L3CACHE_WRITES  : read_data_ro_r = mem_perf_if.l3cache.writes[31:0];
-                        `VX_CSR_MPM_L3CACHE_WRITES_H: read_data_ro_r = 32'(mem_perf_if.l3cache.writes[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L3CACHE_MISS_R  : read_data_ro_r = mem_perf_if.l3cache.read_misses[31:0];
-                        `VX_CSR_MPM_L3CACHE_MISS_R_H: read_data_ro_r = 32'(mem_perf_if.l3cache.read_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L3CACHE_MISS_W  : read_data_ro_r = mem_perf_if.l3cache.write_misses[31:0];
-                        `VX_CSR_MPM_L3CACHE_MISS_W_H: read_data_ro_r = 32'(mem_perf_if.l3cache.write_misses[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L3CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l3cache.bank_stalls[31:0];
-                        `VX_CSR_MPM_L3CACHE_BANK_ST_H: read_data_ro_r = 32'(mem_perf_if.l3cache.bank_stalls[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_L3CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l3cache.mshr_stalls[31:0];
-                        `VX_CSR_MPM_L3CACHE_MSHR_ST_H: read_data_ro_r = 32'(mem_perf_if.l3cache.mshr_stalls[`PERF_CTR_BITS-1:32]); 
-                        // PERF: memory
-                        `VX_CSR_MPM_MEM_READS       : read_data_ro_r = mem_perf_if.mem.reads[31:0];
-                        `VX_CSR_MPM_MEM_READS_H     : read_data_ro_r = 32'(mem_perf_if.mem.reads[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_MEM_WRITES      : read_data_ro_r = mem_perf_if.mem.writes[31:0];
-                        `VX_CSR_MPM_MEM_WRITES_H    : read_data_ro_r = 32'(mem_perf_if.mem.writes[`PERF_CTR_BITS-1:32]);
-                        `VX_CSR_MPM_MEM_LT          : read_data_ro_r = mem_perf_if.mem.latency[31:0];
-                        `VX_CSR_MPM_MEM_LT_H        : read_data_ro_r = 32'(mem_perf_if.mem.latency[`PERF_CTR_BITS-1:32]);     
-                        default:;
-                        endcase
-                    end
-                    default:;
-                    endcase
-                `endif
-                end
-            end
-        endcase
-    end
-
-    assign read_data_ro = read_data_ro_r;
-    assign read_data_rw = read_data_rw_r;
-
-    `UNUSED_VAR (base_dcrs)
-
-    `RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid))
-
-`ifdef PERF_ENABLE
-    `UNUSED_VAR (mem_perf_if.icache);
-    `UNUSED_VAR (mem_perf_if.smem);
-`endif
-
-endmodule

hw/rtl/core/VX_csr_unit.sv

@@ -1,179 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_csr_unit import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0,
-    parameter NUM_LANES = 1
-) (
-    input wire                  clk,
-    input wire                  reset,
-
-    input base_dcrs_t           base_dcrs,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave        mem_perf_if,
-    VX_pipeline_perf_if.slave   pipeline_perf_if,
-`endif
-    
-`ifdef EXT_F_ENABLE
-    VX_fpu_to_csr_if.slave      fpu_to_csr_if [`NUM_FPU_BLOCKS],
-`endif
-
-    VX_commit_csr_if.slave      commit_csr_if,
-    VX_sched_csr_if.slave       sched_csr_if,
-    VX_execute_if.slave         execute_if,
-    VX_commit_if.master         commit_if
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam PID_BITS   = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH  = `UP(PID_BITS);
-    localparam DATAW      = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * 32 + PID_WIDTH + 1 + 1;
-
-    `UNUSED_VAR (execute_if.data.rs3_data)
-    
-    reg [NUM_LANES-1:0][31:0]   csr_read_data;
-    reg  [31:0]                 csr_write_data;
-    wire [31:0]                 csr_read_data_ro, csr_read_data_rw;
-    wire [31:0]                 csr_req_data;
-    reg                         csr_rd_enable;
-    wire                        csr_wr_enable;
-    wire                        csr_req_ready;
-
-    // wait for all pending instructions to complete
-    assign sched_csr_if.alm_empty_wid = execute_if.data.wid;
-    wire no_pending_instr = sched_csr_if.alm_empty;
-    
-    wire csr_req_valid = execute_if.valid && no_pending_instr;
-    assign execute_if.ready = csr_req_ready && no_pending_instr;
-
-    wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.imm[`VX_CSR_ADDR_BITS-1:0];
-    wire [`NRI_BITS-1:0] csr_imm = execute_if.data.imm[`VX_CSR_ADDR_BITS +: `NRI_BITS];
-
-    wire [NUM_LANES-1:0][31:0] rs1_data;
-    `UNUSED_VAR (rs1_data)
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign rs1_data[i] = execute_if.data.rs1_data[i][31:0];
-    end
-
-    wire csr_write_enable = (execute_if.data.op_type == `INST_SFU_CSRRW);
-
-    VX_csr_data #(
-        .CORE_ID (CORE_ID)
-    ) csr_data (
-        .clk            (clk),
-        .reset          (reset),
-
-        .base_dcrs      (base_dcrs),
-
-    `ifdef PERF_ENABLE
-        .mem_perf_if    (mem_perf_if),
-        .pipeline_perf_if(pipeline_perf_if),
-    `endif
-
-        .commit_csr_if  (commit_csr_if),
-        .cycles         (sched_csr_if.cycles),
-        .active_warps   (sched_csr_if.active_warps),
-        .thread_masks   (sched_csr_if.thread_masks),
-    
-    `ifdef EXT_F_ENABLE
-        .fpu_to_csr_if  (fpu_to_csr_if), 
-    `endif    
-
-        .read_enable    (csr_req_valid && csr_rd_enable),
-        .read_uuid      (execute_if.data.uuid),
-        .read_wid       (execute_if.data.wid),        
-        .read_addr      (csr_addr),
-        .read_data_ro   (csr_read_data_ro),
-        .read_data_rw   (csr_read_data_rw),
-
-        .write_enable   (csr_req_valid && csr_wr_enable),
-        .write_uuid     (execute_if.data.uuid),
-        .write_wid      (execute_if.data.wid),
-        .write_addr     (csr_addr),
-        .write_data     (csr_write_data)
-    );
-
-    // CSR read
-
-    wire [NUM_LANES-1:0][31:0] wtid, gtid;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        if (PID_BITS != 0) begin
-            assign wtid[i] = 32'(execute_if.data.pid * NUM_LANES + i);
-        end else begin
-            assign wtid[i] = 32'(i);
-        end
-        assign gtid[i] = (32'(CORE_ID) << (`NW_BITS + `NT_BITS)) + (32'(execute_if.data.wid) << `NT_BITS) + wtid[i];
-    end  
-
-    always @(*) begin
-        csr_rd_enable = 0;
-        case (csr_addr)
-        `VX_CSR_THREAD_ID : csr_read_data = wtid;
-        `VX_CSR_MHARTID   : csr_read_data = gtid;
-        default : begin
-            csr_read_data = {NUM_LANES{csr_read_data_ro | csr_read_data_rw}};
-            csr_rd_enable = 1;
-        end
-        endcase
-    end
-
-    // CSR write
-
-    assign csr_req_data = execute_if.data.use_imm ? 32'(csr_imm) : rs1_data[0];
-
-    assign csr_wr_enable = (csr_write_enable || (| csr_req_data));
-
-    always @(*) begin
-        case (execute_if.data.op_type)
-            `INST_SFU_CSRRW: begin
-                csr_write_data = csr_req_data;
-            end
-            `INST_SFU_CSRRS: begin
-                csr_write_data = csr_read_data_rw | csr_req_data;
-            end
-            //`INST_SFU_CSRRC
-            default: begin
-                csr_write_data = csr_read_data_rw & ~csr_req_data;
-            end
-        endcase
-    end
-
-    // unlock the warp
-    assign sched_csr_if.unlock_warp = csr_req_valid && csr_req_ready && execute_if.data.eop;
-    assign sched_csr_if.unlock_wid = execute_if.data.wid;
-
-    // send response
-    wire [NUM_LANES-1:0][31:0] csr_commit_data;
-
-    VX_elastic_buffer #(
-        .DATAW (DATAW),
-        .SIZE  (2)
-    ) rsp_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (csr_req_valid),
-        .ready_in  (csr_req_ready),
-        .data_in   ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, csr_read_data, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}),
-        .data_out  ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, csr_commit_data, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop}),
-        .valid_out (commit_if.valid),
-        .ready_out (commit_if.ready)
-    );
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign commit_if.data.data[i] = `XLEN'(csr_commit_data[i]);
-    end
-
-endmodule

hw/rtl/core/VX_dcr_data.sv

@@ -1,57 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-`include "VX_trace.vh"
-
-module VX_dcr_data import VX_gpu_pkg::*; (
-    input wire              clk,
-    input wire              reset,
-
-    // Inputs
-    VX_dcr_bus_if.slave     dcr_bus_if,
-
-    // Outputs
-    output base_dcrs_t      base_dcrs
-);
-
-    `UNUSED_VAR (reset)
-
-    base_dcrs_t dcrs;
-
-    always @(posedge clk) begin
-       if (dcr_bus_if.write_valid) begin
-            case (dcr_bus_if.write_addr)
-            `VX_DCR_BASE_STARTUP_ADDR0 : dcrs.startup_addr[31:0] <= dcr_bus_if.write_data;
-        `ifdef XLEN_64
-            `VX_DCR_BASE_STARTUP_ADDR1 : dcrs.startup_addr[63:32] <= dcr_bus_if.write_data;
-        `endif
-            `VX_DCR_BASE_MPM_CLASS : dcrs.mpm_class <= dcr_bus_if.write_data[7:0];
-            default:;
-            endcase
-        end
-    end
-
-    assign base_dcrs = dcrs;
-
-`ifdef DBG_TRACE_CORE_PIPELINE
-    always @(posedge clk) begin
-        if (dcr_bus_if.write_valid) begin
-            `TRACE(1, ("%d: base-dcr: state=", $time));
-            trace_base_dcr(1, dcr_bus_if.write_addr);
-            `TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data));
-        end
-    end
-`endif
-
-endmodule

hw/rtl/core/VX_decode.sv

@@ -1,553 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-`include "VX_trace.vh"
-
-`ifdef EXT_F_ENABLE
-    `define USED_IREG(x) \
-        x``_r = {1'b0, ``x}; \
-        use_``x = 1
-
-    `define USED_FREG(x) \
-        x``_r = {1'b1, ``x}; \
-        use_``x = 1
-`else
-    `define USED_IREG(x) \
-        x``_r = ``x; \
-        use_``x = 1
-`endif
-
-module VX_decode  #(
-    parameter CORE_ID = 0
-) (
-    input wire              clk,
-    input wire              reset,
-
-    // inputs
-    VX_fetch_if.slave       fetch_if,
-
-    // outputs      
-    VX_decode_if.master     decode_if,
-    VX_decode_sched_if.master decode_sched_if
-);
-
-    localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + (`NR_BITS * 4) + `XLEN + 1 + 1;
-
-    `UNUSED_PARAM (CORE_ID)
-    `UNUSED_VAR (clk)
-    `UNUSED_VAR (reset)
-    
-    reg [`EX_BITS-1:0] ex_type;    
-    reg [`INST_OP_BITS-1:0] op_type; 
-    reg [`INST_MOD_BITS-1:0] op_mod;
-    reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r;
-    reg [`XLEN-1:0] imm;    
-    reg use_rd, use_rs1, use_rs2, use_rs3, use_PC, use_imm;
-    reg is_wstall;
-
-    wire [31:0] instr = fetch_if.data.instr;
-    wire [6:0] opcode = instr[6:0];  
-    wire [1:0] func2  = instr[26:25];
-    wire [2:0] func3  = instr[14:12];
-    wire [4:0] func5  = instr[31:27];
-    wire [6:0] func7  = instr[31:25];
-    wire [11:0] u_12  = instr[31:20];
-
-    wire [4:0] rd  = instr[11:7];
-    wire [4:0] rs1 = instr[19:15];
-    wire [4:0] rs2 = instr[24:20];
-    wire [4:0] rs3 = instr[31:27];
-
-    `UNUSED_VAR (func2)
-    `UNUSED_VAR (func5)
-    `UNUSED_VAR (rs3)
-    `UNUSED_VAR (use_rd)
-    `UNUSED_VAR (use_rs1)
-    `UNUSED_VAR (use_rs2)
-    `UNUSED_VAR (use_rs3)
-
-    wire is_itype_sh = func3[0] && ~func3[1];
-
-    wire [19:0] ui_imm  = instr[31:12];
-`ifdef XLEN_64
-    wire [11:0] i_imm   = is_itype_sh ? {6'b0, instr[25:20]} : u_12;
-    wire [11:0] iw_imm  = is_itype_sh ? {7'b0, instr[24:20]} : u_12;
-`else
-    wire [11:0] i_imm   = is_itype_sh ? {7'b0, instr[24:20]} : u_12;
-`endif    
-    wire [11:0] s_imm   = {func7, rd};
-    wire [12:0] b_imm   = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
-    wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
-
-    reg [`INST_ALU_BITS-1:0] r_type;
-    always @(*) begin
-        case (func3)
-            3'h0: r_type = (opcode[5] && func7[5]) ? `INST_ALU_SUB : `INST_ALU_ADD;
-            3'h1: r_type = `INST_ALU_SLL;
-            3'h2: r_type = `INST_ALU_SLT;
-            3'h3: r_type = `INST_ALU_SLTU;
-            3'h4: r_type = `INST_ALU_XOR;
-            3'h5: r_type = func7[5] ? `INST_ALU_SRA : `INST_ALU_SRL;
-            3'h6: r_type = `INST_ALU_OR;
-            3'h7: r_type = `INST_ALU_AND;
-        endcase
-    end
-
-    reg [`INST_BR_BITS-1:0] b_type;
-    always @(*) begin
-        case (func3)
-            3'h0: b_type = `INST_BR_EQ;
-            3'h1: b_type = `INST_BR_NE;
-            3'h4: b_type = `INST_BR_LT;
-            3'h5: b_type = `INST_BR_GE;
-            3'h6: b_type = `INST_BR_LTU;
-            3'h7: b_type = `INST_BR_GEU;
-            default: b_type = 'x;
-        endcase
-    end
-
-    reg [`INST_BR_BITS-1:0] s_type;
-    always @(*) begin
-        case (u_12)
-            12'h000: s_type = `INST_OP_BITS'(`INST_BR_ECALL);
-            12'h001: s_type = `INST_OP_BITS'(`INST_BR_EBREAK);             
-            12'h002: s_type = `INST_OP_BITS'(`INST_BR_URET);                        
-            12'h102: s_type = `INST_OP_BITS'(`INST_BR_SRET);                        
-            12'h302: s_type = `INST_OP_BITS'(`INST_BR_MRET);
-            default: s_type = 'x;
-        endcase
-    end
-
-`ifdef EXT_M_ENABLE
-    reg [`INST_M_BITS-1:0] m_type;
-    always @(*) begin
-        case (func3)
-            3'h0: m_type = `INST_M_MUL;
-            3'h1: m_type = `INST_M_MULH;
-            3'h2: m_type = `INST_M_MULHSU;
-            3'h3: m_type = `INST_M_MULHU;
-            3'h4: m_type = `INST_M_DIV;
-            3'h5: m_type = `INST_M_DIVU;
-            3'h6: m_type = `INST_M_REM;
-            3'h7: m_type = `INST_M_REMU;
-        endcase
-    end
-`endif
-
-    always @(*) begin
-
-        ex_type   = '0;
-        op_type   = 'x;
-        op_mod    = '0;
-        rd_r      = '0;
-        rs1_r     = '0;
-        rs2_r     = '0;
-        rs3_r     = '0;
-        imm       = 'x;
-        use_imm   = 0;
-        use_PC    = 0;
-        use_rd    = 0;
-        use_rs1   = 0;
-        use_rs2   = 0;
-        use_rs3   = 0;
-        is_wstall = 0;
-
-        case (opcode)            
-            `INST_I: begin
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(r_type);
-                use_rd  = 1;
-                use_imm = 1;
-                imm     = {{(`XLEN-12){i_imm[11]}}, i_imm};
-                `USED_IREG (rd);
-                `USED_IREG (rs1);
-            end
-            `INST_R: begin 
-                ex_type = `EX_ALU;
-            `ifdef EXT_M_ENABLE
-                if (func7[0]) begin
-                    op_type = `INST_OP_BITS'(m_type);
-                    op_mod[1] = 1;
-                end else 
-            `endif
-                begin
-                    op_type = `INST_OP_BITS'(r_type);
-                end          
-                use_rd = 1;
-                `USED_IREG (rd);
-                `USED_IREG (rs1);
-                `USED_IREG (rs2);
-            end
-        `ifdef XLEN_64
-            `INST_I_W: begin
-                // ADDIW, SLLIW, SRLIW, SRAIW
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(r_type);
-                op_mod[2] = 1;
-                use_rd  = 1;
-                use_imm = 1;
-                imm     = {{(`XLEN-12){iw_imm[11]}}, iw_imm};
-                `USED_IREG (rd);
-                `USED_IREG (rs1);
-            end
-            `INST_R_W: begin
-                ex_type = `EX_ALU;
-            `ifdef EXT_M_ENABLE                
-                if (func7[0]) begin
-                    // MULW, DIVW, DIVUW, REMW, REMUW
-                    op_type = `INST_OP_BITS'(m_type);
-                    op_mod[1] = 1;                    
-                end else 
-            `endif
-                begin
-                    // ADDW, SUBW, SLLW, SRLW, SRAW
-                    op_type = `INST_OP_BITS'(r_type);
-                end
-                op_mod[2] = 1;
-                use_rd = 1;
-                `USED_IREG (rd);
-                `USED_IREG (rs1);
-                `USED_IREG (rs2);
-            end
-        `endif
-            `INST_LUI: begin 
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(`INST_ALU_LUI);
-                use_rd  = 1;
-                use_imm = 1;
-                imm     = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
-                `USED_IREG (rd);
-            end
-            `INST_AUIPC: begin 
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(`INST_ALU_AUIPC);
-                use_rd  = 1;
-                use_imm = 1;
-                use_PC  = 1;
-                imm     = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
-                `USED_IREG (rd);
-            end
-            `INST_JAL: begin 
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(`INST_BR_JAL);
-                op_mod[0] = 1;
-                use_rd  = 1;
-                use_imm = 1;
-                use_PC  = 1;
-                is_wstall = 1;
-                imm     = {{(`XLEN-21){jal_imm[20]}}, jal_imm};
-                `USED_IREG (rd);
-            end
-            `INST_JALR: begin 
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(`INST_BR_JALR);
-                op_mod[0] = 1;
-                use_rd  = 1;
-                use_imm = 1;
-                is_wstall = 1;
-                imm     = {{(`XLEN-12){u_12[11]}}, u_12};
-                `USED_IREG (rd);
-                `USED_IREG (rs1);
-            end
-            `INST_B: begin 
-                ex_type = `EX_ALU;
-                op_type = `INST_OP_BITS'(b_type);
-                op_mod[0] = 1;
-                use_imm = 1;
-                use_PC  = 1;
-                is_wstall = 1;
-                imm     = {{(`XLEN-13){b_imm[12]}}, b_imm};
-                `USED_IREG (rs1);
-                `USED_IREG (rs2);
-            end
-            `INST_FENCE: begin
-                ex_type = `EX_LSU;
-                op_type = `INST_LSU_FENCE;
-            end
-            `INST_SYS : begin 
-                if (func3[1:0] != 0) begin                    
-                    ex_type = `EX_SFU;
-                    op_type = `INST_OP_BITS'(`INST_SFU_CSR(func3[1:0]));
-                    use_rd  = 1;
-                    is_wstall = 1;
-                    use_imm = func3[2];
-                    imm[`VX_CSR_ADDR_BITS-1:0] = u_12; // addr
-                    `USED_IREG (rd);
-                    if (func3[2]) begin
-                        imm[`VX_CSR_ADDR_BITS +: `NRI_BITS] = rs1; // imm
-                    end else begin
-                        `USED_IREG (rs1);
-                    end                    
-                end else begin
-                    ex_type = `EX_ALU;
-                    op_type = `INST_OP_BITS'(s_type);
-                    op_mod[0] = 1;
-                    use_rd  = 1;
-                    use_imm = 1;
-                    use_PC  = 1;
-                    is_wstall = 1;
-                    imm     = `XLEN'd4;
-                    `USED_IREG (rd);
-                end
-            end
-        `ifdef EXT_F_ENABLE
-            `INST_FL, 
-        `endif
-            `INST_L: begin 
-                ex_type = `EX_LSU;
-                op_type = `INST_OP_BITS'({1'b0, func3});
-                use_rd  = 1;
-                imm     = {{(`XLEN-12){u_12[11]}}, u_12};
-                use_imm = 1;
-            `ifdef EXT_F_ENABLE
-                if (opcode[2]) begin
-                    `USED_FREG (rd);
-                end else
-            `endif
-                `USED_IREG (rd);
-                `USED_IREG (rs1);
-            end
-        `ifdef EXT_F_ENABLE
-            `INST_FS, 
-        `endif
-            `INST_S: begin 
-                ex_type = `EX_LSU;
-                op_type = `INST_OP_BITS'({1'b1, func3});
-                imm     = {{(`XLEN-12){s_imm[11]}}, s_imm};
-                use_imm = 1;
-                `USED_IREG (rs1);
-            `ifdef EXT_F_ENABLE
-                if (opcode[2]) begin
-                    `USED_FREG (rs2);
-                end else
-            `endif
-                `USED_IREG (rs2);
-            end
-        `ifdef EXT_F_ENABLE
-            `INST_FMADD,
-            `INST_FMSUB,
-            `INST_FNMSUB,
-            `INST_FNMADD: begin 
-                ex_type = `EX_FPU;
-                op_type = `INST_OP_BITS'({2'b11, opcode[3:2]});
-                op_mod  = `INST_MOD_BITS'(func3);
-                imm[0]  = func2[0]; // destination is double?
-                use_rd  = 1;
-                `USED_FREG (rd);              
-                `USED_FREG (rs1);
-                `USED_FREG (rs2);
-                `USED_FREG (rs3);
-            end
-            `INST_FCI: begin 
-                ex_type = `EX_FPU;
-                op_mod  = `INST_MOD_BITS'(func3);
-            `ifdef FLEN_64
-                imm[0]  = func2[0]; // destination is double?
-            `endif
-                use_rd  = 1;                
-                case (func5)
-                    5'b00000, // FADD
-                    5'b00001, // FSUB
-                    5'b00010, // FMUL
-                    5'b00011: begin // FDIV
-                        op_type = `INST_OP_BITS'(func5[1:0]);
-                        `USED_FREG (rd);
-                        `USED_FREG (rs1);
-                        `USED_FREG (rs2);
-                    end
-                    5'b00100: begin
-                        // NCP: FSGNJ=0, FSGNJN=1, FSGNJX=2
-                        op_type = `INST_OP_BITS'(`INST_FPU_MISC);
-                        op_mod  = `INST_MOD_BITS'(func3[1:0]);
-                        `USED_FREG (rd);
-                        `USED_FREG (rs1);
-                        `USED_FREG (rs2);
-                    end
-                    5'b00101: begin
-                        // NCP: FMIN=6, FMAX=7
-                        op_type = `INST_OP_BITS'(`INST_FPU_MISC);
-                        op_mod  = func3[0] ? 7 : 6;
-                        `USED_FREG (rd);
-                        `USED_FREG (rs1);
-                        `USED_FREG (rs2);
-                    end 
-                `ifdef FLEN_64
-                    5'b01000: begin   
-                        // CVT.S.D, CVT.D.S
-                        op_type = `INST_OP_BITS'(`INST_FPU_F2F);
-                        `USED_FREG (rd);
-                        `USED_FREG (rs1);
-                    end
-                `endif
-                    5'b01011: begin                        
-                        // SQRT
-                        op_type = `INST_OP_BITS'(`INST_FPU_SQRT);
-                        `USED_FREG (rd);
-                        `USED_FREG (rs1);
-                    end   
-                    5'b10100: begin
-                        // CMP
-                        op_type = `INST_OP_BITS'(`INST_FPU_CMP);
-                        `USED_IREG (rd);
-                        `USED_FREG (rs1);
-                        `USED_FREG (rs2);
-                    end             
-                    5'b11000: begin
-                        // CVT.W.X, CVT.WU.X
-                        op_type = (rs2[0]) ? `INST_OP_BITS'(`INST_FPU_F2U) : `INST_OP_BITS'(`INST_FPU_F2I);
-                    `ifdef XLEN_64
-                        imm[1] = rs2[1]; // is 64-bit integer
-                    `endif
-                        `USED_IREG (rd);
-                        `USED_FREG (rs1);
-                    end
-                    5'b11010: begin
-                        // CVT.X.W, CVT.X.WU
-                        op_type = (rs2[0]) ? `INST_OP_BITS'(`INST_FPU_U2F) : `INST_OP_BITS'(`INST_FPU_I2F);
-                    `ifdef XLEN_64
-                        imm[1] = rs2[1]; // is 64-bit integer
-                    `endif
-                        `USED_FREG (rd);
-                        `USED_IREG (rs1);
-                    end
-                    5'b11100: begin 
-                        if (func3[0]) begin
-                            // NCP: FCLASS=3
-                            op_type = `INST_OP_BITS'(`INST_FPU_MISC);                                     
-                            op_mod  = 3;
-                        end else begin
-                            // NCP: FMV.X.W=4
-                            op_type = `INST_OP_BITS'(`INST_FPU_MISC);
-                            op_mod  = 4;
-                        end
-                        `USED_IREG (rd);
-                        `USED_FREG (rs1);                                           
-                    end 
-                    5'b11110: begin 
-                        // NCP: FMV.W.X=5
-                        op_type = `INST_OP_BITS'(`INST_FPU_MISC); 
-                        op_mod  = 5;
-                        `USED_FREG (rd);
-                        `USED_IREG (rs1);
-                    end
-                default:;
-                endcase
-            end
-        `endif
-            `INST_EXT1: begin 
-                case (func7)
-                    7'h00: begin
-                        ex_type = `EX_SFU;
-                        is_wstall = 1;
-                        case (func3)
-                            3'h0: begin // TMC
-                                op_type = `INST_OP_BITS'(`INST_SFU_TMC);
-                                `USED_IREG (rs1);
-                            end
-                            3'h1: begin // WSPAWN
-                                op_type = `INST_OP_BITS'(`INST_SFU_WSPAWN);
-                                `USED_IREG (rs1);
-                                `USED_IREG (rs2);
-                            end
-                            3'h2: begin // SPLIT
-                                op_type = `INST_OP_BITS'(`INST_SFU_SPLIT);
-                                use_rd    = 1;
-                                `USED_IREG (rs1);                                
-                                `USED_IREG (rd);                                
-                            end
-                            3'h3: begin // JOIN
-                                op_type = `INST_OP_BITS'(`INST_SFU_JOIN);
-                                `USED_IREG (rs1);
-                            end
-                            3'h4: begin // BAR
-                                op_type = `INST_OP_BITS'(`INST_SFU_BAR);
-                                `USED_IREG (rs1);
-                                `USED_IREG (rs2);
-                            end
-                            3'h5: begin // PRED
-                                op_type = `INST_OP_BITS'(`INST_SFU_PRED);
-                                `USED_IREG (rs1);
-                                `USED_IREG (rs2);
-                            end
-                            default:;
-                        endcase
-                    end
-                    default:;
-                endcase
-            end
-            `INST_EXT2: begin                
-                case (func3)
-                    3'h1: begin
-                        case (func2)                       
-                            2'h0: begin // CMOV
-                                ex_type = `EX_SFU;
-                                op_type = `INST_OP_BITS'(`INST_SFU_CMOV);
-                                use_rd = 1;
-                                `USED_IREG (rd);
-                                `USED_IREG (rs1);
-                                `USED_IREG (rs2);
-                                `USED_IREG (rs3);
-                            end
-                            default:;
-                        endcase
-                    end
-                    default:;
-                endcase
-            end
-            default:;
-        endcase
-    end
-
-    // disable write to integer register r0
-    wire wb = use_rd && (rd_r != 0);
-
-    VX_elastic_buffer #(
-        .DATAW (DATAW),
-        .SIZE  (0)
-    ) req_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (fetch_if.valid),
-        .ready_in  (fetch_if.ready),
-        .data_in   ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_mod, use_PC, imm, use_imm, wb, rd_r, rs1_r, rs2_r, rs3_r}),
-        .data_out  ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.use_PC, decode_if.data.imm, decode_if.data.use_imm, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}),
-        .valid_out (decode_if.valid),
-        .ready_out (decode_if.ready)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    wire fetch_fire = fetch_if.valid && fetch_if.ready;
-
-    assign decode_sched_if.valid    = fetch_fire;
-    assign decode_sched_if.wid      = fetch_if.data.wid;
-    assign decode_sched_if.is_wstall = is_wstall;
-`ifndef L1_ENABLE    
-    assign fetch_if.ibuf_pop = decode_if.ibuf_pop;
-`endif
-
-`ifdef DBG_TRACE_CORE_PIPELINE
-    always @(posedge clk) begin
-        if (decode_if.valid && decode_if.ready) begin
-            `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));
-            trace_ex_type(1, decode_if.data.ex_type);
-            `TRACE(1, (", op="));
-            trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.rd, decode_if.data.rs2, decode_if.data.use_imm, decode_if.data.imm);
-            `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, opds=%b%b%b%b, use_pc=%b, use_imm=%b (#%0d)\n",
-                decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid));
-        end
-    end
-`endif
-
-endmodule

hw/rtl/core/VX_dispatch.sv

@@ -1,236 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-`include "VX_trace.vh"
-
-module VX_dispatch import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    output wire [`PERF_CTR_BITS-1:0] perf_stalls [`NUM_EX_UNITS],
-`endif
-    // inputs
-    VX_operands_if.slave    operands_if [`ISSUE_WIDTH],
-
-    // outputs
-    VX_dispatch_if.master   alu_dispatch_if [`ISSUE_WIDTH],
-    VX_dispatch_if.master   lsu_dispatch_if [`ISSUE_WIDTH],
-`ifdef EXT_F_ENABLE
-    VX_dispatch_if.master   fpu_dispatch_if [`ISSUE_WIDTH],
-`endif
-    VX_dispatch_if.master   sfu_dispatch_if [`ISSUE_WIDTH] 
-);
-    `UNUSED_PARAM (CORE_ID)
-
-    localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH;
-
-    wire [`ISSUE_WIDTH-1:0][`NT_WIDTH-1:0] last_active_tid;
-
-    wire [`NUM_THREADS-1:0][`NT_WIDTH-1:0] tids;
-    for (genvar i = 0; i < `NUM_THREADS; ++i) begin                 
-        assign tids[i] = `NT_WIDTH'(i);
-    end
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        VX_find_first #(
-            .N (`NUM_THREADS),
-            .DATAW (`NT_WIDTH),
-            .REVERSE (1)
-        ) last_tid_select (
-            .valid_in (operands_if[i].data.tmask),
-            .data_in  (tids),
-            .data_out (last_active_tid[i]),
-            `UNUSED_PIN (valid_out)
-        );
-    end
- 
-    // ALU dispatch    
-
-    VX_operands_if alu_operands_if[`ISSUE_WIDTH]();
-    
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign alu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_ALU);
-        assign alu_operands_if[i].data = operands_if[i].data;
-
-        `RESET_RELAY (alu_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (DATAW),
-            .SIZE    (2),
-            .OUT_REG (2)
-        ) alu_buffer (
-            .clk        (clk),
-            .reset      (alu_reset),
-            .valid_in   (alu_operands_if[i].valid),
-            .ready_in   (alu_operands_if[i].ready),
-            .data_in    (`TO_DISPATCH_DATA(alu_operands_if[i].data, last_active_tid[i])),
-            .data_out   (alu_dispatch_if[i].data),
-            .valid_out  (alu_dispatch_if[i].valid),
-            .ready_out  (alu_dispatch_if[i].ready)
-        );
-    end
-
-    // LSU dispatch
-
-    VX_operands_if lsu_operands_if[`ISSUE_WIDTH]();
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign lsu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_LSU);
-        assign lsu_operands_if[i].data = operands_if[i].data;
-
-        `RESET_RELAY (lsu_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (DATAW),
-            .SIZE    (2),
-            .OUT_REG (2)
-        ) lsu_buffer (
-            .clk        (clk),
-            .reset      (lsu_reset),
-            .valid_in   (lsu_operands_if[i].valid),
-            .ready_in   (lsu_operands_if[i].ready),
-            .data_in    (`TO_DISPATCH_DATA(lsu_operands_if[i].data, last_active_tid[i])),           
-            .data_out   (lsu_dispatch_if[i].data),
-            .valid_out  (lsu_dispatch_if[i].valid),
-            .ready_out  (lsu_dispatch_if[i].ready)
-        );
-    end
-
-    // FPU dispatch
-
-`ifdef EXT_F_ENABLE
-
-    VX_operands_if fpu_operands_if[`ISSUE_WIDTH]();
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign fpu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_FPU);
-        assign fpu_operands_if[i].data = operands_if[i].data;
-
-        `RESET_RELAY (fpu_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (DATAW),
-            .SIZE    (2),
-            .OUT_REG (2)
-        ) fpu_buffer (
-            .clk        (clk),
-            .reset      (fpu_reset),
-            .valid_in   (fpu_operands_if[i].valid),
-            .ready_in   (fpu_operands_if[i].ready),
-            .data_in    (`TO_DISPATCH_DATA(fpu_operands_if[i].data, last_active_tid[i])),           
-            .data_out   (fpu_dispatch_if[i].data),
-            .valid_out  (fpu_dispatch_if[i].valid),
-            .ready_out  (fpu_dispatch_if[i].ready)
-        );
-    end
-`endif
-
-    // SFU dispatch
-
-    VX_operands_if sfu_operands_if[`ISSUE_WIDTH]();
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign sfu_operands_if[i].valid = operands_if[i].valid && (operands_if[i].data.ex_type == `EX_SFU);
-        assign sfu_operands_if[i].data = operands_if[i].data;
-
-        `RESET_RELAY (sfu_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (DATAW),
-            .SIZE    (2),
-            .OUT_REG (2)
-        ) sfu_buffer (
-            .clk        (clk),
-            .reset      (sfu_reset),
-            .valid_in   (sfu_operands_if[i].valid),
-            .ready_in   (sfu_operands_if[i].ready),
-            .data_in    (`TO_DISPATCH_DATA(sfu_operands_if[i].data, last_active_tid[i])),           
-            .data_out   (sfu_dispatch_if[i].data),
-            .valid_out  (sfu_dispatch_if[i].valid),
-            .ready_out  (sfu_dispatch_if[i].ready)
-        );
-    end
-
-    // can take next request?
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign operands_if[i].ready = (alu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_ALU)) 
-                                   || (lsu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_LSU))
-                                `ifdef EXT_F_ENABLE
-                                   || (fpu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_FPU))
-                                `endif
-                                   || (sfu_operands_if[i].ready && (operands_if[i].data.ex_type == `EX_SFU));
-    end
-
-`ifdef PERF_ENABLE    
-    wire [`NUM_EX_UNITS-1:0] perf_unit_stalls_per_cycle, perf_unit_stalls_per_cycle_r;
-    reg [`ISSUE_WIDTH-1:0][`NUM_EX_UNITS-1:0] perf_issue_unit_stalls_per_cycle;
-    reg [`NUM_EX_UNITS-1:0][`PERF_CTR_BITS-1:0] perf_stalls_r;
-
-    for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
-        always @(*) begin        
-            perf_issue_unit_stalls_per_cycle[i] = '0;
-            if (operands_if[i].valid && ~operands_if[i].ready) begin
-                perf_issue_unit_stalls_per_cycle[i][operands_if[i].data.ex_type] = 1;
-            end
-        end
-    end
-
-    VX_reduce #(
-        .DATAW_IN (`NUM_EX_UNITS),
-        .N  (`ISSUE_WIDTH),
-        .OP ("|")
-    ) reduce (
-        .data_in (perf_issue_unit_stalls_per_cycle),
-        .data_out (perf_unit_stalls_per_cycle)
-    );
-
-    `BUFFER(perf_unit_stalls_per_cycle_r, perf_unit_stalls_per_cycle);
-
-    for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
-        always @(posedge clk) begin
-            if (reset) begin
-                perf_stalls_r[i] <= '0;
-            end else begin
-                perf_stalls_r[i] <= perf_stalls_r[i] + `PERF_CTR_BITS'(perf_unit_stalls_per_cycle_r[i]);
-            end
-        end
-    end
-    
-    for (genvar i=0; i < `NUM_EX_UNITS; ++i) begin
-        assign perf_stalls[i] = perf_stalls_r[i];
-    end
-`endif
-
-`ifdef DBG_TRACE_CORE_PIPELINE
-    for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
-        always @(posedge clk) begin
-            if (operands_if[i].valid && operands_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC));
-                trace_ex_type(1, operands_if[i].data.ex_type);
-                `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.op_mod, operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd));
-                `TRACE_ARRAY1D(1, operands_if[i].data.rs1_data, `NUM_THREADS);
-                `TRACE(1, (", rs2_data="));
-                `TRACE_ARRAY1D(1, operands_if[i].data.rs2_data, `NUM_THREADS);
-                `TRACE(1, (", rs3_data="));
-                `TRACE_ARRAY1D(1, operands_if[i].data.rs3_data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid));
-            end
-        end
-    end
-`endif
-
-endmodule

hw/rtl/core/VX_dispatch_unit.sv

@@ -1,256 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_dispatch_unit import VX_gpu_pkg::*; #(    
-    parameter BLOCK_SIZE = 1,
-    parameter NUM_LANES  = 1,
-    parameter OUT_REG    = 0,
-    parameter MAX_FANOUT = `MAX_FANOUT
-) ( 
-    input  wire             clk,
-    input  wire             reset,
-
-    // inputs    
-    VX_dispatch_if.slave    dispatch_if [`ISSUE_WIDTH],
-
-    // outputs
-    VX_execute_if.master    execute_if [BLOCK_SIZE]
-
-);
-    `STATIC_ASSERT ((`NUM_THREADS == NUM_LANES  * (`NUM_THREADS / NUM_LANES)), ("invalid parameter"))
-    localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE);
-    localparam NUM_PACKETS  = `NUM_THREADS / NUM_LANES;
-    localparam PID_BITS     = `CLOG2(NUM_PACKETS);
-    localparam PID_WIDTH    = `UP(PID_BITS);
-    localparam BATCH_COUNT  = `ISSUE_WIDTH / BLOCK_SIZE;
-    localparam BATCH_COUNT_W= `LOG2UP(BATCH_COUNT);
-    localparam ISSUE_W      = `LOG2UP(`ISSUE_WIDTH);
-    localparam IN_DATAW     = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + `NT_WIDTH + (3 * `NUM_THREADS * `XLEN);
-    localparam OUT_DATAW    = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + `NR_BITS + `NT_WIDTH + (3 * NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1;
-    localparam FANOUT_ENABLE= (`NUM_THREADS > (MAX_FANOUT + MAX_FANOUT/2));
-
-    localparam DATA_TMASK_OFF = IN_DATAW - (`UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS);
-    localparam DATA_REGS_OFF = 0;
-
-    wire [`ISSUE_WIDTH-1:0] dispatch_valid;
-    wire [`ISSUE_WIDTH-1:0][IN_DATAW-1:0] dispatch_data;
-    wire [`ISSUE_WIDTH-1:0] dispatch_ready;
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        assign dispatch_valid[i] = dispatch_if[i].valid;
-        assign dispatch_data[i] = dispatch_if[i].data;
-        assign dispatch_if[i].ready = dispatch_ready[i];
-    end
-    
-    wire [BLOCK_SIZE-1:0][ISSUE_W-1:0] issue_indices;
-    wire [BLOCK_SIZE-1:0] block_ready;
-    wire [BLOCK_SIZE-1:0][NUM_LANES-1:0] block_tmask;
-    wire [BLOCK_SIZE-1:0][2:0][NUM_LANES-1:0][`XLEN-1:0] block_regs;
-    wire [BLOCK_SIZE-1:0][PID_WIDTH-1:0] block_pid;
-    wire [BLOCK_SIZE-1:0] block_sop;
-    wire [BLOCK_SIZE-1:0] block_eop;
-    wire [BLOCK_SIZE-1:0] block_done;
-
-    wire batch_done = (& block_done);
-    
-    logic [BATCH_COUNT_W-1:0] batch_idx;
-    if (BATCH_COUNT != 1) begin
-        always @(posedge clk) begin
-            if (reset) begin
-                batch_idx <= '0;
-            end else begin
-                batch_idx <= batch_idx + BATCH_COUNT_W'(batch_done);
-            end
-        end
-    end else begin
-        assign batch_idx = 0;
-        `UNUSED_VAR (batch_done)
-    end
-    
-    for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
-
-        wire [ISSUE_W-1:0] issue_idx = ISSUE_W'(batch_idx * BLOCK_SIZE) + ISSUE_W'(block_idx);
-        assign issue_indices[block_idx] = issue_idx;
-
-        wire valid_p, ready_p;
-
-        if (`NUM_THREADS != NUM_LANES) begin
-            reg [NUM_PACKETS-1:0] sent_mask_p;
-            wire [PID_WIDTH-1:0] start_p_n, start_p, end_p;
-            wire dispatch_valid_r;
-            reg is_first_p;
-
-            wire fire_p = valid_p && ready_p;
-
-            wire is_last_p = (start_p == end_p);
-
-            wire fire_eop = fire_p && is_last_p;
-
-            always @(posedge clk) begin
-                if (reset) begin
-                    sent_mask_p <= '0;
-                    is_first_p  <= 1;
-                end else begin
-                    if ((BATCH_COUNT != 1) ? batch_done : fire_eop) begin
-                        sent_mask_p <= '0;
-                        is_first_p <= 1;
-                    end else if (fire_p) begin
-                        sent_mask_p[start_p] <= 1;
-                        is_first_p <= 0;
-                    end
-                end
-            end
-
-            wire [NUM_PACKETS-1:0][NUM_LANES-1:0] per_packet_tmask;
-            wire [NUM_PACKETS-1:0][2:0][NUM_LANES-1:0][`XLEN-1:0] per_packet_regs; 
-
-            wire [`NUM_THREADS-1:0] dispatch_tmask = dispatch_data[issue_idx][DATA_TMASK_OFF +: `NUM_THREADS];
-            wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs1_data = dispatch_data[issue_idx][DATA_REGS_OFF + 2 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
-            wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs2_data = dispatch_data[issue_idx][DATA_REGS_OFF + 1 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
-            wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs3_data = dispatch_data[issue_idx][DATA_REGS_OFF + 0 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
-
-            for (genvar i = 0; i < NUM_PACKETS; ++i) begin
-                for (genvar j = 0; j < NUM_LANES; ++j) begin
-                    localparam k = i * NUM_LANES + j;
-                    assign per_packet_tmask[i][j]   = dispatch_tmask[k];
-                    assign per_packet_regs[i][0][j] = dispatch_rs1_data[k];
-                    assign per_packet_regs[i][1][j] = dispatch_rs2_data[k];
-                    assign per_packet_regs[i][2][j] = dispatch_rs3_data[k];
-                end
-            end
-
-            wire [NUM_PACKETS-1:0] packet_valids;
-            wire [NUM_PACKETS-1:0][PID_WIDTH-1:0] packet_ids;
-
-            for (genvar i = 0; i < NUM_PACKETS; ++i) begin                 
-                assign packet_valids[i] = (| per_packet_tmask[i]);
-                assign packet_ids[i] = PID_WIDTH'(i);
-            end
-
-            VX_find_first #(
-                .N       (NUM_PACKETS),
-                .DATAW   (PID_WIDTH),
-                .REVERSE (0)
-            ) find_first (                    
-                .valid_in  (packet_valids & ~sent_mask_p),
-                .data_in   (packet_ids),
-                .data_out  (start_p_n),
-                `UNUSED_PIN (valid_out)
-            );
-
-            VX_find_first #(
-                .N       (NUM_PACKETS),
-                .DATAW   (PID_WIDTH),
-                .REVERSE (1)
-            ) find_last (                    
-                .valid_in  (packet_valids),
-                .data_in   (packet_ids),
-                .data_out  (end_p),
-                `UNUSED_PIN (valid_out)
-            );   
-
-            VX_pipe_register #(
-                .DATAW  (1 + PID_WIDTH),
-                .RESETW (1),
-                .DEPTH  (FANOUT_ENABLE ? 1 : 0)
-            ) pipe_reg (
-                .clk      (clk),
-                .reset    (reset || fire_p), // should flush on fire
-                .enable   (1'b1),
-                .data_in  ({dispatch_valid[issue_idx], start_p_n}),
-                .data_out ({dispatch_valid_r, start_p})
-            );  
-
-            wire [NUM_LANES-1:0] tmask_p = per_packet_tmask[start_p];
-            wire [2:0][NUM_LANES-1:0][`XLEN-1:0] regs_p = per_packet_regs[start_p];
-
-            wire block_enable = (BATCH_COUNT == 1 || ~(& sent_mask_p));
-            
-            assign valid_p = dispatch_valid_r && block_enable;            
-            assign block_tmask[block_idx] = tmask_p;
-            assign block_regs[block_idx]  = regs_p;
-            assign block_pid[block_idx]   = start_p;
-            assign block_sop[block_idx]   = is_first_p;
-            assign block_eop[block_idx]   = is_last_p;
-            if (FANOUT_ENABLE) begin
-                assign block_ready[block_idx] = dispatch_valid_r && ready_p && block_enable;
-            end else begin
-                assign block_ready[block_idx] = ready_p && block_enable;
-            end
-            assign block_done[block_idx] = ~dispatch_valid[issue_idx] || fire_eop;
-        end else begin
-            assign valid_p = dispatch_valid[issue_idx];
-            assign block_tmask[block_idx] = dispatch_data[issue_idx][DATA_TMASK_OFF +: `NUM_THREADS];
-            assign block_regs[block_idx][0] = dispatch_data[issue_idx][DATA_REGS_OFF + 2 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
-            assign block_regs[block_idx][1] = dispatch_data[issue_idx][DATA_REGS_OFF + 1 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
-            assign block_regs[block_idx][2] = dispatch_data[issue_idx][DATA_REGS_OFF + 0 * `NUM_THREADS * `XLEN +: `NUM_THREADS * `XLEN];
-            assign block_pid[block_idx]   = '0;
-            assign block_sop[block_idx]   = 1'b1;
-            assign block_eop[block_idx]   = 1'b1;
-            assign block_ready[block_idx] = ready_p;
-            assign block_done[block_idx]  = ~valid_p || ready_p;
-        end
-
-        wire [ISSUE_ISW_W-1:0] isw;
-        if (BATCH_COUNT != 1) begin
-            if (BLOCK_SIZE != 1) begin
-                assign isw = {batch_idx, BLOCK_SIZE_W'(block_idx)};
-            end else begin
-                assign isw = batch_idx;
-            end
-        end else begin
-            assign isw = block_idx;
-        end
-
-        `RESET_RELAY(buf_out_reset, reset);
-
-        wire [`NW_WIDTH-1:0] block_wid = wis_to_wid(dispatch_data[issue_idx][DATA_TMASK_OFF+`NUM_THREADS +: ISSUE_WIS_W], isw);
-
-        VX_elastic_buffer #(
-            .DATAW   (OUT_DATAW),
-            .SIZE    (`OUT_REG_TO_EB_SIZE(OUT_REG)),
-            .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
-        ) buf_out (
-            .clk       (clk),
-            .reset     (buf_out_reset),
-            .valid_in  (valid_p),
-            .ready_in  (ready_p),
-            .data_in   ({                
-                dispatch_data[issue_idx][IN_DATAW-1 : DATA_TMASK_OFF+`NUM_THREADS+ISSUE_WIS_W],
-                block_wid,
-                block_tmask[block_idx],
-                dispatch_data[issue_idx][DATA_TMASK_OFF-1 : DATA_REGS_OFF + 3 * `NUM_THREADS * `XLEN],
-                block_regs[block_idx][0],
-                block_regs[block_idx][1],
-                block_regs[block_idx][2],     
-                block_pid[block_idx],
-                block_sop[block_idx],
-                block_eop[block_idx]}),
-            .data_out  (execute_if[block_idx].data),
-            .valid_out (execute_if[block_idx].valid),
-            .ready_out (execute_if[block_idx].ready)
-        );
-    end
-
-    reg [`ISSUE_WIDTH-1:0] ready_in;
-    always @(*) begin
-        ready_in = 0;
-        for (integer i = 0; i < BLOCK_SIZE; ++i) begin
-            ready_in[issue_indices[i]] = block_ready[i] && block_eop[i];
-        end
-    end
-    assign dispatch_ready = ready_in; 
-
-endmodule

hw/rtl/core/VX_execute.sv

@@ -1,137 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_execute import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    `SCOPE_IO_DECL
-
-    input wire              clk, 
-    input wire              reset,    
-
-    input base_dcrs_t       base_dcrs,
-
-    // Dcache interface
-    VX_mem_bus_if.master    dcache_bus_if [DCACHE_NUM_REQS],
-
-    // commit interface
-    VX_commit_csr_if.slave  commit_csr_if,
-
-    // fetch interface
-    VX_sched_csr_if.slave   sched_csr_if,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave    mem_perf_if,
-    VX_pipeline_perf_if.slave pipeline_perf_if,
-`endif
-
-`ifdef EXT_F_ENABLE
-    VX_dispatch_if.slave    fpu_dispatch_if [`ISSUE_WIDTH],
-    VX_commit_if.master     fpu_commit_if [`ISSUE_WIDTH],
-`endif
-  
-    VX_dispatch_if.slave    alu_dispatch_if [`ISSUE_WIDTH],
-    VX_commit_if.master     alu_commit_if [`ISSUE_WIDTH],
-    VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS],
-    
-    VX_dispatch_if.slave    lsu_dispatch_if [`ISSUE_WIDTH],  
-    VX_commit_if.master     lsu_commit_if [`ISSUE_WIDTH],
-    
-    VX_dispatch_if.slave    sfu_dispatch_if [`ISSUE_WIDTH], 
-    VX_commit_if.master     sfu_commit_if [`ISSUE_WIDTH],
-    VX_warp_ctl_if.master   warp_ctl_if,
-
-    // simulation helper signals
-    output wire             sim_ebreak
-);
-
-`ifdef EXT_F_ENABLE
-    VX_fpu_to_csr_if fpu_to_csr_if[`NUM_FPU_BLOCKS]();
-`endif
-
-    `RESET_RELAY (alu_reset, reset);
-    `RESET_RELAY (lsu_reset, reset);
-    `RESET_RELAY (sfu_reset, reset);
-    
-    VX_alu_unit #(
-        .CORE_ID (CORE_ID)
-    ) alu_unit (
-        .clk            (clk),
-        .reset          (alu_reset),
-        .dispatch_if    (alu_dispatch_if),
-        .branch_ctl_if  (branch_ctl_if),
-        .commit_if      (alu_commit_if)
-    );
-
-    `SCOPE_IO_SWITCH (1)
-
-    VX_lsu_unit #(
-        .CORE_ID (CORE_ID)
-    ) lsu_unit (
-        `SCOPE_IO_BIND  (0)
-        .clk            (clk),
-        .reset          (lsu_reset),
-        .cache_bus_if   (dcache_bus_if),
-        .dispatch_if    (lsu_dispatch_if),
-        .commit_if      (lsu_commit_if)
-    );
-
-`ifdef EXT_F_ENABLE
-    `RESET_RELAY (fpu_reset, reset);
-
-    VX_fpu_unit #(
-        .CORE_ID (CORE_ID)
-    ) fpu_unit (
-        .clk            (clk),
-        .reset          (fpu_reset),    
-        .dispatch_if    (fpu_dispatch_if), 
-        .fpu_to_csr_if  (fpu_to_csr_if),
-        .commit_if      (fpu_commit_if)
-    );
-`endif
-
-    VX_sfu_unit #(
-        .CORE_ID (CORE_ID)
-    ) sfu_unit (
-        .clk            (clk),
-        .reset          (sfu_reset),
-
-    `ifdef PERF_ENABLE
-        .mem_perf_if    (mem_perf_if),
-        .pipeline_perf_if (pipeline_perf_if),
-    `endif
-
-        .base_dcrs      (base_dcrs),            
-
-        .dispatch_if    (sfu_dispatch_if),
-    
-    `ifdef EXT_F_ENABLE
-        .fpu_to_csr_if  (fpu_to_csr_if),
-    `endif
-    
-        .commit_csr_if  (commit_csr_if),
-        .sched_csr_if   (sched_csr_if),
-        .warp_ctl_if    (warp_ctl_if),
-        .commit_if      (sfu_commit_if)
-    );
-
-    // simulation helper signal to get RISC-V tests Pass/Fail status
-    assign sim_ebreak = alu_dispatch_if[0].valid && alu_dispatch_if[0].ready 
-                     && alu_dispatch_if[0].data.wis == 0
-                     && `INST_ALU_IS_BR(alu_dispatch_if[0].data.op_mod)
-                     && (`INST_BR_BITS'(alu_dispatch_if[0].data.op_type) == `INST_BR_EBREAK
-                      || `INST_BR_BITS'(alu_dispatch_if[0].data.op_type) == `INST_BR_ECALL);
-
-endmodule

hw/rtl/core/VX_fetch.sv

@@ -1,187 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_fetch import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    `SCOPE_IO_DECL
-
-    input  wire             clk,
-    input  wire             reset,
-
-    // Icache interface
-    VX_mem_bus_if.master    icache_bus_if,
-    
-    // inputs
-    VX_schedule_if.slave    schedule_if,
-
-    // outputs
-    VX_fetch_if.master      fetch_if
-);
-    `UNUSED_PARAM (CORE_ID)
-    `UNUSED_VAR (reset)
-
-    wire icache_req_valid;
-    wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr;
-    wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag;
-    wire icache_req_ready;
-
-    wire [`UUID_WIDTH-1:0] rsp_uuid;
-    wire [`NW_WIDTH-1:0] req_tag, rsp_tag;    
-
-    wire icache_req_fire = icache_req_valid && icache_req_ready;
-
-    assign req_tag = schedule_if.data.wid;
-    
-    assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_data.tag;
-
-    wire [`XLEN-1:0] rsp_PC;
-    wire [`NUM_THREADS-1:0] rsp_tmask;
-
-    VX_dp_ram #(
-        .DATAW  (`XLEN + `NUM_THREADS),
-        .SIZE   (`NUM_WARPS),
-        .LUTRAM (1)
-    ) tag_store (
-        .clk   (clk),  
-        .read  (1'b1),
-        .write (icache_req_fire),        
-        `UNUSED_PIN (wren),
-        .waddr (req_tag),
-        .wdata ({schedule_if.data.PC, schedule_if.data.tmask}),
-        .raddr (rsp_tag),
-        .rdata ({rsp_PC, rsp_tmask})
-    );
-
-`ifndef L1_ENABLE
-    // Ensure that the ibuffer doesn't fill up.
-    // This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache request.
-    // This issue is particularly prevalent when the icache and dcache is disabled and both requests share the same bus.
-    wire [ISSUE_ISW-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid);
-
-    wire [`ISSUE_WIDTH-1:0] pending_ibuf_full;
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        VX_pending_size #( 
-            .SIZE (`IBUF_SIZE)
-        ) pending_reads (
-            .clk   (clk),
-            .reset (reset),
-            .incr  (icache_req_fire && schedule_isw == i),
-            .decr  (fetch_if.ibuf_pop[i]),
-            .full  (pending_ibuf_full[i]),
-            `UNUSED_PIN (size),
-            `UNUSED_PIN (empty)
-        );
-    end
-    wire ibuf_ready = ~pending_ibuf_full[schedule_isw];
-`else
-    wire ibuf_ready = 1'b1;
-`endif
-
-    `RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0), 
-        ("%t: *** invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid))
-
-    // Icache Request
-    
-    assign icache_req_valid = schedule_if.valid && ibuf_ready;
-    assign icache_req_addr  = schedule_if.data.PC[`MEM_ADDR_WIDTH-1:2];
-    assign icache_req_tag   = {schedule_if.data.uuid, req_tag};
-    assign schedule_if.ready = icache_req_ready && ibuf_ready;
-
-    VX_elastic_buffer #(
-        .DATAW   (ICACHE_ADDR_WIDTH + ICACHE_TAG_WIDTH),
-        .SIZE    (2),
-        .OUT_REG (1) // external bus should be registered
-    ) req_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (icache_req_valid),
-        .ready_in  (icache_req_ready),
-        .data_in   ({icache_req_addr, icache_req_tag}),
-        .data_out  ({icache_bus_if.req_data.addr, icache_bus_if.req_data.tag}),
-        .valid_out (icache_bus_if.req_valid),
-        .ready_out (icache_bus_if.req_ready)
-    );
-
-    assign icache_bus_if.req_data.rw     = 0;
-    assign icache_bus_if.req_data.byteen = 4'b1111;
-    assign icache_bus_if.req_data.data   = '0;    
-
-    // Icache Response
-
-    assign fetch_if.valid = icache_bus_if.rsp_valid;
-    assign fetch_if.data.tmask = rsp_tmask;
-    assign fetch_if.data.wid   = rsp_tag;
-    assign fetch_if.data.PC    = rsp_PC;
-    assign fetch_if.data.instr = icache_bus_if.rsp_data.data;
-    assign fetch_if.data.uuid  = rsp_uuid;
-    assign icache_bus_if.rsp_ready = fetch_if.ready;
-
-`ifdef DBG_SCOPE_FETCH
-    if (CORE_ID == 0) begin
-    `ifdef SCOPE
-        wire schedule_fire = schedule_if.valid && schedule_if.ready;
-        wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
-        VX_scope_tap #(
-            .SCOPE_ID (1),
-            .TRIGGERW (4),
-            .PROBEW   (3*`UUID_WIDTH + 108)
-        ) scope_tap (
-            .clk(clk),
-            .reset(scope_reset),
-            .start(1'b0),
-            .stop(1'b0),
-            .triggers({
-                reset,
-                schedule_fire,
-                icache_req_fire,
-                icache_rsp_fire
-            }),
-            .probes({
-                schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC,
-                icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr,
-                icache_bus_if.rsp_data.data, icache_bus_if.rsp_data.tag
-            }),
-            .bus_in(scope_bus_in),
-            .bus_out(scope_bus_out)
-        );
-    `endif
-    `ifdef CHIPSCOPE
-        ila_fetch ila_fetch_inst (
-            .clk    (clk),
-            .probe0 ({reset, schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC, schedule_if.ready, schedule_if.valid}),        
-            .probe1 ({icache_bus_if.req_data.tag, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr, icache_bus_if.req_ready, icache_bus_if.req_valid}),
-            .probe2 ({icache_bus_if.rsp_data.data, icache_bus_if.rsp_data.tag, icache_bus_if.rsp_ready, icache_bus_if.rsp_valid})
-        );
-    `endif
-    end
-`else
-    `SCOPE_IO_UNUSED()
-`endif
-
-`ifdef DBG_TRACE_CORE_ICACHE
-    wire schedule_fire = schedule_if.valid && schedule_if.ready;
-    wire fetch_fire = fetch_if.valid && fetch_if.ready;
-    always @(posedge clk) begin
-        if (schedule_fire) begin
-            `TRACE(1, ("%d: I$%0d req: wid=%0d, PC=0x%0h, tmask=%b (#%0d)\n", $time, CORE_ID, schedule_if.data.wid, schedule_if.data.PC, schedule_if.data.tmask, schedule_if.data.uuid));
-        end
-        if (fetch_fire) begin
-            `TRACE(1, ("%d: I$%0d rsp: wid=%0d, PC=0x%0h, tmask=%b, instr=0x%0h (#%0d)\n", $time, CORE_ID, fetch_if.data.wid, fetch_if.data.PC, fetch_if.data.tmask, fetch_if.data.instr, fetch_if.data.uuid));
-        end
-    end
-`endif
-
-endmodule

hw/rtl/core/VX_fpu_unit.sv

@@ -1,259 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-`include "VX_fpu_define.vh"
-
-module VX_fpu_unit import VX_fpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input wire clk,
-    input wire reset,
-
-    VX_dispatch_if.slave    dispatch_if [`ISSUE_WIDTH],
-    VX_fpu_to_csr_if.master fpu_to_csr_if[`NUM_FPU_BLOCKS],
-
-    VX_commit_if.master     commit_if [`ISSUE_WIDTH]
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam BLOCK_SIZE = `NUM_FPU_BLOCKS;
-    localparam NUM_LANES  = `NUM_FPU_LANES;
-    localparam PID_BITS   = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH  = `UP(PID_BITS);
-    localparam TAG_WIDTH  = `LOG2UP(`FPUQ_SIZE);
-    localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `NUM_THREADS);
-
-    VX_execute_if #(
-        .NUM_LANES (NUM_LANES)
-    ) execute_if[BLOCK_SIZE]();
-
-    `RESET_RELAY (dispatch_reset, reset);
-
-    VX_dispatch_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (PARTIAL_BW ? 1 : 0)
-    ) dispatch_unit (
-        .clk        (clk),
-        .reset      (dispatch_reset),
-        .dispatch_if(dispatch_if),
-        .execute_if (execute_if)
-    );
-
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) commit_block_if[BLOCK_SIZE]();
-
-    for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin
-        `UNUSED_VAR (execute_if[block_idx].data.tid)
-        `UNUSED_VAR (execute_if[block_idx].data.wb)
-        `UNUSED_VAR (execute_if[block_idx].data.use_PC)
-        `UNUSED_VAR (execute_if[block_idx].data.use_imm)
-
-        // Store request info
-        wire fpu_req_valid, fpu_req_ready;
-        wire fpu_rsp_valid, fpu_rsp_ready;    
-        wire [NUM_LANES-1:0][`XLEN-1:0] fpu_rsp_result;
-        fflags_t fpu_rsp_fflags;
-        wire fpu_rsp_has_fflags;
-
-        wire [`UUID_WIDTH-1:0]  fpu_rsp_uuid;
-        wire [`NW_WIDTH-1:0]    fpu_rsp_wid;
-        wire [NUM_LANES-1:0]    fpu_rsp_tmask;
-        wire [`XLEN-1:0]        fpu_rsp_PC;
-        wire [`NR_BITS-1:0]     fpu_rsp_rd;
-        wire [PID_WIDTH-1:0]    fpu_rsp_pid;
-        wire                    fpu_rsp_sop;
-        wire                    fpu_rsp_eop;
-
-        wire [TAG_WIDTH-1:0] fpu_req_tag, fpu_rsp_tag;    
-        wire mdata_full;
-
-        wire [`INST_FMT_BITS-1:0] fpu_fmt = execute_if[block_idx].data.imm[`INST_FMT_BITS-1:0];
-        wire [`INST_FRM_BITS-1:0] fpu_frm = execute_if[block_idx].data.op_mod[`INST_FRM_BITS-1:0];
-
-        wire execute_fire = execute_if[block_idx].valid && execute_if[block_idx].ready;
-        wire fpu_rsp_fire = fpu_rsp_valid && fpu_rsp_ready;
-
-        VX_index_buffer #(
-            .DATAW  (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + PID_WIDTH + 1 + 1),
-            .SIZE   (`FPUQ_SIZE)
-        ) tag_store (
-            .clk          (clk),
-            .reset        (reset),
-            .acquire_en   (execute_fire), 
-            .write_addr   (fpu_req_tag), 
-            .write_data   ({execute_if[block_idx].data.uuid, execute_if[block_idx].data.wid, execute_if[block_idx].data.tmask, execute_if[block_idx].data.PC, execute_if[block_idx].data.rd, execute_if[block_idx].data.pid, execute_if[block_idx].data.sop, execute_if[block_idx].data.eop}),
-            .read_data    ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}),
-            .read_addr    (fpu_rsp_tag),
-            .release_en   (fpu_rsp_fire), 
-            .full         (mdata_full),
-            `UNUSED_PIN (empty)
-        );
-
-        // resolve dynamic FRM from CSR   
-        wire [`INST_FRM_BITS-1:0] fpu_req_frm; 
-        `ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].read_wid, execute_if[block_idx].data.wid, block_idx, `NUM_FPU_BLOCKS)
-        assign fpu_req_frm = (execute_if[block_idx].data.op_type != `INST_FPU_MISC 
-                           && fpu_frm == `INST_FRM_DYN) ? fpu_to_csr_if[block_idx].read_frm : fpu_frm;
-
-        // submit FPU request
-
-        assign fpu_req_valid = execute_if[block_idx].valid && ~mdata_full;
-        assign execute_if[block_idx].ready = fpu_req_ready && ~mdata_full;
-
-        `RESET_RELAY (fpu_reset, reset);   
-
-    `ifdef FPU_DPI
-
-        VX_fpu_dpi #(
-            .NUM_LANES  (NUM_LANES),
-            .TAGW       (TAG_WIDTH),
-            .OUT_REG    (PARTIAL_BW ? 1 : 3)
-        ) fpu_dpi (
-            .clk        (clk),
-            .reset      (fpu_reset),
-
-            .valid_in   (fpu_req_valid),
-            .op_type    (execute_if[block_idx].data.op_type),
-            .lane_mask  (execute_if[block_idx].data.tmask),
-            .fmt        (fpu_fmt),
-            .frm        (fpu_req_frm),
-            .dataa      (execute_if[block_idx].data.rs1_data),
-            .datab      (execute_if[block_idx].data.rs2_data),
-            .datac      (execute_if[block_idx].data.rs3_data),
-            .tag_in     (fpu_req_tag),
-            .ready_in   (fpu_req_ready),
-
-            .valid_out  (fpu_rsp_valid),
-            .result     (fpu_rsp_result),
-            .has_fflags (fpu_rsp_has_fflags),
-            .fflags     (fpu_rsp_fflags),
-            .tag_out    (fpu_rsp_tag),
-            .ready_out  (fpu_rsp_ready)     
-        );   
-
-    `elsif FPU_FPNEW
-
-        VX_fpu_fpnew #(
-            .NUM_LANES  (NUM_LANES),
-            .TAGW       (TAG_WIDTH),
-            .OUT_REG    (PARTIAL_BW ? 1 : 3)
-        ) fpu_fpnew (
-            .clk        (clk),
-            .reset      (fpu_reset), 
-
-            .valid_in   (fpu_req_valid),
-            .op_type    (execute_if[block_idx].data.op_type),
-            .lane_mask  (execute_if[block_idx].data.tmask),
-            .fmt        (fpu_fmt),
-            .frm        (fpu_req_frm),
-            .dataa      (execute_if[block_idx].data.rs1_data),
-            .datab      (execute_if[block_idx].data.rs2_data),
-            .datac      (execute_if[block_idx].data.rs3_data), 
-            .tag_in     (fpu_req_tag),
-            .ready_in   (fpu_req_ready),
-
-            .valid_out  (fpu_rsp_valid), 
-            .result     (fpu_rsp_result),
-            .has_fflags (fpu_rsp_has_fflags),
-            .fflags     (fpu_rsp_fflags),
-            .tag_out    (fpu_rsp_tag), 
-            .ready_out  (fpu_rsp_ready)        
-        );
-
-    `elsif FPU_DSP
-
-        VX_fpu_dsp #(
-            .NUM_LANES  (NUM_LANES),
-            .TAGW       (TAG_WIDTH),
-            .OUT_REG    (PARTIAL_BW ? 1 : 3)
-        ) fpu_dsp (
-            .clk        (clk),
-            .reset      (fpu_reset), 
-
-            .valid_in   (fpu_req_valid),
-            .lane_mask  (execute_if[block_idx].data.tmask),
-            .op_type    (execute_if[block_idx].data.op_type),
-            .fmt        (fpu_fmt),
-            .frm        (fpu_req_frm),
-            .dataa      (execute_if[block_idx].data.rs1_data),
-            .datab      (execute_if[block_idx].data.rs2_data),
-            .datac      (execute_if[block_idx].data.rs3_data), 
-            .tag_in     (fpu_req_tag),
-            .ready_in   (fpu_req_ready),
-
-            .valid_out  (fpu_rsp_valid), 
-            .result     (fpu_rsp_result), 
-            .has_fflags (fpu_rsp_has_fflags),
-            .fflags     (fpu_rsp_fflags),
-            .tag_out    (fpu_rsp_tag),
-            .ready_out  (fpu_rsp_ready)
-        );
-        
-    `endif
-
-        // handle FPU response
-
-        fflags_t fpu_rsp_fflags_q;
-
-        if (PID_BITS != 0) begin
-            fflags_t fpu_rsp_fflags_r;
-            always @(posedge clk) begin
-                if (reset) begin
-                    fpu_rsp_fflags_r <= '0;
-                end else if (fpu_rsp_fire) begin
-                    fpu_rsp_fflags_r <= fpu_rsp_eop ? '0 : (fpu_rsp_fflags_r | fpu_rsp_fflags);
-                end
-            end
-            assign fpu_rsp_fflags_q = fpu_rsp_fflags_r | fpu_rsp_fflags;
-        end else begin
-            assign fpu_rsp_fflags_q = fpu_rsp_fflags;
-        end
-        
-        assign fpu_to_csr_if[block_idx].write_enable = fpu_rsp_fire && fpu_rsp_eop && fpu_rsp_has_fflags;
-        `ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].write_wid, fpu_rsp_wid, block_idx, `NUM_FPU_BLOCKS)
-        assign fpu_to_csr_if[block_idx].write_fflags = fpu_rsp_fflags_q;
-
-        // send response
-
-        VX_elastic_buffer #(
-            .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + (NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1),
-            .SIZE  (0)
-        ) rsp_buf (
-            .clk       (clk),
-            .reset     (reset),
-            .valid_in  (fpu_rsp_valid),
-            .ready_in  (fpu_rsp_ready),
-            .data_in   ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_result, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop}),
-            .data_out  ({commit_block_if[block_idx].data.uuid, commit_block_if[block_idx].data.wid, commit_block_if[block_idx].data.tmask, commit_block_if[block_idx].data.PC, commit_block_if[block_idx].data.rd, commit_block_if[block_idx].data.data, commit_block_if[block_idx].data.pid, commit_block_if[block_idx].data.sop, commit_block_if[block_idx].data.eop}),
-            .valid_out (commit_block_if[block_idx].valid),
-            .ready_out (commit_block_if[block_idx].ready)
-        );
-        assign commit_block_if[block_idx].data.wb = 1'b1;
-    end
-
-    `RESET_RELAY (commit_reset, reset);
-
-    VX_gather_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (PARTIAL_BW ? 3 : 0)
-    ) gather_unit (
-        .clk           (clk),
-        .reset         (commit_reset),
-        .commit_in_if  (commit_block_if),
-        .commit_out_if (commit_if)
-    );
-
-endmodule

hw/rtl/core/VX_gather_unit.sv

@@ -1,129 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_gather_unit import VX_gpu_pkg::*; #(
-    parameter BLOCK_SIZE = 1,
-    parameter NUM_LANES  = 1,
-    parameter OUT_REG    = 0
-) ( 
-    input  wire         clk,
-    input  wire         reset,
-
-    // inputs
-    VX_commit_if.slave  commit_in_if [BLOCK_SIZE],
-    
-    // outputs
-    VX_commit_if.master commit_out_if [`ISSUE_WIDTH]
-
-);
-    localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE);
-    localparam PID_BITS     = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH    = `UP(PID_BITS);
-    localparam DATAW        = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + 1 + `NR_BITS + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1;
-    localparam DATA_WIS_OFF = DATAW - (`UUID_WIDTH + `NW_WIDTH);
-
-    wire [BLOCK_SIZE-1:0] commit_in_valid;
-    wire [BLOCK_SIZE-1:0][DATAW-1:0] commit_in_data;
-    wire [BLOCK_SIZE-1:0] commit_in_ready;
-    wire [BLOCK_SIZE-1:0][ISSUE_ISW_W-1:0] commit_in_isw;
-
-    for (genvar i = 0; i < BLOCK_SIZE; ++i) begin
-        assign commit_in_valid[i] = commit_in_if[i].valid;
-        assign commit_in_data[i] = commit_in_if[i].data;
-        assign commit_in_if[i].ready = commit_in_ready[i];
-        if (BLOCK_SIZE != `ISSUE_WIDTH) begin
-            if (BLOCK_SIZE != 1) begin
-                assign commit_in_isw[i] = {commit_in_data[i][DATA_WIS_OFF+BLOCK_SIZE_W +: (ISSUE_ISW_W-BLOCK_SIZE_W)], BLOCK_SIZE_W'(i)};
-            end else begin
-                assign commit_in_isw[i] = commit_in_data[i][DATA_WIS_OFF +: ISSUE_ISW_W];
-            end
-        end else begin
-            assign commit_in_isw[i] = BLOCK_SIZE_W'(i);
-        end
-    end
-
-    reg [`ISSUE_WIDTH-1:0] commit_out_valid;
-    reg [`ISSUE_WIDTH-1:0][DATAW-1:0] commit_out_data;
-    wire [`ISSUE_WIDTH-1:0] commit_out_ready;
-
-    always @(*) begin
-        commit_out_valid = '0;
-        for (integer i = 0; i < `ISSUE_WIDTH; ++i) begin
-            commit_out_data[i] = 'x;
-        end
-        for (integer i = 0; i < BLOCK_SIZE; ++i) begin
-            commit_out_valid[commit_in_isw[i]] = commit_in_valid[i];
-            commit_out_data[commit_in_isw[i]] = commit_in_data[i];
-        end
-    end
-    for (genvar i = 0; i < BLOCK_SIZE; ++i) begin
-        assign commit_in_ready[i] = commit_out_ready[commit_in_isw[i]];
-    end
-    
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        VX_commit_if #(
-            .NUM_LANES (NUM_LANES)
-        ) commit_tmp_if();
-
-        `RESET_RELAY(commit_out_reset, reset);
-
-        VX_elastic_buffer #(
-            .DATAW   (DATAW),
-            .SIZE    (`OUT_REG_TO_EB_SIZE(OUT_REG)),
-            .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
-        ) out_buf (
-            .clk        (clk),
-            .reset      (commit_out_reset),
-            .valid_in   (commit_out_valid[i]),
-            .ready_in   (commit_out_ready[i]),
-            .data_in    (commit_out_data[i]),            
-            .data_out   (commit_tmp_if.data),
-            .valid_out  (commit_tmp_if.valid),
-            .ready_out  (commit_tmp_if.ready)
-        );
-
-        logic [`NUM_THREADS-1:0] commit_tmask_r;
-        logic [`NUM_THREADS-1:0][`XLEN-1:0] commit_data_r;
-        if (PID_BITS != 0) begin
-            always @(*) begin
-                commit_tmask_r = '0;
-                commit_data_r  = 'x;
-                for (integer j = 0; j < NUM_LANES; ++j) begin
-                    commit_tmask_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.tmask[j];
-                    commit_data_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.data[j];
-                end
-            end
-        end else begin
-            assign commit_tmask_r = commit_tmp_if.data.tmask;
-            assign commit_data_r = commit_tmp_if.data.data;
-        end
-
-        assign commit_out_if[i].valid = commit_tmp_if.valid;
-        assign commit_out_if[i].data = {
-            commit_tmp_if.data.uuid,
-            commit_tmp_if.data.wid,
-            commit_tmask_r,
-            commit_tmp_if.data.PC,
-            commit_tmp_if.data.wb,
-            commit_tmp_if.data.rd,
-            commit_data_r,
-            1'b0, // PID
-            commit_tmp_if.data.sop,
-            commit_tmp_if.data.eop
-        };
-        assign commit_tmp_if.ready = commit_out_if[i].ready;
-    end
-
-endmodule

hw/rtl/core/VX_ibuffer.sv

@@ -1,74 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_ibuffer import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input wire          clk,
-    input wire          reset,
-
-    // inputs
-    VX_decode_if.slave  decode_if,
-
-    // outputs
-    VX_ibuffer_if.master ibuffer_if [`ISSUE_WIDTH]
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam ISW_WIDTH  = `LOG2UP(`ISSUE_WIDTH);
-    localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4);
-    
-    wire [`ISSUE_WIDTH-1:0] ibuf_ready_in;
-
-    wire [ISW_WIDTH-1:0] decode_isw = wid_to_isw(decode_if.data.wid);
-    wire [ISSUE_WIS_W-1:0] decode_wis = wid_to_wis(decode_if.data.wid);
-    
-    assign decode_if.ready = ibuf_ready_in[decode_isw];
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        VX_elastic_buffer #(
-            .DATAW   (DATAW),
-            .SIZE    (`IBUF_SIZE),
-            .OUT_REG (1)
-        ) instr_buf (
-            .clk      (clk),
-            .reset    (reset),
-            .valid_in (decode_if.valid && decode_isw == i),
-            .ready_in (ibuf_ready_in[i]),
-            .data_in  ({
-                decode_if.data.uuid,
-                decode_wis,
-                decode_if.data.tmask,
-                decode_if.data.ex_type,
-                decode_if.data.op_type,
-                decode_if.data.op_mod,
-                decode_if.data.wb,
-                decode_if.data.use_PC,
-                decode_if.data.use_imm,
-                decode_if.data.PC,
-                decode_if.data.imm,
-                decode_if.data.rd, 
-                decode_if.data.rs1, 
-                decode_if.data.rs2, 
-                decode_if.data.rs3}),
-            .data_out(ibuffer_if[i].data),
-            .valid_out (ibuffer_if[i].valid),
-            .ready_out(ibuffer_if[i].ready)
-        );        
-    `ifndef L1_ENABLE
-        assign decode_if.ibuf_pop[i] = ibuffer_if[i].valid && ibuffer_if[i].ready;
-    `endif
-    end
-
-endmodule

hw/rtl/core/VX_int_unit.sv

@@ -1,191 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_int_unit #(
-    parameter CORE_ID   = 0,
-    parameter BLOCK_IDX = 0,
-    parameter NUM_LANES = 1
-) (
-    input wire              clk,
-    input wire              reset,
-    
-    // Inputs
-    VX_execute_if.slave     execute_if,
-
-    // Outputs    
-    VX_commit_if.master     commit_if,
-    VX_branch_ctl_if.master branch_ctl_if
-);   
-
-    `UNUSED_PARAM (CORE_ID)
-    localparam LANE_BITS      = `CLOG2(NUM_LANES);
-    localparam LANE_WIDTH     = `UP(LANE_BITS);
-    localparam PID_BITS       = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH      = `UP(PID_BITS);
-    localparam SHIFT_IMM_BITS = `CLOG2(`XLEN);
-
-    `UNUSED_VAR (execute_if.data.rs3_data)
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] add_result;
-    wire [NUM_LANES-1:0][`XLEN:0]   sub_result; // +1 bit for branch compare
-    wire [NUM_LANES-1:0][`XLEN-1:0] shr_result;
-    reg  [NUM_LANES-1:0][`XLEN-1:0] msc_result;
-    
-    wire [NUM_LANES-1:0][`XLEN-1:0] add_result_w;
-    wire [NUM_LANES-1:0][`XLEN-1:0] sub_result_w;
-    wire [NUM_LANES-1:0][`XLEN-1:0] shr_result_w;
-    reg  [NUM_LANES-1:0][`XLEN-1:0] msc_result_w;
-
-    reg [NUM_LANES-1:0][`XLEN-1:0] alu_result;
-    wire [NUM_LANES-1:0][`XLEN-1:0] alu_result_r;
-
-`ifdef XLEN_64
-    wire is_alu_w = `INST_ALU_IS_W(execute_if.data.op_mod);
-`else
-    wire is_alu_w = 0;
-`endif
-
-    `UNUSED_VAR (execute_if.data.op_mod)
-
-    wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(execute_if.data.op_type);
-    wire [`INST_BR_BITS-1:0]   br_op = `INST_BR_BITS'(execute_if.data.op_type);
-    wire                    is_br_op = `INST_ALU_IS_BR(execute_if.data.op_mod);
-    wire                   is_sub_op = `INST_ALU_IS_SUB(alu_op);
-    wire                   is_signed = `INST_ALU_SIGNED(alu_op);   
-    wire [1:0]              op_class = is_br_op ? `INST_BR_CLASS(alu_op) : `INST_ALU_CLASS(alu_op);
-    
-    wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1 = execute_if.data.rs1_data;
-    wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2 = execute_if.data.rs2_data;
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1_PC  = execute_if.data.use_PC ? {NUM_LANES{execute_if.data.PC}} : alu_in1;
-    wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_imm = execute_if.data.use_imm ? {NUM_LANES{execute_if.data.imm}} : alu_in2;
-    wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_br  = (execute_if.data.use_imm && ~is_br_op) ? {NUM_LANES{execute_if.data.imm}} : alu_in2;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];
-        assign add_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] + alu_in2_imm[i][31:0]));
-    end
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [`XLEN:0] sub_in1 = {is_signed & alu_in1[i][`XLEN-1], alu_in1[i]};
-        wire [`XLEN:0] sub_in2 = {is_signed & alu_in2_br[i][`XLEN-1], alu_in2_br[i]};
-        assign sub_result[i] = sub_in1 - sub_in2;
-        assign sub_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] - alu_in2_imm[i][31:0]));
-    end
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin    
-        wire [`XLEN:0] shr_in1 = {is_signed && alu_in1[i][`XLEN-1], alu_in1[i]};        
-        assign shr_result[i] = `XLEN'($signed(shr_in1) >>> alu_in2_imm[i][SHIFT_IMM_BITS-1:0]);
-        wire [32:0] shr_in1_w = {is_signed && alu_in1[i][31], alu_in1[i][31:0]};
-        wire [31:0] shr_res_w = 32'($signed(shr_in1_w) >>> alu_in2_imm[i][4:0]);
-        assign shr_result_w[i] = `XLEN'($signed(shr_res_w));
-    end
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            case (alu_op[1:0])
-                2'b00: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; // AND
-                2'b01: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; // OR
-                2'b10: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; // XOR
-                2'b11: msc_result[i] = alu_in1[i] << alu_in2_imm[i][SHIFT_IMM_BITS-1:0]; // SLL
-            endcase
-        end
-        assign msc_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] << alu_in2_imm[i][4:0]));
-    end
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [`XLEN-1:0] slt_br_result = `XLEN'({is_br_op && ~(| sub_result[i][`XLEN-1:0]), sub_result[i][`XLEN]});
-        wire [`XLEN-1:0] sub_slt_br_result = (is_sub_op && ~is_br_op) ? sub_result[i][`XLEN-1:0] : slt_br_result;
-        always @(*) begin
-            case ({is_alu_w, op_class})                        
-                3'b000: alu_result[i] = add_result[i];      // ADD, LUI, AUIPC
-                3'b001: alu_result[i] = sub_slt_br_result;  // SUB, SLTU, SLTI, BR*
-                3'b010: alu_result[i] = shr_result[i];      // SRL, SRA, SRLI, SRAI
-                3'b011: alu_result[i] = msc_result[i];      // AND, OR, XOR, SLL, SLLI
-                3'b100: alu_result[i] = add_result_w[i];    // ADDIW, ADDW
-                3'b101: alu_result[i] = sub_result_w[i];    // SUBW
-                3'b110: alu_result[i] = shr_result_w[i];    // SRLW, SRAW, SRLIW, SRAIW
-                3'b111: alu_result[i] = msc_result_w[i];    // SLLW
-            endcase
-        end       
-    end
-
-    // branch
-
-    wire [`XLEN-1:0] PC_r, imm_r;
-    wire [`INST_BR_BITS-1:0] br_op_r;
-    wire [LANE_WIDTH-1:0] tid, tid_r;
-    wire is_br_op_r;
-
-    if (LANE_BITS != 0) begin
-        assign tid = execute_if.data.tid[0 +: LANE_BITS];
-    end else begin
-        assign tid = 0;
-    end   
-
-    VX_elastic_buffer #(
-        .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `NR_BITS + 1 + PID_WIDTH + 1 + 1 + (NUM_LANES * `XLEN) + `XLEN + `XLEN + 1 + `INST_BR_BITS + LANE_WIDTH)
-    ) rsp_buf (
-        .clk      (clk),
-        .reset    (reset),
-        .valid_in (execute_if.valid),
-        .ready_in (execute_if.ready),
-        .data_in  ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, alu_result, execute_if.data.PC, execute_if.data.imm, is_br_op, br_op, tid}),
-        .data_out ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.rd, commit_if.data.wb, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop, alu_result_r, PC_r, imm_r, is_br_op_r, br_op_r, tid_r}),
-        .valid_out (commit_if.valid),
-        .ready_out (commit_if.ready)
-    );
-
-    `UNUSED_VAR (br_op_r)
-    wire is_br_neg  = `INST_BR_IS_NEG(br_op_r);
-    wire is_br_less = `INST_BR_IS_LESS(br_op_r);
-    wire is_br_static = `INST_BR_IS_STATIC(br_op_r);
-    wire [`XLEN-1:0] br_result = alu_result_r[tid_r];
-
-    wire is_less  = br_result[0];
-    wire is_equal = br_result[1];
-
-    wire br_enable = is_br_op_r && commit_if.valid && commit_if.ready && commit_if.data.eop;
-    wire br_taken = ((is_br_less ? is_less : is_equal) ^ is_br_neg) | is_br_static;
-    wire [`XLEN-1:0] br_dest = is_br_static ? br_result : (PC_r + imm_r);
-    wire [`NW_WIDTH-1:0] br_wid;
-    `ASSIGN_BLOCKED_WID (br_wid, commit_if.data.wid, BLOCK_IDX, `NUM_ALU_BLOCKS)
-
-    VX_pipe_register #(
-        .DATAW (1 + `NW_WIDTH + 1 + `XLEN)
-    ) branch_reg (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (1'b1),
-        .data_in  ({br_enable, br_wid, br_taken, br_dest}),
-        .data_out ({branch_ctl_if.valid, branch_ctl_if.wid, branch_ctl_if.taken, branch_ctl_if.dest})
-    );
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin    
-        assign commit_if.data.data[i] = (is_br_op_r && is_br_static) ? (PC_r + 4) : alu_result_r[i];
-    end
-
-    assign commit_if.data.PC = PC_r;
- 
-`ifdef DBG_TRACE_CORE_PIPELINE
-    always @(posedge clk) begin
-        if (branch_ctl_if.valid) begin
-            `TRACE(1, ("%d: core%0d-branch: wid=%0d, PC=0x%0h, taken=%b, dest=0x%0h (#%0d)\n",
-                $time, CORE_ID, branch_ctl_if.wid, commit_if.data.PC, branch_ctl_if.taken, branch_ctl_if.dest, commit_if.data.uuid));
-        end
-    end
-`endif
-
-endmodule

hw/rtl/core/VX_ipdom_stack.sv

@@ -1,108 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_platform.vh"
-
-module VX_ipdom_stack #(
-    parameter WIDTH   = 1,
-    parameter DEPTH   = 1,
-    parameter OUT_REG = 0,
-    parameter ADDRW   = `LOG2UP(DEPTH)
-) (
-    input  wire             clk,
-    input  wire             reset,
-    input  wire [WIDTH-1:0] q0,
-    input  wire [WIDTH-1:0] q1,
-    output wire [WIDTH-1:0] d,
-    output wire             d_set,    
-    input  wire             push,
-    input  wire             pop,    
-    output wire             empty,
-    output wire             full
-);
-    reg slot_set [DEPTH-1:0];
-    
-    reg [ADDRW-1:0] rd_ptr, wr_ptr;
-
-    reg empty_r, full_r;
-
-    wire [WIDTH-1:0] d0, d1;
-
-    wire d_set_n = slot_set[rd_ptr];
-
-    always @(posedge clk) begin
-        if (reset) begin   
-            rd_ptr  <= '0;
-            wr_ptr  <= '0;
-            empty_r <= 1;
-            full_r  <= 0; 
-        end else begin
-            `ASSERT(~push || ~full, ("runtime error: writing to a full stack!"));
-            `ASSERT(~pop || ~empty, ("runtime error: reading an empty stack!"));
-            `ASSERT(~push || ~pop,  ("runtime error: push and pop in same cycle not supported!"));
-            if (push) begin                
-                rd_ptr  <= wr_ptr;
-                wr_ptr  <= wr_ptr + ADDRW'(1);                
-                empty_r <= 0;
-                full_r  <= (ADDRW'(DEPTH-1) == wr_ptr);
-            end else if (pop) begin                   
-                wr_ptr  <= wr_ptr - ADDRW'(d_set_n);
-                rd_ptr  <= rd_ptr - ADDRW'(d_set_n);
-                empty_r <= (rd_ptr == 0) && (d_set_n == 1);
-                full_r  <= 0;
-            end
-        end
-    end    
-
-    VX_dp_ram #(
-        .DATAW   (WIDTH * 2),
-        .SIZE    (DEPTH),
-        .OUT_REG (OUT_REG ? 1 : 0),
-        .LUTRAM  (OUT_REG ? 0 : 1)
-    ) store (
-        .clk   (clk),
-        .read  (1'b1),
-        .write (push),        
-        `UNUSED_PIN (wren),               
-        .waddr (wr_ptr),
-        .wdata ({q1, q0}),
-        .raddr (rd_ptr),
-        .rdata ({d1, d0})
-    );
-    
-    always @(posedge clk) begin
-        if (push) begin
-            slot_set[wr_ptr] <= 0;   
-        end else if (pop) begin            
-            slot_set[rd_ptr] <= 1;
-        end
-    end
-
-    wire d_set_r;
-    VX_pipe_register #(
-        .DATAW (1),
-        .DEPTH (OUT_REG)
-    ) pipe_reg (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (1'b1),
-        .data_in  (d_set_n),
-        .data_out (d_set_r)
-    );
-
-    assign d     = d_set_r ? d0 : d1;
-    assign d_set = ~d_set_r;
-    assign empty = empty_r;
-    assign full  = full_r;
-
-endmodule

hw/rtl/core/VX_issue.sv

@@ -1,174 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-`include "VX_trace.vh"
-
-module VX_issue #(
-    parameter CORE_ID = 0
-) (
-    `SCOPE_IO_DECL
-
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    VX_pipeline_perf_if.issue perf_issue_if,
-`endif
-
-    VX_decode_if.slave      decode_if,
-    VX_writeback_if.slave   writeback_if [`ISSUE_WIDTH],
-
-    VX_dispatch_if.master   alu_dispatch_if [`ISSUE_WIDTH],
-    VX_dispatch_if.master   lsu_dispatch_if [`ISSUE_WIDTH],
-`ifdef EXT_F_ENABLE
-    VX_dispatch_if.master   fpu_dispatch_if [`ISSUE_WIDTH],
-`endif
-    VX_dispatch_if.master   sfu_dispatch_if [`ISSUE_WIDTH]
-);
-    VX_ibuffer_if  ibuffer_if [`ISSUE_WIDTH]();
-    VX_ibuffer_if  scoreboard_if [`ISSUE_WIDTH]();
-    VX_operands_if operands_if [`ISSUE_WIDTH]();
-
-    `RESET_RELAY (ibuf_reset, reset);
-    `RESET_RELAY (scoreboard_reset, reset);
-    `RESET_RELAY (operands_reset, reset);
-    `RESET_RELAY (dispatch_reset, reset);
-
-    VX_ibuffer #(
-        .CORE_ID (CORE_ID)
-    ) ibuffer (
-        .clk            (clk),
-        .reset          (ibuf_reset), 
-        .decode_if      (decode_if),
-        .ibuffer_if     (ibuffer_if)
-    );
-
-    VX_scoreboard #(
-        .CORE_ID (CORE_ID)
-    ) scoreboard (
-        .clk            (clk),
-        .reset          (scoreboard_reset),
-    `ifdef PERF_ENABLE
-        .perf_scb_stalls(perf_issue_if.scb_stalls),
-        .perf_units_uses(perf_issue_if.units_uses),
-        .perf_sfu_uses  (perf_issue_if.sfu_uses),
-    `endif
-        .writeback_if   (writeback_if),
-        .ibuffer_if     (ibuffer_if),
-        .scoreboard_if  (scoreboard_if)
-    );
-
-    VX_operands #(
-        .CORE_ID (CORE_ID)
-    ) operands (
-        .clk            (clk), 
-        .reset          (operands_reset), 
-        .writeback_if   (writeback_if),
-        .scoreboard_if  (scoreboard_if),
-        .operands_if    (operands_if)
-    );
-
-    VX_dispatch #(
-        .CORE_ID (CORE_ID)
-    ) dispatch (
-        .clk            (clk), 
-        .reset          (dispatch_reset),
-    `ifdef PERF_ENABLE
-        `UNUSED_PIN     (perf_stalls),
-    `endif
-        .operands_if    (operands_if),
-        .alu_dispatch_if(alu_dispatch_if),
-        .lsu_dispatch_if(lsu_dispatch_if),
-    `ifdef EXT_F_ENABLE
-        .fpu_dispatch_if(fpu_dispatch_if),
-    `endif
-        .sfu_dispatch_if(sfu_dispatch_if)
-    ); 
-
-`ifdef DBG_SCOPE_ISSUE
-    if (CORE_ID == 0) begin
-    `ifdef SCOPE
-        wire operands_if_fire = operands_if[0].valid && operands_if[0].ready;
-        wire operands_if_not_ready = ~operands_if[0].ready;
-        wire writeback_if_valid = writeback_if[0].valid;
-        VX_scope_tap #(
-            .SCOPE_ID (2),
-            .TRIGGERW (4),
-            .PROBEW   (`UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS +
-                1 + `NR_BITS + `XLEN + 1 + 1 + (`NUM_THREADS * 3 * `XLEN) +
-                `UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1)
-        ) scope_tap (
-            .clk(clk),
-            .reset(scope_reset),
-            .start(1'b0),
-            .stop(1'b0),
-            .triggers({
-                reset, 
-                operands_if_fire,
-                operands_if_not_ready, 
-                writeback_if_valid
-            }),
-            .probes({
-                operands_if[0].data.uuid,
-                operands_if[0].data.tmask,
-                operands_if[0].data.ex_type,
-                operands_if[0].data.op_type,
-                operands_if[0].data.op_mod,
-                operands_if[0].data.wb,
-                operands_if[0].data.rd,
-                operands_if[0].data.imm,
-                operands_if[0].data.use_PC,
-                operands_if[0].data.use_imm,
-                operands_if[0].data.rs1_data,
-                operands_if[0].data.rs2_data,
-                operands_if[0].data.rs3_data,
-                writeback_if[0].data.uuid,
-                writeback_if[0].data.tmask,
-                writeback_if[0].data.rd,
-                writeback_if[0].data.data,
-                writeback_if[0].data.eop
-            }),
-            .bus_in(scope_bus_in),
-            .bus_out(scope_bus_out)
-        );
-    `endif        
-    `ifdef CHIPSCOPE
-        ila_issue ila_issue_inst (
-            .clk    (clk),
-            .probe0 ({operands_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, operands_if.PC, operands_if.tmask, operands_if.wid, operands_if.ex_type, operands_if.op_type, operands_if.ready, operands_if.valid}),
-            .probe1 ({writeback_if.uuid, writeback_if.data[0], writeback_if.PC, writeback_if.tmask, writeback_if.wid, writeback_if.eop, writeback_if.valid})
-        );
-    `endif
-    end
-`else
-    `SCOPE_IO_UNUSED()
-`endif
-
-`ifdef PERF_ENABLE
-    reg [`PERF_CTR_BITS-1:0] perf_ibf_stalls;
-    
-    wire decode_stall = decode_if.valid && ~decode_if.ready;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_ibf_stalls <= '0;
-        end else begin
-            perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'(decode_stall);
-        end
-    end
-
-    assign perf_issue_if.ibf_stalls = perf_ibf_stalls;
-`endif
-
-endmodule

hw/rtl/core/VX_lsu_unit.sv

@@ -1,647 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_lsu_unit import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (    
-    `SCOPE_IO_DECL
-
-   input wire               clk,
-    input wire              reset,
-
-   // Dcache interface
-    VX_mem_bus_if.master    cache_bus_if [DCACHE_NUM_REQS],
-
-    // inputs
-    VX_dispatch_if.slave    dispatch_if [`ISSUE_WIDTH],
-
-    // outputs    
-    VX_commit_if.master     commit_if [`ISSUE_WIDTH]
-);
-    localparam BLOCK_SIZE   = 1;
-    localparam NUM_LANES    = `NUM_LSU_LANES;
-    localparam PID_BITS     = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH    = `UP(PID_BITS);
-    localparam RSP_ARB_DATAW= `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1;
-    localparam LSUQ_SIZEW   = `LOG2UP(`LSUQ_SIZE);
-    localparam MEM_ASHIFT   = `CLOG2(`MEM_BLOCK_SIZE);    
-    localparam MEM_ADDRW    = `XLEN - MEM_ASHIFT;
-    localparam REQ_ASHIFT   = `CLOG2(DCACHE_WORD_SIZE);
-    localparam CACHE_TAG_WIDTH = `UUID_WIDTH + (NUM_LANES * `CACHE_ADDR_TYPE_BITS) + LSUQ_TAG_BITS;
-
-    VX_execute_if #(
-        .NUM_LANES (NUM_LANES)
-    ) execute_if[BLOCK_SIZE]();
-
-    `RESET_RELAY (dispatch_reset, reset);
-
-    VX_dispatch_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (1)
-    ) dispatch_unit (
-        .clk        (clk),
-        .reset      (dispatch_reset),
-        .dispatch_if(dispatch_if),
-        .execute_if (execute_if)
-    );
-
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) commit_st_if();
-    
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) commit_ld_if();
-    
-    `UNUSED_VAR (execute_if[0].data.op_mod)     
-    `UNUSED_VAR (execute_if[0].data.use_PC)
-    `UNUSED_VAR (execute_if[0].data.use_imm)
-    `UNUSED_VAR (execute_if[0].data.rs3_data)
-    `UNUSED_VAR (execute_if[0].data.tid)
-
-`ifdef SM_ENABLE
-    `STATIC_ASSERT((1 << `SMEM_LOG_SIZE) == `MEM_BLOCK_SIZE * ((1 << `SMEM_LOG_SIZE) / `MEM_BLOCK_SIZE), ("invalid parameter"))
-    `STATIC_ASSERT(0 == (`SMEM_BASE_ADDR % (1 << `SMEM_LOG_SIZE)), ("invalid parameter"))
-    localparam SMEM_START_B = MEM_ADDRW'(`XLEN'(`SMEM_BASE_ADDR) >> MEM_ASHIFT);
-    localparam SMEM_END_B = MEM_ADDRW'((`XLEN'(`SMEM_BASE_ADDR) + (1 << `SMEM_LOG_SIZE)) >> MEM_ASHIFT);
-`endif
-
-    // tag = uuid + addr_type + wid + PC + tmask + rd + op_type + align + is_dup + pid + pkt_addr 
-    localparam TAG_WIDTH = `UUID_WIDTH + (NUM_LANES * `CACHE_ADDR_TYPE_BITS) + `NW_WIDTH + `XLEN + NUM_LANES + `NR_BITS + `INST_LSU_BITS + (NUM_LANES * (REQ_ASHIFT)) + `LSU_DUP_ENABLED + PID_WIDTH + LSUQ_SIZEW;
-
-    `STATIC_ASSERT(0 == (`IO_BASE_ADDR % `MEM_BLOCK_SIZE), ("invalid parameter"))
-
-    wire [NUM_LANES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] lsu_addr_type;
-
-    // full address calculation
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] full_addr;    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign full_addr[i] = execute_if[0].data.rs1_data[i][`XLEN-1:0] + execute_if[0].data.imm;
-    end
-
-    // detect duplicate addresses
-
-    wire lsu_is_dup;
-`ifdef LSU_DUP_ENABLE
-    if (NUM_LANES > 1) begin    
-        wire [NUM_LANES-2:0] addr_matches;
-        for (genvar i = 0; i < (NUM_LANES-1); ++i) begin
-            assign addr_matches[i] = (execute_if[0].data.rs1_data[i+1] == execute_if[0].data.rs1_data[0]) || ~execute_if[0].data.tmask[i+1];
-        end
-        assign lsu_is_dup = execute_if[0].data.tmask[0] && (& addr_matches);
-    end else begin
-        assign lsu_is_dup = 0;
-    end
-`else
-    assign lsu_is_dup = 0;
-`endif
-
-    // detect address type
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [MEM_ADDRW-1:0] full_addr_b = full_addr[i][MEM_ASHIFT +: MEM_ADDRW];
-        // is non-cacheable I/O address
-        wire is_addr_io = (full_addr_b >= MEM_ADDRW'(`XLEN'(`IO_BASE_ADDR) >> MEM_ASHIFT));
-    `ifdef SM_ENABLE
-        // is shared memory address
-        wire is_addr_sm = (full_addr_b >= SMEM_START_B) && (full_addr_b < SMEM_END_B);
-        assign lsu_addr_type[i] = {is_addr_io, is_addr_sm};
-    `else
-        assign lsu_addr_type[i] = is_addr_io;
-    `endif
-    end
-
-    wire mem_req_empty;
-    wire st_rsp_ready;
-    wire lsu_valid, lsu_ready;
-
-    // fence: stall the pipeline until all pending requests are sent
-    wire is_fence = `INST_LSU_IS_FENCE(execute_if[0].data.op_type);
-    wire fence_wait = is_fence && ~mem_req_empty;
-    
-    assign lsu_valid = execute_if[0].valid && ~fence_wait;
-    assign execute_if[0].ready = lsu_ready && ~fence_wait;
-
-    // schedule memory request    
-
-    wire                            mem_req_valid;
-    wire [NUM_LANES-1:0]            mem_req_mask;
-    wire                            mem_req_rw;  
-    wire [NUM_LANES-1:0][`MEM_ADDR_WIDTH-REQ_ASHIFT-1:0] mem_req_addr;
-    reg  [NUM_LANES-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen;
-    reg  [NUM_LANES-1:0][`XLEN-1:0] mem_req_data;
-    wire [TAG_WIDTH-1:0]            mem_req_tag;
-    wire                            mem_req_ready;
-
-    wire                            mem_rsp_valid;
-    wire [NUM_LANES-1:0]            mem_rsp_mask;
-    wire [NUM_LANES-1:0][`XLEN-1:0] mem_rsp_data;
-    wire [TAG_WIDTH-1:0]            mem_rsp_tag;
-    wire                            mem_rsp_sop;
-    wire                            mem_rsp_eop;
-    wire                            mem_rsp_ready;
-
-    assign mem_req_valid = lsu_valid;
-    assign lsu_ready = mem_req_ready 
-                   && (~mem_req_rw || st_rsp_ready); // writes commit directly
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign mem_req_mask[i] = execute_if[0].data.tmask[i] && (~lsu_is_dup || (i == 0));
-    end
-
-    assign mem_req_rw = ~execute_if[0].data.wb;    
-
-    wire mem_req_fire = mem_req_valid && mem_req_ready;
-    wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
-    `UNUSED_VAR (mem_req_fire)
-    `UNUSED_VAR (mem_rsp_fire)
-
-    // address formatting
-
-    wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] req_align;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin  
-        assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0];
-        assign mem_req_addr[i] = full_addr[i][`MEM_ADDR_WIDTH-1:REQ_ASHIFT];
-    end
-
-    // byte enable formatting
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            mem_req_byteen[i] = '0;
-            case (`INST_LSU_WSIZE(execute_if[0].data.op_type))
-                0: begin // 8-bit   
-                    mem_req_byteen[i][req_align[i]] = 1'b1;
-                end
-                1: begin // 16 bit
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1;
-                end
-            `ifdef XLEN_64
-                2: begin // 32 bit
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1;
-                end
-            `endif
-                default : mem_req_byteen[i] = {DCACHE_WORD_SIZE{1'b1}};
-            endcase
-        end
-    end
-
-    // memory misalignment not supported!
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire lsu_req_fire = execute_if[0].valid && execute_if[0].ready;        
-        `RUNTIME_ASSERT((~lsu_req_fire || ~execute_if[0].data.tmask[i] || is_fence || (full_addr[i] % (1 << `INST_LSU_WSIZE(execute_if[0].data.op_type))) == 0), 
-            ("misaligned memory access, wid=%0d, PC=0x%0h, addr=0x%0h, wsize=%0d! (#%0d)", 
-                execute_if[0].data.wid, execute_if[0].data.PC, full_addr[i], `INST_LSU_WSIZE(execute_if[0].data.op_type), execute_if[0].data.uuid));
-    end
-
-    // store data formatting
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            mem_req_data[i] = execute_if[0].data.rs2_data[i];
-            case (req_align[i])
-                1: mem_req_data[i][`XLEN-1:8]  = execute_if[0].data.rs2_data[i][`XLEN-9:0];
-                2: mem_req_data[i][`XLEN-1:16] = execute_if[0].data.rs2_data[i][`XLEN-17:0];
-                3: mem_req_data[i][`XLEN-1:24] = execute_if[0].data.rs2_data[i][`XLEN-25:0];
-            `ifdef XLEN_64
-                4: mem_req_data[i][`XLEN-1:32] = execute_if[0].data.rs2_data[i][`XLEN-33:0];
-                5: mem_req_data[i][`XLEN-1:40] = execute_if[0].data.rs2_data[i][`XLEN-41:0];
-                6: mem_req_data[i][`XLEN-1:48] = execute_if[0].data.rs2_data[i][`XLEN-49:0];
-                7: mem_req_data[i][`XLEN-1:56] = execute_if[0].data.rs2_data[i][`XLEN-57:0];
-            `endif
-                default:;
-            endcase
-        end
-    end
-
-    // track SOP/EOP for out-of-order memory responses  
-
-    wire [LSUQ_SIZEW-1:0] pkt_waddr, pkt_raddr;
-    wire mem_rsp_sop_pkt, mem_rsp_eop_pkt;
-
-    if (PID_BITS != 0) begin
-        reg [`LSUQ_SIZE-1:0][PID_BITS:0] pkt_ctr;
-        reg [`LSUQ_SIZE-1:0] pkt_sop, pkt_eop;
-
-        wire mem_req_rd_fire     = mem_req_fire && execute_if[0].data.wb;
-        wire mem_req_rd_sop_fire = mem_req_rd_fire && execute_if[0].data.sop;
-        wire mem_req_rd_eop_fire = mem_req_rd_fire && execute_if[0].data.eop;
-        wire mem_rsp_eop_fire    = mem_rsp_fire && mem_rsp_eop;
-        wire full;
-        
-        VX_allocator #(
-            .SIZE (`LSUQ_SIZE)
-        ) pkt_allocator (
-            .clk        (clk),
-            .reset      (reset),
-            .acquire_en (mem_req_rd_eop_fire),
-            .acquire_addr(pkt_waddr),
-            .release_en (mem_rsp_eop_pkt),
-            .release_addr(pkt_raddr),
-            `UNUSED_PIN (empty),
-            .full       (full)
-        );
-
-        wire rd_during_wr = mem_req_rd_fire && mem_rsp_eop_fire && (pkt_raddr == pkt_waddr);
-
-        always @(posedge clk) begin
-            if (reset) begin                
-                pkt_ctr <= '0;
-                pkt_sop <= '0;
-                pkt_eop <= '0;
-            end else begin
-                if (mem_req_rd_sop_fire) begin
-                    pkt_sop[pkt_waddr] <= 1;
-                end
-                if (mem_req_rd_eop_fire) begin
-                    pkt_eop[pkt_waddr] <= 1;
-                end
-                if (mem_rsp_fire) begin
-                    pkt_sop[pkt_raddr] <= 0;
-                end
-                if (mem_rsp_eop_pkt) begin
-                    pkt_eop[pkt_raddr] <= 0;
-                end
-                if (~rd_during_wr) begin
-                    if (mem_req_rd_fire) begin
-                        pkt_ctr[pkt_waddr] <= pkt_ctr[pkt_waddr] + PID_BITS'(1);
-                    end
-                    if (mem_rsp_eop_fire) begin
-                        pkt_ctr[pkt_raddr] <= pkt_ctr[pkt_raddr] - PID_BITS'(1);
-                    end
-                end
-            end
-        end
-
-        assign mem_rsp_sop_pkt = pkt_sop[pkt_raddr];
-        assign mem_rsp_eop_pkt = mem_rsp_eop_fire && pkt_eop[pkt_raddr] && (pkt_ctr[pkt_raddr] == 1);
-        `RUNTIME_ASSERT(~(mem_req_rd_fire && full), ("allocator full!"))
-        `RUNTIME_ASSERT(~mem_req_rd_sop_fire || 0 == pkt_ctr[pkt_waddr], ("Oops!"))
-        `UNUSED_VAR (mem_rsp_sop)
-    end else begin
-        assign pkt_waddr = 0;
-        assign mem_rsp_sop_pkt = mem_rsp_sop;        
-        assign mem_rsp_eop_pkt = mem_rsp_eop;
-        `UNUSED_VAR (pkt_raddr)
-    end
-
-    assign mem_req_tag = {
-        execute_if[0].data.uuid, lsu_addr_type, execute_if[0].data.wid, execute_if[0].data.tmask, execute_if[0].data.PC, execute_if[0].data.rd, execute_if[0].data.op_type, req_align, execute_if[0].data.pid, pkt_waddr
-    `ifdef LSU_DUP_ENABLE
-        , lsu_is_dup
-    `endif
-    };
-
-    wire [DCACHE_NUM_REQS-1:0]              cache_req_valid;
-    wire [DCACHE_NUM_REQS-1:0]              cache_req_rw;
-    wire [DCACHE_NUM_REQS-1:0][(`XLEN/8)-1:0] cache_req_byteen;
-    wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] cache_req_addr;
-    wire [DCACHE_NUM_REQS-1:0][`XLEN-1:0] cache_req_data;
-    wire [DCACHE_NUM_REQS-1:0][CACHE_TAG_WIDTH-1:0] cache_req_tag;
-    wire [DCACHE_NUM_REQS-1:0]              cache_req_ready;
-    wire [DCACHE_NUM_REQS-1:0]              cache_rsp_valid;
-    wire [DCACHE_NUM_REQS-1:0][`XLEN-1:0] cache_rsp_data;
-    wire [DCACHE_NUM_REQS-1:0][CACHE_TAG_WIDTH-1:0] cache_rsp_tag;
-    wire [DCACHE_NUM_REQS-1:0]              cache_rsp_ready;
-
-    `RESET_RELAY (mem_scheduler_reset, reset);
-
-    VX_mem_scheduler #(
-        .INSTANCE_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)),
-        .NUM_REQS    (LSU_MEM_REQS), 
-        .NUM_BANKS   (DCACHE_NUM_REQS),
-        .ADDR_WIDTH  (DCACHE_ADDR_WIDTH),
-        .DATA_WIDTH  (`XLEN),
-        .QUEUE_SIZE  (`LSUQ_SIZE),
-        .TAG_WIDTH   (TAG_WIDTH),
-        .MEM_TAG_ID  (`UUID_WIDTH + (NUM_LANES * `CACHE_ADDR_TYPE_BITS)),
-        .UUID_WIDTH  (`UUID_WIDTH),
-        .RSP_PARTIAL (1),
-        .MEM_OUT_REG (2)
-    ) mem_scheduler (
-        .clk            (clk),
-        .reset          (mem_scheduler_reset),
-
-        // Input request
-        .req_valid      (mem_req_valid),
-        .req_rw         (mem_req_rw),
-        .req_mask       (mem_req_mask),
-        .req_byteen     (mem_req_byteen),
-        .req_addr       (mem_req_addr),
-        .req_data       (mem_req_data),
-        .req_tag        (mem_req_tag),
-        .req_empty      (mem_req_empty),
-        .req_ready      (mem_req_ready),
-        `UNUSED_PIN     (write_notify),
-        
-        // Output response
-        .rsp_valid      (mem_rsp_valid),
-        .rsp_mask       (mem_rsp_mask),
-        .rsp_data       (mem_rsp_data),
-        .rsp_tag        (mem_rsp_tag),
-        .rsp_sop        (mem_rsp_sop),
-        .rsp_eop        (mem_rsp_eop),
-        .rsp_ready      (mem_rsp_ready),
-
-        // Memory request
-        .mem_req_valid  (cache_req_valid),
-        .mem_req_rw     (cache_req_rw),
-        .mem_req_byteen (cache_req_byteen),
-        .mem_req_addr   (cache_req_addr),
-        .mem_req_data   (cache_req_data),
-        .mem_req_tag    (cache_req_tag),
-        .mem_req_ready  (cache_req_ready),
-
-        // Memory response
-        .mem_rsp_valid  (cache_rsp_valid),
-        .mem_rsp_data   (cache_rsp_data),
-        .mem_rsp_tag    (cache_rsp_tag),
-        .mem_rsp_ready  (cache_rsp_ready)
-    );
-
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-        assign cache_bus_if[i].req_valid = cache_req_valid[i];
-        assign cache_bus_if[i].req_data.rw = cache_req_rw[i];
-        assign cache_bus_if[i].req_data.byteen = cache_req_byteen[i];
-        assign cache_bus_if[i].req_data.addr = cache_req_addr[i];
-        assign cache_bus_if[i].req_data.data = cache_req_data[i];
-        assign cache_req_ready[i] = cache_bus_if[i].req_ready;
-
-        assign cache_rsp_valid[i] = cache_bus_if[i].rsp_valid;
-        assign cache_rsp_data[i] = cache_bus_if[i].rsp_data.data;
-        assign cache_bus_if[i].rsp_ready = cache_rsp_ready[i];
-    end
-
-    // cache tag formatting: <uuid, tag, type>
-    
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-        wire [`UUID_WIDTH-1:0]                          cache_req_uuid, cache_rsp_uuid;
-        wire [NUM_LANES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type, cache_rsp_type;        
-        wire [`CLOG2(`LSUQ_SIZE)-1:0]                   cache_req_tag_x, cache_rsp_tag_x;
-        if (DCACHE_NUM_BATCHES > 1) begin
-
-            wire [DCACHE_NUM_BATCHES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type_b, cache_rsp_type_b;            
-            wire [`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type_bi, cache_rsp_type_bi;
-            wire [DCACHE_BATCH_SEL_BITS-1:0] cache_req_bid, cache_rsp_bid;
-
-            assign {cache_req_uuid, cache_req_type, cache_req_bid, cache_req_tag_x} = cache_req_tag[i];
-            assign cache_req_type_bi = cache_req_type_b[cache_req_bid];
-            assign cache_bus_if[i].req_data.tag = {cache_req_uuid, cache_req_bid, cache_req_tag_x, cache_req_type_bi};
-
-            assign {cache_rsp_uuid, cache_rsp_bid, cache_rsp_tag_x, cache_rsp_type_bi} = cache_bus_if[i].rsp_data.tag;
-            assign cache_rsp_type_b = {DCACHE_NUM_BATCHES{cache_rsp_type_bi}};
-            assign cache_rsp_tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_bid, cache_rsp_tag_x};
-
-            for (genvar j = 0; j < DCACHE_NUM_BATCHES; ++j) begin
-                localparam k = j * DCACHE_NUM_REQS + i;                
-                if (k < NUM_LANES) begin
-                    assign cache_req_type_b[j] = cache_req_type[k];
-                    assign cache_rsp_type[k] = cache_rsp_type_b[j];
-                end else begin
-                    assign cache_req_type_b[j] = '0;
-                    `UNUSED_VAR (cache_rsp_type_b[j])
-                end
-            end
-
-        end else begin
-            
-            assign {cache_req_uuid, cache_req_type, cache_req_tag_x} = cache_req_tag[i];
-            assign cache_bus_if[i].req_data.tag = {cache_req_uuid, cache_req_tag_x, cache_req_type[i]};
-
-            assign {cache_rsp_uuid, cache_rsp_tag_x, cache_rsp_type[i]} = cache_bus_if[i].rsp_data.tag;
-            assign cache_rsp_tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_tag_x};        
-
-            for (genvar j = 0; j < DCACHE_NUM_REQS; ++j) begin
-                if (i != j) begin
-                    `UNUSED_VAR (cache_req_type[j])
-                    assign cache_rsp_type[j] = '0;
-                end
-            end
-        end
-    end
-    
-    wire [`UUID_WIDTH-1:0] rsp_uuid;
-    wire [NUM_LANES-1:0][`CACHE_ADDR_TYPE_BITS-1:0] rsp_addr_type;
-    wire [`NW_WIDTH-1:0] rsp_wid;
-    wire [NUM_LANES-1:0] rsp_tmask_uq;
-    wire [`XLEN-1:0] rsp_pc;
-    wire [`NR_BITS-1:0] rsp_rd;
-    wire [`INST_LSU_BITS-1:0] rsp_op_type;
-    wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] rsp_align;
-    wire [PID_WIDTH-1:0] rsp_pid;
-    wire rsp_is_dup;
-    
-`ifndef LSU_DUP_ENABLE
-    assign rsp_is_dup = 0;
-`endif
-
-    assign {
-        rsp_uuid, rsp_addr_type, rsp_wid, rsp_tmask_uq, rsp_pc, rsp_rd, rsp_op_type, rsp_align, rsp_pid, pkt_raddr
-    `ifdef LSU_DUP_ENABLE
-        , rsp_is_dup
-    `endif
-    } = mem_rsp_tag;
-    `UNUSED_VAR (rsp_addr_type)
-    `UNUSED_VAR (rsp_op_type)
-
-    // load response formatting
-
-    reg [NUM_LANES-1:0][`XLEN-1:0] rsp_data;
-    wire [NUM_LANES-1:0] rsp_tmask;
-
-`ifdef XLEN_64
-`ifdef EXT_F_ENABLE
-    // apply nan-boxing to flw outputs
-    wire rsp_is_float = rsp_rd[5];
-`else
-    wire rsp_is_float = 0;
-`endif
-`endif
-
-    for (genvar i = 0; i < NUM_LANES; i++) begin
-    `ifdef XLEN_64
-        wire [63:0] rsp_data64 = (i == 0 || rsp_is_dup) ? mem_rsp_data[0] : mem_rsp_data[i];
-        wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? (rsp_align[0][2] ? mem_rsp_data[0][63:32] : mem_rsp_data[0][31:0]) :
-                                                          (rsp_align[i][2] ? mem_rsp_data[i][63:32] : mem_rsp_data[i][31:0]);
-    `else
-        wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? mem_rsp_data[0] : mem_rsp_data[i];
-    `endif        
-        wire [15:0] rsp_data16 = rsp_align[i][1] ? rsp_data32[31:16] : rsp_data32[15:0];
-        wire [7:0]  rsp_data8  = rsp_align[i][0] ? rsp_data16[15:8] : rsp_data16[7:0];
-
-        always @(*) begin
-            case (`INST_LSU_FMT(rsp_op_type))
-            `INST_FMT_B:  rsp_data[i] = `XLEN'(signed'(rsp_data8));
-            `INST_FMT_H:  rsp_data[i] = `XLEN'(signed'(rsp_data16));
-            `INST_FMT_BU: rsp_data[i] = `XLEN'(unsigned'(rsp_data8));
-            `INST_FMT_HU: rsp_data[i] = `XLEN'(unsigned'(rsp_data16));
-        `ifdef XLEN_64            
-            `INST_FMT_W:  rsp_data[i] = rsp_is_float ? (`XLEN'(rsp_data32) | 64'hffffffff00000000) : `XLEN'(signed'(rsp_data32));
-            `INST_FMT_WU: rsp_data[i] = `XLEN'(unsigned'(rsp_data32));
-            `INST_FMT_D:  rsp_data[i] = `XLEN'(signed'(rsp_data64));
-        `else
-            `INST_FMT_W:  rsp_data[i] = `XLEN'(signed'(rsp_data32));
-        `endif
-            default: rsp_data[i] = 'x;
-            endcase
-        end        
-    end   
-
-    assign rsp_tmask = rsp_is_dup ? rsp_tmask_uq : mem_rsp_mask;
-
-    // load commit
-
-    VX_elastic_buffer #(
-        .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + (NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1),
-        .SIZE  (2)
-    ) ld_rsp_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (mem_rsp_valid),
-        .ready_in  (mem_rsp_ready),
-        .data_in   ({rsp_uuid, rsp_wid, rsp_tmask, rsp_pc, rsp_rd, rsp_data, rsp_pid, mem_rsp_sop_pkt, mem_rsp_eop_pkt}),
-        .data_out  ({commit_ld_if.data.uuid, commit_ld_if.data.wid, commit_ld_if.data.tmask, commit_ld_if.data.PC, commit_ld_if.data.rd, commit_ld_if.data.data, commit_ld_if.data.pid, commit_ld_if.data.sop, commit_ld_if.data.eop}),
-        .valid_out (commit_ld_if.valid),
-        .ready_out (commit_ld_if.ready)
-    );
-
-    assign commit_ld_if.data.wb = 1'b1;
-
-    // store commit
-
-    VX_elastic_buffer #(
-        .DATAW (`UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + PID_WIDTH + 1 + 1),
-        .SIZE  (2)
-    ) st_rsp_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (mem_req_fire && mem_req_rw),
-        .ready_in  (st_rsp_ready),
-        .data_in   ({execute_if[0].data.uuid, execute_if[0].data.wid, execute_if[0].data.tmask, execute_if[0].data.PC, execute_if[0].data.pid, execute_if[0].data.sop, execute_if[0].data.eop}),
-        .data_out  ({commit_st_if.data.uuid, commit_st_if.data.wid, commit_st_if.data.tmask, commit_st_if.data.PC, commit_st_if.data.pid, commit_st_if.data.sop, commit_st_if.data.eop}),
-        .valid_out (commit_st_if.valid),
-        .ready_out (commit_st_if.ready)
-    );
-    assign commit_st_if.data.rd   = '0;
-    assign commit_st_if.data.wb   = 1'b0;
-    assign commit_st_if.data.data = commit_ld_if.data.data; // force arbiter passthru
-
-    // lsu commit
-    
-    `RESET_RELAY (commit_reset, reset);
-
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) commit_arb_if[1]();
-
-    VX_stream_arb #(
-        .NUM_INPUTS (2),
-        .DATAW      (RSP_ARB_DATAW),
-        .OUT_REG    (3)
-    ) rsp_arb (
-        .clk       (clk),
-        .reset     (commit_reset),
-        .valid_in  ({commit_st_if.valid, commit_ld_if.valid}),
-        .ready_in  ({commit_st_if.ready, commit_ld_if.ready}),
-        .data_in   ({commit_st_if.data, commit_ld_if.data}),
-        .data_out  (commit_arb_if[0].data),
-        .valid_out (commit_arb_if[0].valid), 
-        .ready_out (commit_arb_if[0].ready),        
-        `UNUSED_PIN (sel_out)
-    );
-
-    VX_gather_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (3)
-    ) gather_unit (
-        .clk           (clk),
-        .reset         (commit_reset),
-        .commit_in_if  (commit_arb_if),
-        .commit_out_if (commit_if)
-    );
-
-`ifdef DBG_SCOPE_LSU
-    if (CORE_ID == 0) begin
-    `ifdef SCOPE
-        VX_scope_tap #(
-            .SCOPE_ID (3),
-            .TRIGGERW (3),
-            .PROBEW   (`UUID_WIDTH+NUM_LANES*(`XLEN+4+`XLEN)+1+`UUID_WIDTH+NUM_LANES*`XLEN)
-        ) scope_tap (
-            .clk(clk),
-            .reset(scope_reset),
-            .start(1'b0),
-            .stop(1'b0),
-            .triggers({reset, mem_req_fire, mem_rsp_fire}),
-            .probes({execute_if[0].data.uuid, full_addr, mem_req_rw, mem_req_byteen, mem_req_data, rsp_uuid, rsp_data}),
-            .bus_in(scope_bus_in),
-            .bus_out(scope_bus_out)
-        );
-    `endif
-    `ifdef CHIPSCOPE    
-        wire [31:0] full_addr_0 = full_addr[0];
-        wire [31:0] mem_req_data_0 = mem_req_data[0];
-        wire [31:0] rsp_data_0 = rsp_data[0];
-        ila_lsu ila_lsu_inst (
-            .clk    (clk),
-            .probe0 ({mem_req_data_0, execute_if[0].data.uuid, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask, full_addr_0, mem_req_byteen, mem_req_rw, mem_req_ready, mem_req_valid}),
-            .probe1 ({rsp_data_0, rsp_uuid, mem_rsp_eop, rsp_pc, rsp_rd, rsp_tmask, rsp_wid, mem_rsp_ready, mem_rsp_valid}),
-            .probe2 ({cache_bus_if.req_data.data, cache_bus_if.req_data.tag, cache_bus_if.req_data.byteen, cache_bus_if.req_data.addr, cache_bus_if.req_data.rw, cache_bus_if.req_ready, cache_bus_if.req_valid}),
-            .probe3 ({cache_bus_if.rsp_data.data, cache_bus_if.rsp_data.tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid})
-        );
-    `endif
-    end
-`else
-    `SCOPE_IO_UNUSED()
-`endif
-  
-`ifdef DBG_TRACE_CORE_DCACHE
-    always @(posedge clk) begin    
-        if (execute_if[0].valid && fence_wait) begin
-            `TRACE(1, ("%d: *** D$%0d fence wait\n", $time, CORE_ID));
-        end
-        if (mem_req_fire) begin
-            if (mem_req_rw) begin
-                `TRACE(1, ("%d: D$%0d Wr Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask));
-                `TRACE_ARRAY1D(1, full_addr, NUM_LANES);
-                `TRACE(1, (", tag=0x%0h, byteen=0x%0h, type=", mem_req_tag, mem_req_byteen));
-                `TRACE_ARRAY1D(1, lsu_addr_type, NUM_LANES);
-                `TRACE(1, (", data="));
-                `TRACE_ARRAY1D(1, mem_req_data, NUM_LANES);
-                `TRACE(1, (", is_dup=%b (#%0d)\n", lsu_is_dup, execute_if[0].data.uuid));
-            end else begin
-                `TRACE(1, ("%d: D$%0d Rd Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask));
-                `TRACE_ARRAY1D(1, full_addr, NUM_LANES);
-                `TRACE(1, (", tag=0x%0h, byteen=0x%0h, type=", mem_req_tag, mem_req_byteen));
-                `TRACE_ARRAY1D(1, lsu_addr_type, NUM_LANES);
-                `TRACE(1, (", rd=%0d, is_dup=%b (#%0d)\n", execute_if[0].data.rd, lsu_is_dup, execute_if[0].data.uuid));
-            end
-        end
-        if (mem_rsp_fire) begin
-            `TRACE(1, ("%d: D$%0d Rsp: wid=%0d, PC=0x%0h, tmask=%b, tag=0x%0h, rd=%0d, sop=%b, eop=%b, data=",
-                $time, CORE_ID, rsp_wid, rsp_pc, mem_rsp_mask, mem_rsp_tag, rsp_rd, mem_rsp_sop, mem_rsp_eop));
-            `TRACE_ARRAY1D(1, mem_rsp_data, NUM_LANES);
-            `TRACE(1, (", is_dup=%b (#%0d)\n", rsp_is_dup, rsp_uuid));
-        end
-    end
-`endif
-    
-endmodule

hw/rtl/core/VX_muldiv_unit.sv

@@ -1,341 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_muldiv_unit #(
-    parameter CORE_ID   = 0,
-    parameter NUM_LANES = 1
-) (
-    input wire          clk,
-    input wire          reset,
-    
-    // Inputs
-    VX_execute_if.slave execute_if,
-
-    // Outputs
-    VX_commit_if.master commit_if
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam PID_BITS  = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH = `UP(PID_BITS);
-    localparam TAGW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + PID_WIDTH + 1 + 1;
-
-    `UNUSED_VAR (execute_if.data.rs3_data)
-
-    wire [`INST_M_BITS-1:0] muldiv_op = `INST_M_BITS'(execute_if.data.op_type);
-
-    wire is_mulx_op = `INST_M_IS_MULX(muldiv_op);
-    wire is_signed_op = `INST_M_SIGNED(muldiv_op);
-`ifdef XLEN_64
-    wire is_alu_w = `INST_ALU_IS_W(execute_if.data.op_mod);
-`else
-    wire is_alu_w = 0;
-`endif
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_out;
-    wire [`UUID_WIDTH-1:0] mul_uuid_out;
-    wire [`NW_WIDTH-1:0] mul_wid_out;
-    wire [NUM_LANES-1:0] mul_tmask_out;
-    wire [`XLEN-1:0] mul_PC_out;
-    wire [`NR_BITS-1:0] mul_rd_out;
-    wire mul_wb_out;
-    wire [PID_WIDTH-1:0] mul_pid_out;
-    wire mul_sop_out, mul_eop_out;
-    
-    wire mul_valid_in = execute_if.valid && is_mulx_op;
-    wire mul_ready_in;
-    wire mul_valid_out;
-    wire mul_ready_out;
-    
-    wire is_mulh_in      = `INST_M_IS_MULH(muldiv_op);
-    wire is_signed_mul_a = `INST_M_SIGNED_A(muldiv_op);
-    wire is_signed_mul_b = is_signed_op;
-
-`ifdef IMUL_DPI
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_tmp;  
-
-    wire mul_fire_in = mul_valid_in && mul_ready_in;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [`XLEN-1:0] mul_resultl, mul_resulth;
-        wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i]; 
-        wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i]; 
-        always @(*) begin   
-            dpi_imul (mul_fire_in, is_signed_mul_a, is_signed_mul_b, mul_in1, mul_in2, mul_resultl, mul_resulth);
-        end
-        assign mul_result_tmp[i] = is_mulh_in ? mul_resulth : (is_alu_w ? `XLEN'($signed(mul_resultl[31:0])) : mul_resultl);
-    end
-
-    VX_shift_register #(
-        .DATAW  (1 + TAGW + (NUM_LANES * `XLEN)),
-        .DEPTH  (`LATENCY_IMUL),
-        .RESETW (1)
-    ) mul_shift_reg (
-        .clk(clk),
-        .reset    (reset),
-        .enable   (mul_ready_in),
-        .data_in  ({mul_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, mul_result_tmp}),
-        .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, mul_result_out})
-    );
-
-    assign mul_ready_in = mul_ready_out || ~mul_valid_out;
-
-`else      
-    
-    wire [NUM_LANES-1:0][2*(`XLEN+1)-1:0] mul_result_tmp;
-    wire is_mulh_out;
-    wire is_mul_w_out;
-
-`ifdef XLEN_64
-
-    wire [NUM_LANES-1:0][`XLEN:0] mul_in1;
-    wire [NUM_LANES-1:0][`XLEN:0] mul_in2;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign mul_in1[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]} : {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]};
-        assign mul_in2[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]} : {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};
-    end    
-
-    wire mul_strode;
-    wire mul_busy;
-
-    VX_elastic_adapter mul_elastic_adapter (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (mul_valid_in),
-        .ready_in  (mul_ready_in), 
-        .valid_out (mul_valid_out),
-        .ready_out (mul_ready_out),
-        .strobe    (mul_strode),
-        .busy      (mul_busy)
-    );
-
-    VX_serial_mul #(
-        .A_WIDTH (`XLEN+1),
-        .LANES   (NUM_LANES),
-        .SIGNED  (1)
-    ) serial_mul (
-        .clk       (clk),
-        .reset     (reset), 
-
-        .strobe    (mul_strode),
-        .busy      (mul_busy), 
-        
-        .dataa     (mul_in1),
-        .datab     (mul_in2),
-        .result    (mul_result_tmp)
-    );
-
-    reg [TAGW+2-1:0] mul_tag_r;
-    always @(posedge clk) begin
-        if (mul_valid_in && mul_ready_in) begin
-            mul_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_mulh_in, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop};
-        end
-    end
-    
-    assign {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out, is_mul_w_out, mul_pid_out, mul_sop_out, mul_eop_out} = mul_tag_r;
-
-`else
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [`XLEN:0] mul_in1 = {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]};
-        wire [`XLEN:0] mul_in2 = {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};        
-    
-        VX_multiplier #(
-            .A_WIDTH (`XLEN+1),
-            .B_WIDTH (`XLEN+1),
-            .R_WIDTH (2*(`XLEN+1)),
-            .SIGNED  (1),
-            .LATENCY (`LATENCY_IMUL)
-        ) multiplier (
-            .clk    (clk),
-            .enable (mul_ready_in),
-            .dataa  (mul_in1),
-            .datab  (mul_in2),
-            .result (mul_result_tmp[i])
-        );        
-    end
-
-    VX_shift_register #(
-        .DATAW  (1 + TAGW + 1 + 1),
-        .DEPTH  (`LATENCY_IMUL),
-        .RESETW (1)
-    ) mul_shift_reg (
-        .clk(clk),
-        .reset    (reset),
-        .enable   (mul_ready_in),
-        .data_in  ({mul_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, is_mulh_in, is_alu_w}),
-        .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, is_mulh_out, is_mul_w_out})
-    );
-
-    assign mul_ready_in = mul_ready_out || ~mul_valid_out;
-
-`endif
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-    `ifdef XLEN_64
-        assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : 
-                                                 (is_mul_w_out ? `XLEN'($signed(mul_result_tmp[i][31:0])) : 
-                                                                 mul_result_tmp[i][`XLEN-1:0]);
-    `else
-        assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : mul_result_tmp[i][`XLEN-1:0];
-        `UNUSED_VAR (is_mul_w_out)
-    `endif
-    end
-
-`endif
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] div_result_out;
-    wire [`UUID_WIDTH-1:0] div_uuid_out;
-    wire [`NW_WIDTH-1:0] div_wid_out;
-    wire [NUM_LANES-1:0] div_tmask_out;
-    wire [`XLEN-1:0] div_PC_out;
-    wire [`NR_BITS-1:0] div_rd_out;
-    wire div_wb_out;
-    wire [PID_WIDTH-1:0] div_pid_out;
-    wire div_sop_out, div_eop_out;
-
-    wire is_rem_op = `INST_M_IS_REM(muldiv_op);
-
-    wire div_valid_in = execute_if.valid && ~is_mulx_op;  
-    wire div_ready_in;
-    wire div_valid_out;
-    wire div_ready_out;
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] div_in1;
-    wire [NUM_LANES-1:0][`XLEN-1:0] div_in2;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-    `ifdef XLEN_64
-        assign div_in1[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]}: execute_if.data.rs1_data[i];
-        assign div_in2[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]}: execute_if.data.rs2_data[i];
-    `else
-        assign div_in1[i] = execute_if.data.rs1_data[i];
-        assign div_in2[i] = execute_if.data.rs2_data[i];
-    `endif        
-    end
-
-`ifdef IDIV_DPI    
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] div_result_in;
-    wire div_fire_in = div_valid_in && div_ready_in;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [`XLEN-1:0] div_quotient, div_remainder;
-        always @(*) begin  
-            dpi_idiv (div_fire_in, is_signed_op, div_in1[i], div_in2[i], div_quotient, div_remainder);
-        end
-        assign div_result_in[i] = is_rem_op ? (is_alu_w ? `XLEN'($signed(div_remainder[31:0])) : div_remainder) : 
-                                              (is_alu_w ? `XLEN'($signed(div_quotient[31:0])) : div_quotient);
-    end
-
-    VX_shift_register #(
-        .DATAW  (1 + TAGW + (NUM_LANES * `XLEN)),
-        .DEPTH  (`LATENCY_IMUL),
-        .RESETW (1)
-    ) div_shift_reg (
-        .clk(clk),
-        .reset    (reset),
-        .enable   (div_ready_in),
-        .data_in  ({div_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, div_result_in}),
-        .data_out ({div_valid_out, div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_pid_out, div_sop_out, div_eop_out, div_result_out})
-    );
-
-    assign div_ready_in = div_ready_out || ~div_valid_out;
-
-`else
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] div_quotient, div_remainder;
-    wire is_rem_op_out;    
-    wire is_div_w_out;
-    wire div_strode;
-    wire div_busy;
-
-    VX_elastic_adapter div_elastic_adapter (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (div_valid_in),
-        .ready_in  (div_ready_in),
-        .valid_out (div_valid_out),
-        .ready_out (div_ready_out),
-        .strobe    (div_strode),
-        .busy      (div_busy)
-    );
-
-    VX_serial_div #(
-        .WIDTHN (`XLEN),
-        .WIDTHD (`XLEN),
-        .WIDTHQ (`XLEN),
-        .WIDTHR (`XLEN),
-        .LANES  (NUM_LANES)
-    ) serial_div (
-        .clk       (clk),
-        .reset     (reset),
-        
-        .strobe    (div_strode),
-        .busy      (div_busy),
-
-        .is_signed (is_signed_op), 
-        .numer     (div_in1),
-        .denom     (div_in2),
-
-        .quotient  (div_quotient),
-        .remainder (div_remainder)        
-    );
-
-    reg [TAGW+2-1:0] div_tag_r;
-    always @(posedge clk) begin
-        if (div_valid_in && div_ready_in) begin
-            div_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_rem_op, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop};
-        end
-    end
-    
-    assign {div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out, is_div_w_out, div_pid_out, div_sop_out, div_eop_out} = div_tag_r;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-    `ifdef XLEN_64
-        assign div_result_out[i] = is_rem_op_out ? (is_div_w_out ? `XLEN'($signed(div_remainder[i][31:0])) : div_remainder[i]) : 
-                                                   (is_div_w_out ? `XLEN'($signed(div_quotient[i][31:0])) : div_quotient[i]);     
-    `else
-        assign div_result_out[i] = is_rem_op_out ? div_remainder[i] : div_quotient[i];
-        `UNUSED_VAR (is_div_w_out)
-    `endif
-    end
-
-`endif
-
-    // can accept new request?
-    assign execute_if.ready = is_mulx_op ? mul_ready_in : div_ready_in;
-
-    VX_stream_arb #(
-        .NUM_INPUTS (2),
-        .DATAW (TAGW + (NUM_LANES * `XLEN)),
-        .OUT_REG (1)
-    ) rsp_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  ({div_valid_out, mul_valid_out}),
-        .ready_in  ({div_ready_out, mul_ready_out}),
-        .data_in   ({{div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_pid_out, div_sop_out, div_eop_out, div_result_out},
-                     {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, mul_result_out}}),
-        .data_out  ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop, commit_if.data.data}),
-        .valid_out (commit_if.valid),
-        .ready_out (commit_if.ready),
-        `UNUSED_PIN (sel_out)
-    );
-    
-endmodule

hw/rtl/core/VX_operands.sv

@@ -1,294 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_operands import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0,
-    parameter CACHE_ENABLE = 0
-) (
-    input wire              clk,
-    input wire              reset,
-
-    VX_writeback_if.slave   writeback_if [`ISSUE_WIDTH],
-    VX_ibuffer_if.slave     scoreboard_if [`ISSUE_WIDTH],
-    VX_operands_if.master   operands_if [`ISSUE_WIDTH]
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + `NR_BITS;
-    localparam RAM_ADDRW = `LOG2UP(`NUM_REGS * ISSUE_RATIO);
-
-    localparam STATE_IDLE   = 2'd0;
-    localparam STATE_FETCH1 = 2'd1;
-    localparam STATE_FETCH2 = 2'd2;
-    localparam STATE_FETCH3 = 2'd3;
-    localparam STATE_BITS   = 2;
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        wire [`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data;
-        reg [`NR_BITS-1:0] gpr_rd_rid, gpr_rd_rid_n;
-        reg [ISSUE_WIS_W-1:0] gpr_rd_wis, gpr_rd_wis_n;
-
-        reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data [ISSUE_RATIO-1:0];
-        reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data_n [ISSUE_RATIO-1:0];
-        reg [`NR_BITS-1:0] cache_reg [ISSUE_RATIO-1:0];
-        reg [`NR_BITS-1:0] cache_reg_n [ISSUE_RATIO-1:0];
-        reg [`NUM_THREADS-1:0] cache_tmask [ISSUE_RATIO-1:0];
-        reg [`NUM_THREADS-1:0] cache_tmask_n [ISSUE_RATIO-1:0];
-        reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n;
-
-        reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n;
-        reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n;
-        reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n;
-
-        reg [STATE_BITS-1:0] state, state_n;
-        reg [`NR_BITS-1:0] rs2, rs2_n;
-        reg [`NR_BITS-1:0] rs3, rs3_n;
-        reg rs2_ready, rs2_ready_n;
-        reg rs3_ready, rs3_ready_n;
-        reg data_ready, data_ready_n;
-
-        wire stg_valid_in, stg_ready_in;
-        
-        wire is_rs1_zero = (scoreboard_if[i].data.rs1 == 0);
-        wire is_rs2_zero = (scoreboard_if[i].data.rs2 == 0);
-        wire is_rs3_zero = (scoreboard_if[i].data.rs3 == 0);
-
-        always @(*) begin
-            state_n      = state;
-            rs2_n        = rs2;
-            rs3_n        = rs3;
-            rs2_ready_n  = rs2_ready;
-            rs3_ready_n  = rs3_ready;
-            rs1_data_n   = rs1_data;
-            rs2_data_n   = rs2_data;
-            rs3_data_n   = rs3_data;
-            cache_data_n = cache_data;
-            cache_reg_n  = cache_reg;
-            cache_tmask_n= cache_tmask;
-            cache_eop_n  = cache_eop;
-            gpr_rd_rid_n = gpr_rd_rid;
-            gpr_rd_wis_n = gpr_rd_wis;
-            data_ready_n = data_ready;
-
-            case (state)
-            STATE_IDLE: begin
-                if (operands_if[i].valid && operands_if[i].ready) begin
-                    data_ready_n = 0;
-                end
-                if (scoreboard_if[i].valid && data_ready_n == 0) begin
-                    data_ready_n = 1;
-                    if (is_rs3_zero || (CACHE_ENABLE != 0 && 
-                                        scoreboard_if[i].data.rs3 == cache_reg[scoreboard_if[i].data.wis] && 
-                                        (scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin
-                        rs3_data_n   = (is_rs3_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis];
-                        rs3_ready_n  = 1;
-                    end else begin
-                        rs3_ready_n  = 0;
-                        gpr_rd_rid_n = scoreboard_if[i].data.rs3;
-                        data_ready_n = 0;
-                        state_n      = STATE_FETCH3;
-                    end
-                    if (is_rs2_zero || (CACHE_ENABLE != 0 && 
-                                        scoreboard_if[i].data.rs2 == cache_reg[scoreboard_if[i].data.wis] && 
-                                        (scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin
-                        rs2_data_n   = (is_rs2_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis];
-                        rs2_ready_n  = 1;
-                    end else begin
-                        rs2_ready_n  = 0;
-                        gpr_rd_rid_n = scoreboard_if[i].data.rs2;
-                        data_ready_n = 0;
-                        state_n      = STATE_FETCH2;
-                    end
-                    if (is_rs1_zero || (CACHE_ENABLE != 0 && 
-                                        scoreboard_if[i].data.rs1 == cache_reg[scoreboard_if[i].data.wis] && 
-                                        (scoreboard_if[i].data.tmask & cache_tmask[scoreboard_if[i].data.wis]) == scoreboard_if[i].data.tmask)) begin
-                        rs1_data_n   = (is_rs1_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if[i].data.wis];
-                    end else begin
-                        gpr_rd_rid_n = scoreboard_if[i].data.rs1;
-                        data_ready_n = 0;
-                        state_n      = STATE_FETCH1;
-                    end
-                end
-                gpr_rd_wis_n = scoreboard_if[i].data.wis;
-                rs2_n = scoreboard_if[i].data.rs2;
-                rs3_n = scoreboard_if[i].data.rs3;
-            end
-            STATE_FETCH1: begin
-                rs1_data_n = gpr_rd_data;
-                if (~rs2_ready) begin
-                    gpr_rd_rid_n = rs2;
-                    state_n = STATE_FETCH2;
-                end else if (~rs3_ready) begin
-                    gpr_rd_rid_n = rs3;
-                    state_n = STATE_FETCH3;
-                end else begin
-                    data_ready_n = 1;
-                    state_n = STATE_IDLE;
-                end
-            end
-            STATE_FETCH2: begin
-                rs2_data_n = gpr_rd_data;
-                if (~rs3_ready) begin
-                    gpr_rd_rid_n = rs3;
-                    state_n = STATE_FETCH3;
-                end else begin
-                    data_ready_n = 1;
-                    state_n = STATE_IDLE;
-                end
-            end
-            STATE_FETCH3: begin
-                rs3_data_n = gpr_rd_data;
-                data_ready_n = 1;
-                state_n = STATE_IDLE;
-            end
-            endcase
-            
-            if (CACHE_ENABLE != 0 && writeback_if[i].valid) begin
-                if ((cache_reg[writeback_if[i].data.wis] == writeback_if[i].data.rd) 
-                 || (cache_eop[writeback_if[i].data.wis] && writeback_if[i].data.sop)) begin
-                    for (integer j = 0; j < `NUM_THREADS; ++j) begin
-                        if (writeback_if[i].data.tmask[j]) begin
-                            cache_data_n[writeback_if[i].data.wis][j] = writeback_if[i].data.data[j];
-                        end
-                    end
-                    cache_reg_n[writeback_if[i].data.wis] = writeback_if[i].data.rd;
-                    cache_eop_n[writeback_if[i].data.wis] = writeback_if[i].data.eop;
-                    cache_tmask_n[writeback_if[i].data.wis] = writeback_if[i].data.sop ? writeback_if[i].data.tmask : 
-                                                                    (cache_tmask_n[writeback_if[i].data.wis] | writeback_if[i].data.tmask);
-                end
-            end
-        end
-
-        always @(posedge clk)  begin
-            if (reset) begin 
-                state       <= STATE_IDLE;
-                cache_eop   <= {ISSUE_RATIO{1'b1}};
-                data_ready  <= 0;
-            end else begin
-                state       <= state_n;
-                cache_eop   <= cache_eop_n;
-                data_ready  <= data_ready_n;
-            end
-            gpr_rd_rid  <= gpr_rd_rid_n;
-            gpr_rd_wis  <= gpr_rd_wis_n;
-            rs2_ready   <= rs2_ready_n;
-            rs3_ready   <= rs3_ready_n;
-            rs2         <= rs2_n;
-            rs3         <= rs3_n;
-            rs1_data    <= rs1_data_n;
-            rs2_data    <= rs2_data_n;
-            rs3_data    <= rs3_data_n;          
-            cache_data  <= cache_data_n;
-            cache_reg   <= cache_reg_n;
-            cache_tmask <= cache_tmask_n;
-        end
-
-        assign stg_valid_in = scoreboard_if[i].valid && data_ready;
-        assign scoreboard_if[i].ready = stg_ready_in && data_ready;        
-
-        VX_toggle_buffer #(
-            .DATAW (DATAW)
-        ) staging_buffer (
-            .clk       (clk),
-            .reset     (reset),
-            .valid_in  (stg_valid_in),
-            .data_in   ({
-                scoreboard_if[i].data.uuid,
-                scoreboard_if[i].data.wis,
-                scoreboard_if[i].data.tmask,
-                scoreboard_if[i].data.PC, 
-                scoreboard_if[i].data.wb,
-                scoreboard_if[i].data.ex_type,
-                scoreboard_if[i].data.op_type,
-                scoreboard_if[i].data.op_mod,
-                scoreboard_if[i].data.use_PC,
-                scoreboard_if[i].data.use_imm,
-                scoreboard_if[i].data.imm,
-                scoreboard_if[i].data.rd
-            }),
-            .ready_in  (stg_ready_in),
-            .valid_out (operands_if[i].valid),
-            .data_out  ({
-                operands_if[i].data.uuid,
-                operands_if[i].data.wis,
-                operands_if[i].data.tmask,
-                operands_if[i].data.PC, 
-                operands_if[i].data.wb,
-                operands_if[i].data.ex_type,
-                operands_if[i].data.op_type,
-                operands_if[i].data.op_mod,
-                operands_if[i].data.use_PC,
-                operands_if[i].data.use_imm,
-                operands_if[i].data.imm,
-                operands_if[i].data.rd
-            }),
-            .ready_out (operands_if[i].ready)
-        );
-
-        assign operands_if[i].data.rs1_data = rs1_data;
-        assign operands_if[i].data.rs2_data = rs2_data;
-        assign operands_if[i].data.rs3_data = rs3_data;
-
-        // GPR banks
-
-        reg [RAM_ADDRW-1:0] gpr_rd_addr;       
-        wire [RAM_ADDRW-1:0] gpr_wr_addr;
-        if (ISSUE_WIS != 0) begin
-            assign gpr_wr_addr = {writeback_if[i].data.wis, writeback_if[i].data.rd};
-            always @(posedge clk) begin
-                gpr_rd_addr <= {gpr_rd_wis_n, gpr_rd_rid_n};
-            end
-        end else begin
-            assign gpr_wr_addr = writeback_if[i].data.rd;
-            always @(posedge clk) begin
-                gpr_rd_addr <= gpr_rd_rid_n;
-            end
-        end
-        
-    `ifdef GPR_RESET
-        reg wr_enabled = 0;
-        always @(posedge clk) begin
-            if (reset) begin
-                wr_enabled <= 1;
-            end
-        end
-    `endif
-
-        for (genvar j = 0; j < `NUM_THREADS; ++j) begin
-            VX_dp_ram #(
-                .DATAW (`XLEN),
-                .SIZE (`NUM_REGS * ISSUE_RATIO),
-            `ifdef GPR_RESET
-                .INIT_ENABLE (1),
-                .INIT_VALUE (0),
-            `endif
-                .NO_RWCHECK (1)
-            ) gpr_ram (
-                .clk   (clk),
-                .read  (1'b1),
-                `UNUSED_PIN (wren),
-            `ifdef GPR_RESET
-                .write (wr_enabled && writeback_if[i].valid && writeback_if[i].data.tmask[j]),
-            `else
-                .write (writeback_if[i].valid && writeback_if[i].data.tmask[j]),
-            `endif              
-                .waddr (gpr_wr_addr),
-                .wdata (writeback_if[i].data.data[j]),
-                .raddr (gpr_rd_addr),
-                .rdata (gpr_rd_data[j])
-            );
-        end
-    end
-
-endmodule

hw/rtl/core/VX_pending_instr.sv

@@ -1,79 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_pending_instr #(
-    parameter CTR_WIDTH  = 12,
-    parameter ALM_EMPTY  = 1,
-    parameter DECR_COUNT = 1
-) (
-    input wire                  clk,
-    input wire                  reset,
-    input wire                  incr,
-    input wire [`NW_WIDTH-1:0]  incr_wid,
-    input wire [DECR_COUNT-1:0] decr,
-    input wire [DECR_COUNT-1:0][`NW_WIDTH-1:0] decr_wid,
-    input wire [`NW_WIDTH-1:0]  alm_empty_wid,
-    output wire                 empty,
-    output wire                 alm_empty
-);
-    localparam COUNTW = `CLOG2(DECR_COUNT+1);
-
-    reg [`NUM_WARPS-1:0][CTR_WIDTH-1:0] pending_instrs;
-    reg [`NUM_WARPS-1:0][COUNTW-1:0] decr_cnt;
-    reg [`NUM_WARPS-1:0][DECR_COUNT-1:0] decr_mask;
-    reg [`NUM_WARPS-1:0] incr_cnt, incr_cnt_n;
-    reg [`NUM_WARPS-1:0] alm_empty_r, empty_r;
-
-    always @(*) begin
-        incr_cnt_n = 0;
-        decr_mask = 0;
-        if (incr) begin
-            incr_cnt_n[incr_wid] = 1;
-        end
-        for (integer i = 0; i < DECR_COUNT; ++i) begin
-            if (decr[i]) begin
-                decr_mask[decr_wid[i]][i] = 1;
-            end
-        end
-    end
-
-    for (genvar i = 0; i < `NUM_WARPS; ++i) begin
-        
-        wire [COUNTW-1:0] decr_cnt_n;
-        `POP_COUNT(decr_cnt_n, decr_mask[i]);
-        
-        wire [CTR_WIDTH-1:0] pending_instrs_n = pending_instrs[i] + CTR_WIDTH'(incr_cnt[i]) - CTR_WIDTH'(decr_cnt[i]);
-
-        always @(posedge clk) begin
-            if (reset) begin
-                incr_cnt[i]       <= '0;
-                decr_cnt[i]       <= '0;
-                pending_instrs[i] <= '0;
-                alm_empty_r[i]    <= 0;
-                empty_r[i]        <= 1;
-            end else begin            
-                incr_cnt[i]       <= incr_cnt_n[i];
-                decr_cnt[i]       <= decr_cnt_n;
-                pending_instrs[i] <= pending_instrs_n;
-                alm_empty_r[i]    <= (pending_instrs_n == ALM_EMPTY);
-                empty_r[i]        <= (pending_instrs_n == 0);
-            end
-		end
-	end
-
-    assign alm_empty = alm_empty_r[alm_empty_wid];
-    assign empty = (& empty_r);
-
-endmodule

hw/rtl/core/VX_schedule.sv

@@ -1,411 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_schedule import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (    
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    VX_pipeline_perf_if.schedule perf_schedule_if,
-`endif
-
-    // configuration
-    input base_dcrs_t       base_dcrs,
-
-    // inputsdecode_if
-    VX_warp_ctl_if.slave    warp_ctl_if, 
-    VX_branch_ctl_if.slave  branch_ctl_if [`NUM_ALU_BLOCKS],
-    VX_decode_sched_if.slave decode_sched_if,
-    VX_commit_sched_if.slave commit_sched_if,
-
-    // outputs
-    VX_schedule_if.master   schedule_if,
-`ifdef GBAR_ENABLE
-    VX_gbar_bus_if.master   gbar_bus_if,
-`endif
-    VX_sched_csr_if.master  sched_csr_if,
-
-    // status
-    output wire             busy
-);
-    `UNUSED_PARAM (CORE_ID)
-
-    reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // updated when a warp is activated or disabled
-    reg [`NUM_WARPS-1:0] stalled_warps, stalled_warps_n;  // set when branch/gpgpu instructions are issued
-    
-    reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, thread_masks_n;
-    reg [`NUM_WARPS-1:0][`XLEN-1:0] warp_pcs, warp_pcs_n;
-
-    wire [`NW_WIDTH-1:0]    schedule_wid;
-    wire [`NUM_THREADS-1:0] schedule_tmask;
-    wire [`XLEN-1:0]        schedule_pc;
-    wire                    schedule_valid;
-    wire                    schedule_ready;
-
-    // split/join
-    wire                    join_valid;
-    wire                    join_is_dvg;
-    wire                    join_is_else;
-    wire [`NW_WIDTH-1:0]    join_wid;   
-    wire [`NUM_THREADS-1:0] join_tmask;
-    wire [`XLEN-1:0]        join_pc;
-
-    reg [`PERF_CTR_BITS-1:0] cycles;
-
-    reg [`NUM_WARPS-1:0][`UUID_WIDTH-1:0] issued_instrs;
-
-    wire schedule_fire = schedule_valid && schedule_ready;
-    wire schedule_if_fire = schedule_if.valid && schedule_if.ready;
-
-    // branch
-    wire [`NUM_ALU_BLOCKS-1:0]                  branch_valid;    
-    wire [`NUM_ALU_BLOCKS-1:0][`NW_WIDTH-1:0]   branch_wid;    
-    wire [`NUM_ALU_BLOCKS-1:0]                  branch_taken;
-    wire [`NUM_ALU_BLOCKS-1:0][`XLEN-1:0]       branch_dest;
-    for (genvar i = 0; i < `NUM_ALU_BLOCKS; ++i) begin
-        assign branch_valid[i] = branch_ctl_if[i].valid;
-        assign branch_wid[i]   = branch_ctl_if[i].wid;
-        assign branch_taken[i] = branch_ctl_if[i].taken;
-        assign branch_dest[i]  = branch_ctl_if[i].dest;
-    end
-
-    // barriers
-    reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks, barrier_masks_n;
-    reg [`NUM_WARPS-1:0] barrier_stalls, barrier_stalls_n;
-    wire [`CLOG2(`NUM_WARPS+1)-1:0] active_barrier_count;
-    wire [`NUM_WARPS-1:0] curr_barrier_mask;    
-`ifdef GBAR_ENABLE
-    reg [`NUM_WARPS-1:0] curr_barrier_mask_n;
-    reg gbar_req_valid;
-    reg [`NB_WIDTH-1:0] gbar_req_id;
-    reg [`NC_WIDTH-1:0] gbar_req_size_m1;
-`endif
-
-    assign curr_barrier_mask = barrier_masks[warp_ctl_if.barrier.id];
-    `POP_COUNT(active_barrier_count, curr_barrier_mask);
-    `UNUSED_VAR (active_barrier_count)
-
-    always @(*) begin
-        active_warps_n  = active_warps;
-        stalled_warps_n = stalled_warps;
-        thread_masks_n  = thread_masks;
-        barrier_masks_n = barrier_masks;
-        barrier_stalls_n= barrier_stalls;
-        warp_pcs_n      = warp_pcs;
-
-        // wspawn handling
-        if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin
-            active_warps_n |= warp_ctl_if.wspawn.wmask;
-            for (integer i = 0; i < `NUM_WARPS; ++i) begin
-                if (warp_ctl_if.wspawn.wmask[i]) begin
-                    thread_masks_n[i][0] = 1;
-                    warp_pcs_n[i] = warp_ctl_if.wspawn.pc;
-                end
-            end
-            stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
-        end
-        
-        // TMC handling
-        if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin
-            active_warps_n[warp_ctl_if.wid]  = (warp_ctl_if.tmc.tmask != 0);
-            thread_masks_n[warp_ctl_if.wid]  = warp_ctl_if.tmc.tmask;
-            stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
-        end
-        
-        // split handling
-        if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin
-            if (warp_ctl_if.split.is_dvg) begin
-                thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.split.then_tmask;
-            end
-            stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
-        end
-
-        // join handling
-        if (join_valid) begin
-            if (join_is_dvg) begin
-                if (join_is_else) begin
-                    warp_pcs_n[join_wid] = join_pc;
-                end
-                thread_masks_n[join_wid] = join_tmask;
-            end
-            stalled_warps_n[join_wid] = 0; // unlock warp
-        end
-
-        // barrier handling        
-    `ifdef GBAR_ENABLE
-        curr_barrier_mask_n = curr_barrier_mask;
-        curr_barrier_mask_n[warp_ctl_if.wid] = 1;
-    `endif
-        if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin
-            if (~warp_ctl_if.barrier.is_global 
-             && (active_barrier_count[`NW_WIDTH-1:0] == warp_ctl_if.barrier.size_m1[`NW_WIDTH-1:0])) begin                                
-                barrier_masks_n[warp_ctl_if.barrier.id] = '0;
-                barrier_stalls_n &= ~barrier_masks[warp_ctl_if.barrier.id];
-            end else begin
-                barrier_masks_n[warp_ctl_if.barrier.id][warp_ctl_if.wid] = 1;
-                barrier_stalls_n[warp_ctl_if.wid] = 1;
-            end
-            stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp
-        end
-    `ifdef GBAR_ENABLE
-        if (gbar_bus_if.rsp_valid && (gbar_req_id == gbar_bus_if.rsp_id)) begin
-            barrier_masks_n[gbar_bus_if.rsp_id] = '0;
-            barrier_stalls_n = '0; // unlock all warps
-        end
-    `endif
-
-        // Branch handling
-        for (integer i = 0; i < `NUM_ALU_BLOCKS; ++i) begin
-            if (branch_valid[i]) begin
-                if (branch_taken[i]) begin
-                    warp_pcs_n[branch_wid[i]] = branch_dest[i];
-                end
-                stalled_warps_n[branch_wid[i]] = 0; // unlock warp
-            end
-        end
-
-        // decode unlock
-        if (decode_sched_if.valid && ~decode_sched_if.is_wstall) begin
-            stalled_warps_n[decode_sched_if.wid] = 0;
-        end
-
-        // CSR unlock
-        if (sched_csr_if.unlock_warp) begin
-            stalled_warps_n[sched_csr_if.unlock_wid] = 0;
-        end
-
-        // stall the warp until decode stage
-        if (schedule_fire) begin
-            stalled_warps_n[schedule_wid] = 1;
-        end
-
-        // advance PC
-        if (schedule_if_fire) begin
-            warp_pcs_n[schedule_if.data.wid] = schedule_if.data.PC + 4;
-        end
-    end
-
-    `UNUSED_VAR (base_dcrs)
-
-    always @(posedge clk) begin
-        if (reset) begin
-            barrier_masks   <= '0;
-        `ifdef GBAR_ENABLE
-            gbar_req_valid  <= 0;
-        `endif
-            stalled_warps   <= '0;
-            warp_pcs        <= '0;
-            active_warps    <= '0;
-            thread_masks    <= '0;
-            barrier_stalls  <= '0;
-            issued_instrs   <= '0;
-            cycles          <= '0;
-
-            // activate first warp
-            warp_pcs[0]     <= base_dcrs.startup_addr;
-            active_warps[0] <= 1;
-            thread_masks[0][0] <= 1;
-        end else begin
-            active_warps   <= active_warps_n;
-            stalled_warps  <= stalled_warps_n;
-            thread_masks   <= thread_masks_n;
-            warp_pcs       <= warp_pcs_n;
-            barrier_masks  <= barrier_masks_n;
-            barrier_stalls <= barrier_stalls_n;
-
-            // global barrier scheduling
-        `ifdef GBAR_ENABLE
-            if (warp_ctl_if.valid && warp_ctl_if.barrier.valid
-             && warp_ctl_if.barrier.is_global 
-             && (curr_barrier_mask_n == active_warps)) begin
-                gbar_req_valid <= 1;
-                gbar_req_id <= warp_ctl_if.barrier.id;
-                gbar_req_size_m1 <= warp_ctl_if.barrier.size_m1[`NC_WIDTH-1:0];
-            end
-            if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin
-                gbar_req_valid <= 0;
-            end
-        `endif
-
-            if (schedule_if_fire) begin
-                issued_instrs[schedule_if.data.wid] <= issued_instrs[schedule_if.data.wid] + `UUID_WIDTH'(1);
-            end
-
-            if (busy) begin
-                cycles <= cycles + 1;
-            end            
-        end
-    end
-
-    // barrier handling
-
-`ifdef GBAR_ENABLE
-    assign gbar_bus_if.req_valid   = gbar_req_valid;
-    assign gbar_bus_if.req_id      = gbar_req_id;
-    assign gbar_bus_if.req_size_m1 = gbar_req_size_m1;
-    assign gbar_bus_if.req_core_id = `NC_WIDTH'(CORE_ID % `NUM_CORES);
-`endif
-
-    // split/join handling
-
-    `RESET_RELAY (split_join_reset, reset);
-
-    VX_split_join #(
-        .CORE_ID (CORE_ID)
-    ) split_join (
-        .clk        (clk),
-        .reset      (split_join_reset),
-        .valid      (warp_ctl_if.valid),
-        .wid        (warp_ctl_if.wid),
-        .split      (warp_ctl_if.split),
-        .sjoin      (warp_ctl_if.sjoin),
-        .join_valid (join_valid),
-        .join_is_dvg (join_is_dvg),
-        .join_is_else (join_is_else),
-        .join_wid   (join_wid), 
-        .join_tmask (join_tmask),
-        .join_pc    (join_pc)
-    );
-
-    // schedule the next ready warp
-
-    wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
-
-    VX_lzc #(
-        .N       (`NUM_WARPS),
-        .REVERSE (1)
-    ) wid_select (
-        .data_in   (ready_warps),
-        .data_out  (schedule_wid),
-        .valid_out (schedule_valid)
-    );
-
-    wire [`NUM_WARPS-1:0][(`NUM_THREADS + `XLEN)-1:0] schedule_data;
-    for (genvar i = 0; i < `NUM_WARPS; ++i) begin
-        assign schedule_data[i] = {thread_masks[i], warp_pcs[i]};
-    end
-
-    assign {schedule_tmask, schedule_pc} = {
-        schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-1:(`NUM_THREADS + `XLEN)-4], 
-        schedule_data[schedule_wid][(`NUM_THREADS + `XLEN)-5:0]
-    };
-
-`ifndef NDEBUG
-    localparam GNW_WIDTH = `LOG2UP(`NUM_CLUSTERS * `NUM_CORES * `NUM_WARPS);
-    reg [`UUID_WIDTH-1:0] instr_uuid;
-    wire [GNW_WIDTH-1:0] g_wid = (GNW_WIDTH'(CORE_ID) << `NW_BITS) + GNW_WIDTH'(schedule_wid);
-`ifdef SV_DPI
-    always @(posedge clk) begin
-        if (reset) begin
-            instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(1, 0, 0));
-        end else if (schedule_fire) begin
-            instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(0, 32'(g_wid), 64'(schedule_pc)));
-        end        
-    end
-`else
-    wire [GNW_WIDTH+16-1:0] w_uuid = {g_wid, 16'(schedule_pc)};
-    always @(*) begin
-        instr_uuid = `UUID_WIDTH'(w_uuid);
-    end
-`endif
-`else
-    wire [`UUID_WIDTH-1:0] instr_uuid = '0;
-`endif
-
-    VX_elastic_buffer #( 
-        .DATAW (`NUM_THREADS + `XLEN + `NW_WIDTH)
-    ) out_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (schedule_valid),
-        .ready_in  (schedule_ready),
-        .data_in   ({schedule_tmask, schedule_pc, schedule_wid}),
-        .data_out  ({schedule_if.data.tmask, schedule_if.data.PC, schedule_if.data.wid}),
-        .valid_out (schedule_if.valid),
-        .ready_out (schedule_if.ready)
-    );
-
-    assign schedule_if.data.uuid = instr_uuid;
-
-    `RESET_RELAY (pending_instr_reset, reset);
-
-    wire no_pending_instr;
-    VX_pending_instr #( 
-        .CTR_WIDTH  (12),
-        .DECR_COUNT (`ISSUE_WIDTH),
-        .ALM_EMPTY  (1)
-    ) pending_instr(
-        .clk       (clk),
-        .reset     (pending_instr_reset),
-        .incr      (schedule_if_fire),
-        .incr_wid  (schedule_if.data.wid),
-        .decr      (commit_sched_if.committed),
-        .decr_wid  (commit_sched_if.committed_wid),
-        .alm_empty_wid (sched_csr_if.alm_empty_wid),
-        .alm_empty (sched_csr_if.alm_empty),
-        .empty     (no_pending_instr)
-    );
-
-    `BUFFER_EX(busy, (active_warps != 0 || ~no_pending_instr), 1'b1, 1);
-
-    // export CSRs
-    assign sched_csr_if.cycles = cycles;
-    assign sched_csr_if.active_warps = active_warps;
-    assign sched_csr_if.thread_masks = thread_masks;
-          
-   // timeout handling
-    reg [31:0] timeout_ctr;
-    reg timeout_enable;
-    always @(posedge clk) begin
-        if (reset) begin
-            timeout_ctr    <= '0;
-            timeout_enable <= 0;
-        end else begin
-            if (decode_sched_if.valid && ~decode_sched_if.is_wstall) begin
-                timeout_enable <= 1;
-            end
-            if (timeout_enable && active_warps !=0 && active_warps == stalled_warps) begin
-                timeout_ctr <= timeout_ctr + 1;
-            end else if (active_warps == 0 || active_warps != stalled_warps) begin
-                timeout_ctr <= '0;
-            end
-        end
-    end
-    `RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT, ("%t: *** core%0d-scheduler-timeout: stalled_warps=%b", $time, CORE_ID, stalled_warps));
-
-`ifdef PERF_ENABLE    
-    reg [`PERF_CTR_BITS-1:0] perf_sched_idles;
-    reg [`PERF_CTR_BITS-1:0] perf_sched_stalls;
-
-    wire schedule_idle = ~schedule_valid;
-    wire schedule_stall = schedule_if.valid && ~schedule_if.ready;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_sched_idles  <= '0;
-            perf_sched_stalls <= '0;            
-        end else begin
-            perf_sched_idles  <= perf_sched_idles + `PERF_CTR_BITS'(schedule_idle);
-            perf_sched_stalls <= perf_sched_stalls + `PERF_CTR_BITS'(schedule_stall);
-        end
-    end
-
-    assign perf_schedule_if.sched_idles = perf_sched_idles;
-    assign perf_schedule_if.sched_stalls = perf_sched_stalls;    
-`endif
-
-endmodule

hw/rtl/core/VX_scoreboard.sv

@@ -1,228 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_scoreboard import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    output reg [`PERF_CTR_BITS-1:0] perf_scb_stalls,
-    output reg [`PERF_CTR_BITS-1:0] perf_units_uses [`NUM_EX_UNITS],
-    output reg [`PERF_CTR_BITS-1:0] perf_sfu_uses [`NUM_SFU_UNITS],
-`endif
-
-    VX_writeback_if.slave   writeback_if [`ISSUE_WIDTH],
-    VX_ibuffer_if.slave     ibuffer_if [`ISSUE_WIDTH],
-    VX_ibuffer_if.master    scoreboard_if [`ISSUE_WIDTH]
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4) + 1;
-
-`ifdef PERF_ENABLE
-    reg [`ISSUE_WIDTH-1:0][`NUM_EX_UNITS-1:0] perf_issue_units_per_cycle;
-    wire [`NUM_EX_UNITS-1:0] perf_units_per_cycle, perf_units_per_cycle_r;
-
-    reg [`ISSUE_WIDTH-1:0][`NUM_SFU_UNITS-1:0] perf_issue_sfu_per_cycle;    
-    wire [`NUM_SFU_UNITS-1:0] perf_sfu_per_cycle, perf_sfu_per_cycle_r;
-
-    wire [`ISSUE_WIDTH-1:0] perf_issue_stalls_per_cycle;
-    wire [`CLOG2(`ISSUE_WIDTH+1)-1:0] perf_stalls_per_cycle, perf_stalls_per_cycle_r;    
-
-    `POP_COUNT(perf_stalls_per_cycle, perf_issue_stalls_per_cycle);    
-
-    VX_reduce #(
-        .DATAW_IN (`NUM_EX_UNITS),
-        .N  (`ISSUE_WIDTH),
-        .OP ("|")
-    ) perf_units_reduce (
-        .data_in  (perf_issue_units_per_cycle),
-        .data_out (perf_units_per_cycle)
-    );    
-
-    VX_reduce #(
-        .DATAW_IN (`NUM_SFU_UNITS),
-        .N  (`ISSUE_WIDTH),
-        .OP ("|")
-    ) perf_sfu_reduce (
-        .data_in  (perf_issue_sfu_per_cycle),
-        .data_out (perf_sfu_per_cycle)
-    );
-
-    `BUFFER(perf_stalls_per_cycle_r, perf_stalls_per_cycle);
-    `BUFFER(perf_units_per_cycle_r, perf_units_per_cycle);
-    `BUFFER(perf_sfu_per_cycle_r, perf_sfu_per_cycle);
-
-    always @(posedge clk) begin
-        if (reset) begin
-            perf_scb_stalls <= '0;            
-        end else begin
-            perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'(perf_stalls_per_cycle_r);
-        end
-    end
-
-    for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
-        always @(posedge clk) begin
-            if (reset) begin
-                perf_units_uses[i] <= '0;
-            end else begin
-                perf_units_uses[i] <= perf_units_uses[i] + `PERF_CTR_BITS'(perf_units_per_cycle_r[i]);
-            end
-        end
-    end
-    
-    for (genvar i = 0; i < `NUM_SFU_UNITS; ++i) begin
-        always @(posedge clk) begin
-            if (reset) begin
-                perf_sfu_uses[i] <= '0;
-            end else begin
-                perf_sfu_uses[i] <= perf_sfu_uses[i] + `PERF_CTR_BITS'(perf_sfu_per_cycle_r[i]);
-            end
-        end
-    end
-`endif
-
-    for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
-        reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0] inuse_regs;
-
-        wire writeback_fire = writeback_if[i].valid && writeback_if[i].data.eop;
-
-        wire inuse_rd  = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd];
-        wire inuse_rs1 = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1];
-        wire inuse_rs2 = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2];
-        wire inuse_rs3 = inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3];
-
-    `ifdef PERF_ENABLE
-        reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0][`EX_WIDTH-1:0] inuse_units;   
-        reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0][`SFU_WIDTH-1:0] inuse_sfu;        
-
-        reg [`SFU_WIDTH-1:0] sfu_type;
-        always @(*) begin
-            case (ibuffer_if[i].data.op_type)
-            `INST_SFU_CSRRW,
-            `INST_SFU_CSRRS,
-            `INST_SFU_CSRRC: sfu_type = `SFU_CSRS;
-            default: sfu_type = `SFU_WCTL;
-            endcase
-        end
-
-        always @(*) begin
-            perf_issue_units_per_cycle[i] = '0;
-            perf_issue_sfu_per_cycle[i] = '0;
-            if (ibuffer_if[i].valid) begin
-                if (inuse_rd) begin
-                    perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd]] = 1;
-                    if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] == `EX_SFU) begin
-                        perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd]] = 1;
-                    end
-                end
-                if (inuse_rs1) begin
-                    perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1]] = 1;
-                    if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1] == `EX_SFU) begin
-                        perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1]] = 1;
-                    end
-                end
-                if (inuse_rs2) begin
-                    perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2]] = 1;
-                    if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2] == `EX_SFU) begin
-                        perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2]] = 1;
-                    end
-                end
-                if (inuse_rs3) begin
-                    perf_issue_units_per_cycle[i][inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3]] = 1;
-                    if (inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3] == `EX_SFU) begin
-                        perf_issue_sfu_per_cycle[i][inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3]] = 1;
-                    end
-                end
-            end
-        end
-        assign perf_issue_stalls_per_cycle[i] = ibuffer_if[i].valid && ~ibuffer_if[i].ready;
-    `endif
-
-        wire [3:0] operands_busy = {inuse_rd, inuse_rs1, inuse_rs2, inuse_rs3};
-        wire operands_ready = ~(| operands_busy);
-        
-        wire stg_valid_in, stg_ready_in;
-        assign stg_valid_in = ibuffer_if[i].valid && operands_ready;
-        assign ibuffer_if[i].ready = stg_ready_in && operands_ready;        
-
-        VX_stream_buffer #(
-            .DATAW (DATAW)
-        ) staging_buffer (
-            .clk       (clk),
-            .reset     (reset),
-            .valid_in  (stg_valid_in),
-            .data_in   (ibuffer_if[i].data),
-            .ready_in  (stg_ready_in),
-            .valid_out (scoreboard_if[i].valid),
-            .data_out  (scoreboard_if[i].data),
-            .ready_out (scoreboard_if[i].ready)
-        );
-
-        always @(posedge clk) begin
-            if (reset) begin
-                inuse_regs <= '0;
-            end else begin
-                if (writeback_fire) begin
-                    inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] <= 0;            
-                end
-                if (ibuffer_if[i].valid && ibuffer_if[i].ready && ibuffer_if[i].data.wb) begin
-                    inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] <= 1;
-                end
-            end
-        `ifdef PERF_ENABLE
-            if (ibuffer_if[i].valid && ibuffer_if[i].ready && ibuffer_if[i].data.wb) begin
-                inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] <= ibuffer_if[i].data.ex_type;
-                if (ibuffer_if[i].data.ex_type == `EX_SFU) begin
-                    inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] <= sfu_type;
-                end
-            end
-        `endif
-        end
-
-    `ifdef SIMULATION
-        reg [31:0] timeout_ctr;       
-
-        always @(posedge clk) begin
-            if (reset) begin
-                timeout_ctr <= '0;
-            end else begin        
-                if (ibuffer_if[i].valid && ~ibuffer_if[i].ready) begin
-                `ifdef DBG_TRACE_CORE_PIPELINE
-                    `TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n",
-                        $time, CORE_ID, wis_to_wid(ibuffer_if[i].data.wis, i), ibuffer_if[i].data.PC, ibuffer_if[i].data.tmask, timeout_ctr,
-                        operands_busy, ibuffer_if[i].data.uuid));
-                `endif
-                    timeout_ctr <= timeout_ctr + 1;
-                end else if (ibuffer_if[i].valid && ibuffer_if[i].ready) begin
-                    timeout_ctr <= '0;
-                end
-            end
-        end
-        
-        `RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT),
-                        ("%t: *** core%0d-scoreboard-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)",
-                            $time, CORE_ID, wis_to_wid(ibuffer_if[i].data.wis, i), ibuffer_if[i].data.PC, ibuffer_if[i].data.tmask, timeout_ctr,
-                            operands_busy, ibuffer_if[i].data.uuid));
-
-        `RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] != 0,
-            ("%t: *** core%0d: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",
-                $time, CORE_ID, wis_to_wid(writeback_if[i].data.wis, i), writeback_if[i].data.PC, writeback_if[i].data.tmask, writeback_if[i].data.rd, writeback_if[i].data.uuid));
-    `endif
-    
-    end
-
-endmodule

hw/rtl/core/VX_sfu_unit.sv

@@ -1,193 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_sfu_unit import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (    
-    input wire              clk,
-    input wire              reset,
-
-`ifdef PERF_ENABLE
-    VX_mem_perf_if.slave    mem_perf_if,
-    VX_pipeline_perf_if.slave pipeline_perf_if,
-`endif
-
-    input base_dcrs_t       base_dcrs,
-
-    // Inputs
-    VX_dispatch_if.slave    dispatch_if [`ISSUE_WIDTH],
-    
-`ifdef EXT_F_ENABLE
-    VX_fpu_to_csr_if.slave  fpu_to_csr_if [`NUM_FPU_BLOCKS],
-`endif
-
-    // Outputs
-    VX_commit_if.master     commit_if [`ISSUE_WIDTH],
-    VX_commit_csr_if.slave  commit_csr_if,
-    VX_sched_csr_if.slave   sched_csr_if,
-    VX_warp_ctl_if.master   warp_ctl_if    
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam BLOCK_SIZE   = 1;
-    localparam NUM_LANES    = `NUM_SFU_LANES;
-    localparam PID_BITS     = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH    = `UP(PID_BITS);
-
-    localparam RSP_ARB_DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + (NUM_LANES * `XLEN) + `NR_BITS + 1 + `XLEN + PID_WIDTH + 1 + 1;
-    localparam RSP_ARB_SIZE = 1 + 1;
-    localparam RSP_ARB_IDX_WCTL = 0;
-    localparam RSP_ARB_IDX_CSRS = 1;
-
-    VX_execute_if #(
-        .NUM_LANES (NUM_LANES)
-    ) execute_if[BLOCK_SIZE]();
-
-    `RESET_RELAY (dispatch_reset, reset);
-
-    VX_dispatch_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (1)
-    ) dispatch_unit (
-        .clk        (clk),
-        .reset      (dispatch_reset),
-        .dispatch_if(dispatch_if),
-        .execute_if (execute_if)
-    );
-
-    wire [RSP_ARB_SIZE-1:0] rsp_arb_valid_in;
-    wire [RSP_ARB_SIZE-1:0] rsp_arb_ready_in;
-    wire [RSP_ARB_SIZE-1:0][RSP_ARB_DATAW-1:0] rsp_arb_data_in;
-    
-
-    // Warp control block    
-    VX_execute_if #(
-        .NUM_LANES (NUM_LANES)
-    ) wctl_execute_if();
-    VX_commit_if#(
-        .NUM_LANES (NUM_LANES)
-    ) wctl_commit_if();
-    
-    assign wctl_execute_if.valid = execute_if[0].valid && `INST_SFU_IS_WCTL(execute_if[0].data.op_type);
-    assign wctl_execute_if.data = execute_if[0].data;
-
-    `RESET_RELAY (wctl_reset, reset);
-    
-    VX_wctl_unit #(
-        .CORE_ID   (CORE_ID),
-        .NUM_LANES (NUM_LANES)
-    ) wctl_unit (
-        .clk        (clk),
-        .reset      (wctl_reset),
-        .execute_if (wctl_execute_if), 
-        .warp_ctl_if(warp_ctl_if), 
-        .commit_if  (wctl_commit_if)
-    );
-
-    assign rsp_arb_valid_in[RSP_ARB_IDX_WCTL] = wctl_commit_if.valid;
-    assign rsp_arb_data_in[RSP_ARB_IDX_WCTL] = wctl_commit_if.data;
-    assign wctl_commit_if.ready = rsp_arb_ready_in[RSP_ARB_IDX_WCTL];
-
-    // CSR unit
-    VX_execute_if #(
-        .NUM_LANES (NUM_LANES)
-    ) csr_execute_if();
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) csr_commit_if();
-
-    assign csr_execute_if.valid = execute_if[0].valid && `INST_SFU_IS_CSR(execute_if[0].data.op_type);
-    assign csr_execute_if.data = execute_if[0].data;
-
-    `RESET_RELAY (csr_reset, reset);
-
-    VX_csr_unit #(
-        .CORE_ID   (CORE_ID),
-        .NUM_LANES (NUM_LANES)
-    ) csr_unit (
-        .clk            (clk),
-        .reset          (csr_reset),
-
-        .base_dcrs      (base_dcrs),
-        .execute_if     (csr_execute_if),
-    
-    `ifdef PERF_ENABLE
-        .mem_perf_if    (mem_perf_if),
-        .pipeline_perf_if(pipeline_perf_if),
-    `endif
-   
-    `ifdef EXT_F_ENABLE  
-        .fpu_to_csr_if  (fpu_to_csr_if),
-    `endif
-
-        .sched_csr_if   (sched_csr_if),
-        .commit_csr_if  (commit_csr_if),
-        .commit_if      (csr_commit_if)
-    );    
-
-    assign rsp_arb_valid_in[RSP_ARB_IDX_CSRS] = csr_commit_if.valid;
-    assign rsp_arb_data_in[RSP_ARB_IDX_CSRS] = csr_commit_if.data;
-    assign csr_commit_if.ready = rsp_arb_ready_in[RSP_ARB_IDX_CSRS];
-
-    // can accept new request?
-
-    reg sfu_req_ready;
-    always @(*) begin
-        case (execute_if[0].data.op_type)
-         `INST_SFU_CSRRW,
-         `INST_SFU_CSRRS,
-         `INST_SFU_CSRRC: sfu_req_ready = csr_execute_if.ready;
-        default: sfu_req_ready = wctl_execute_if.ready;
-        endcase
-    end
-    assign execute_if[0].ready = sfu_req_ready;
-
-    // response arbitration
-    
-    `RESET_RELAY (commit_reset, reset);
-
-    VX_commit_if #(
-        .NUM_LANES (NUM_LANES)
-    ) arb_commit_if[BLOCK_SIZE]();
-
-    VX_stream_arb #(
-        .NUM_INPUTS (RSP_ARB_SIZE),
-        .DATAW      (RSP_ARB_DATAW),
-        .ARBITER    ("R"),
-        .OUT_REG    (3)
-    ) rsp_arb (
-        .clk       (clk),
-        .reset     (commit_reset), 
-        .valid_in  (rsp_arb_valid_in),
-        .ready_in  (rsp_arb_ready_in),
-        .data_in   (rsp_arb_data_in),
-        .data_out  (arb_commit_if[0].data),
-        .valid_out (arb_commit_if[0].valid),
-        .ready_out (arb_commit_if[0].ready),
-        `UNUSED_PIN (sel_out)
-    );
-
-    VX_gather_unit #(
-        .BLOCK_SIZE (BLOCK_SIZE),
-        .NUM_LANES  (NUM_LANES),
-        .OUT_REG    (1)
-    ) gather_unit (
-        .clk           (clk),
-        .reset         (commit_reset),
-        .commit_in_if  (arb_commit_if),
-        .commit_out_if (commit_if)
-    );
-
-endmodule

hw/rtl/core/VX_smem_unit.sv

@@ -1,124 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_smem_unit import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input wire              clk,
-    input wire              reset,
-    
-`ifdef PERF_ENABLE
-    output cache_perf_t     cache_perf,
-`endif
-
-    VX_mem_bus_if.slave     dcache_bus_in_if [DCACHE_NUM_REQS],
-    VX_mem_bus_if.master    dcache_bus_out_if [DCACHE_NUM_REQS]
-);
-    `UNUSED_PARAM (CORE_ID)
-
-    localparam SMEM_ADDR_WIDTH = `SMEM_LOG_SIZE - `CLOG2(DCACHE_WORD_SIZE);
-
-    wire [DCACHE_NUM_REQS-1:0]                  smem_req_valid;
-    wire [DCACHE_NUM_REQS-1:0]                  smem_req_rw;
-    wire [DCACHE_NUM_REQS-1:0][SMEM_ADDR_WIDTH-1:0] smem_req_addr;
-    wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] smem_req_byteen;
-    wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] smem_req_data;
-    wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] smem_req_tag;
-    wire [DCACHE_NUM_REQS-1:0]                  smem_req_ready;
-    wire [DCACHE_NUM_REQS-1:0]                  smem_rsp_valid;
-    wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] smem_rsp_data;
-    wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] smem_rsp_tag;
-    wire [DCACHE_NUM_REQS-1:0]                  smem_rsp_ready;
-
-    `RESET_RELAY (smem_reset, reset);
-    
-    VX_shared_mem #(
-        .INSTANCE_ID($sformatf("core%0d-smem", CORE_ID)),
-        .SIZE       (1 << `SMEM_LOG_SIZE),
-        .NUM_REQS   (DCACHE_NUM_REQS),
-        .NUM_BANKS  (`SMEM_NUM_BANKS),
-        .WORD_SIZE  (DCACHE_WORD_SIZE),
-        .ADDR_WIDTH (SMEM_ADDR_WIDTH),
-        .UUID_WIDTH (`UUID_WIDTH), 
-        .TAG_WIDTH  (DCACHE_NOSM_TAG_WIDTH)
-    ) shared_mem (        
-        .clk        (clk),
-        .reset      (smem_reset),
-
-    `ifdef PERF_ENABLE
-        .cache_perf (cache_perf),
-    `endif
-
-        // Core request
-        .req_valid  (smem_req_valid),
-        .req_rw     (smem_req_rw),
-        .req_byteen (smem_req_byteen),
-        .req_addr   (smem_req_addr),
-        .req_data   (smem_req_data),        
-        .req_tag    (smem_req_tag),
-        .req_ready  (smem_req_ready),
-
-        // Core response
-        .rsp_valid  (smem_rsp_valid),
-        .rsp_data   (smem_rsp_data),
-        .rsp_tag    (smem_rsp_tag),
-        .rsp_ready  (smem_rsp_ready)
-    );
-
-    VX_mem_bus_if #(
-        .DATA_SIZE (DCACHE_WORD_SIZE),
-        .TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
-    ) switch_out_bus_if[2 * DCACHE_NUM_REQS]();
-
-    `RESET_RELAY (switch_reset, reset);
-
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-
-        assign smem_req_valid[i] = switch_out_bus_if[i * 2 + 1].req_valid;
-        assign smem_req_rw[i] = switch_out_bus_if[i * 2 + 1].req_data.rw;
-        assign smem_req_byteen[i] = switch_out_bus_if[i * 2 + 1].req_data.byteen;
-        assign smem_req_data[i] = switch_out_bus_if[i * 2 + 1].req_data.data;
-        assign smem_req_tag[i] = switch_out_bus_if[i * 2 + 1].req_data.tag;
-        assign switch_out_bus_if[i * 2 + 1].req_ready = smem_req_ready[i];
-
-        assign switch_out_bus_if[i * 2 + 1].rsp_valid = smem_rsp_valid[i];
-        assign switch_out_bus_if[i * 2 + 1].rsp_data.data = smem_rsp_data[i];
-        assign switch_out_bus_if[i * 2 + 1].rsp_data.tag = smem_rsp_tag[i];
-        assign smem_rsp_ready[i] = switch_out_bus_if[i * 2 + 1].rsp_ready;
-
-        assign smem_req_addr[i] = switch_out_bus_if[i * 2 + 1].req_data.addr[SMEM_ADDR_WIDTH-1:0];
-
-        VX_smem_switch #(
-            .NUM_REQS     (2),
-            .DATA_SIZE    (DCACHE_WORD_SIZE),
-            .TAG_WIDTH    (DCACHE_TAG_WIDTH),
-            .TAG_SEL_IDX  (0),
-            .ARBITER      ("P"),
-            .OUT_REG_REQ  (2),
-            .OUT_REG_RSP  (2)
-        ) smem_switch (
-            .clk        (clk),
-            .reset      (switch_reset),
-            .bus_in_if  (dcache_bus_in_if[i]),
-            .bus_out_if (switch_out_bus_if[i * 2 +: 2])
-        );
-    end
-
-    // this bus goes to the dcache
-    for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
-        `ASSIGN_VX_MEM_BUS_IF (dcache_bus_out_if[i], switch_out_bus_if[i * 2]);
-    end
-
-endmodule

hw/rtl/core/VX_split_join.sv

@@ -1,76 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_split_join import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0
-) (
-    input  wire                     clk,
-    input  wire                     reset,
-    input  wire                     valid,
-    input  wire [`NW_WIDTH-1:0]     wid,
-    input  split_t                  split,
-    input  join_t                   sjoin,
-    output wire                     join_valid,
-    output wire                     join_is_dvg,
-    output wire                     join_is_else,
-    output wire [`NW_WIDTH-1:0]     join_wid,
-    output wire [`NUM_THREADS-1:0]  join_tmask,
-    output wire [`XLEN-1:0]         join_pc
-);
-    `UNUSED_PARAM (CORE_ID)
-    
-    wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_data [`NUM_WARPS-1:0];
-    wire ipdom_set [`NUM_WARPS-1:0];
-
-    wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_q0 = {split.then_tmask | split.else_tmask, `XLEN'(0)};
-    wire [(`XLEN+`NUM_THREADS)-1:0] ipdom_q1 = {split.else_tmask, split.next_pc};
-
-    wire ipdom_push = valid && split.valid && split.is_dvg;
-    wire ipdom_pop = valid && sjoin.valid && sjoin.is_dvg;
-
-    for (genvar i = 0; i < `NUM_WARPS; ++i) begin
-
-        `RESET_RELAY (ipdom_reset, reset);
-
-        VX_ipdom_stack #(
-            .WIDTH (`XLEN+`NUM_THREADS), 
-            .DEPTH (`UP(`NUM_THREADS-1))
-        ) ipdom_stack (
-            .clk   (clk),
-            .reset (ipdom_reset),
-            .push  (ipdom_push && (i == wid)),
-            .pop   (ipdom_pop && (i == wid)),
-            .q0    (ipdom_q0),
-            .q1    (ipdom_q1),
-            .d     (ipdom_data[i]),
-            .d_set (ipdom_set[i]),
-            `UNUSED_PIN (empty),
-            `UNUSED_PIN (full)
-        );
-    end
-
-    VX_pipe_register #(
-        .DATAW  (1 + 1 + `NW_WIDTH + 1 + `XLEN + `NUM_THREADS),
-        .DEPTH  (1),
-        .RESETW (1)
-    ) pipe_reg (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (1'b1),
-        .data_in  ({valid && sjoin.valid, sjoin.is_dvg, ipdom_set[wid], wid, ipdom_data[wid]}),
-        .data_out ({join_valid, join_is_dvg, join_is_else, join_wid, join_tmask, join_pc})
-    );
-
-endmodule

hw/rtl/core/VX_trace.vh

@@ -1,377 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_TRACE_VH
-`define VX_TRACE_VH
-
-`ifdef SIMULATION
-
-task trace_ex_type(input int level, input [`EX_BITS-1:0] ex_type);
-    case (ex_type)
-        `EX_ALU: `TRACE(level, ("ALU"));
-        `EX_LSU: `TRACE(level, ("LSU"));
-        `EX_FPU: `TRACE(level, ("FPU"));
-        `EX_SFU: `TRACE(level, ("SFU"));
-        default: `TRACE(level, ("?"));
-    endcase
-endtask
-
-task trace_ex_op(input int level, 
-                 input [`EX_BITS-1:0] ex_type, 
-                 input [`INST_OP_BITS-1:0] op_type, 
-                 input [`INST_MOD_BITS-1:0] op_mod,                 
-                 `UNUSED_ARG(input [`NR_BITS-1:0] rd),
-                 `UNUSED_ARG(input [`NR_BITS-1:0] rs2),
-                 input use_imm,
-                 `UNUSED_ARG(input [`XLEN-1:0] imm)
-);
-
-`ifdef FLEN_64
-    logic fdst_d = imm[0];
-`else
-    logic fdst_d = 0;
-`endif
-
-`ifdef XLEN_64
-    logic fcvt_l = imm[1];
-`else
-    logic fcvt_l = 0;
-`endif
-
-`ifdef EXT_F_ENABLE
-    logic rd_float = 1'(rd >> 5) || 1'(rs2 >> 5);
-`else
-    logic rd_float = 0;
-`endif
-
-    case (ex_type)
-    `EX_ALU: begin 
-        if (`INST_ALU_IS_BR(op_mod)) begin
-            case (`INST_BR_BITS'(op_type))
-                `INST_BR_EQ:    `TRACE(level, ("BEQ"));
-                `INST_BR_NE:    `TRACE(level, ("BNE"));
-                `INST_BR_LT:    `TRACE(level, ("BLT"));
-                `INST_BR_GE:    `TRACE(level, ("BGE"));
-                `INST_BR_LTU:   `TRACE(level, ("BLTU"));
-                `INST_BR_GEU:   `TRACE(level, ("BGEU"));
-                `INST_BR_JAL:   `TRACE(level, ("JAL"));
-                `INST_BR_JALR:  `TRACE(level, ("JALR"));
-                `INST_BR_ECALL: `TRACE(level, ("ECALL"));
-                `INST_BR_EBREAK:`TRACE(level, ("EBREAK"));
-                `INST_BR_URET:  `TRACE(level, ("URET"));
-                `INST_BR_SRET:  `TRACE(level, ("SRET"));
-                `INST_BR_MRET:  `TRACE(level, ("MRET"));
-                default:        `TRACE(level, ("?"));
-            endcase
-        end else if (`INST_ALU_IS_M(op_mod)) begin
-            if (`INST_ALU_IS_W(op_mod)) begin
-                case (`INST_M_BITS'(op_type))
-                    `INST_M_MUL:  `TRACE(level, ("MULW"));
-                    `INST_M_DIV:  `TRACE(level, ("DIVW"));
-                    `INST_M_DIVU: `TRACE(level, ("DIVUW"));
-                    `INST_M_REM:  `TRACE(level, ("REMW"));
-                    `INST_M_REMU: `TRACE(level, ("REMUW"));
-                    default:      `TRACE(level, ("?"));
-                endcase
-            end else begin
-                case (`INST_M_BITS'(op_type))
-                    `INST_M_MUL:   `TRACE(level, ("MUL"));
-                    `INST_M_MULH:  `TRACE(level, ("MULH"));
-                    `INST_M_MULHSU:`TRACE(level, ("MULHSU"));
-                    `INST_M_MULHU: `TRACE(level, ("MULHU"));
-                    `INST_M_DIV:   `TRACE(level, ("DIV"));
-                    `INST_M_DIVU:  `TRACE(level, ("DIVU"));
-                    `INST_M_REM:   `TRACE(level, ("REM"));
-                    `INST_M_REMU:  `TRACE(level, ("REMU"));
-                    default:       `TRACE(level, ("?"));
-                endcase
-            end
-        end else begin
-            if (`INST_ALU_IS_W(op_mod)) begin
-                if (use_imm) begin
-                    case (`INST_ALU_BITS'(op_type))
-                        `INST_ALU_ADD: `TRACE(level, ("ADDIW"));
-                        `INST_ALU_SLL: `TRACE(level, ("SLLIW"));
-                        `INST_ALU_SRL: `TRACE(level, ("SRLIW"));
-                        `INST_ALU_SRA: `TRACE(level, ("SRAIW"));
-                        default:       `TRACE(level, ("?"));
-                    endcase
-                end else begin
-                    case (`INST_ALU_BITS'(op_type))
-                        `INST_ALU_ADD: `TRACE(level, ("ADDW"));
-                        `INST_ALU_SUB: `TRACE(level, ("SUBW"));
-                        `INST_ALU_SLL: `TRACE(level, ("SLLW"));
-                        `INST_ALU_SRL: `TRACE(level, ("SRLW"));
-                        `INST_ALU_SRA: `TRACE(level, ("SRAW"));
-                        default:       `TRACE(level, ("?"));
-                    endcase
-                end
-            end else begin
-                if (use_imm) begin
-                    case (`INST_ALU_BITS'(op_type))
-                        `INST_ALU_ADD:   `TRACE(level, ("ADDI"));
-                        `INST_ALU_SLL:   `TRACE(level, ("SLLI"));
-                        `INST_ALU_SRL:   `TRACE(level, ("SRLI"));
-                        `INST_ALU_SRA:   `TRACE(level, ("SRAI"));
-                        `INST_ALU_SLT:   `TRACE(level, ("SLTI"));
-                        `INST_ALU_SLTU:  `TRACE(level, ("SLTIU"));
-                        `INST_ALU_XOR:   `TRACE(level, ("XORI"));
-                        `INST_ALU_OR:    `TRACE(level, ("ORI"));
-                        `INST_ALU_AND:   `TRACE(level, ("ANDI"));
-                        `INST_ALU_LUI:   `TRACE(level, ("LUI"));
-                        `INST_ALU_AUIPC: `TRACE(level, ("AUIPC"));
-                        default:         `TRACE(level, ("?"));
-                    endcase
-                end else begin
-                    case (`INST_ALU_BITS'(op_type))
-                        `INST_ALU_ADD:   `TRACE(level, ("ADD"));
-                        `INST_ALU_SUB:   `TRACE(level, ("SUB"));
-                        `INST_ALU_SLL:   `TRACE(level, ("SLL"));
-                        `INST_ALU_SRL:   `TRACE(level, ("SRL"));
-                        `INST_ALU_SRA:   `TRACE(level, ("SRA"));
-                        `INST_ALU_SLT:   `TRACE(level, ("SLT"));
-                        `INST_ALU_SLTU:  `TRACE(level, ("SLTU"));
-                        `INST_ALU_XOR:   `TRACE(level, ("XOR"));
-                        `INST_ALU_OR:    `TRACE(level, ("OR"));
-                        `INST_ALU_AND:   `TRACE(level, ("AND"));
-                        default:         `TRACE(level, ("?"));
-                    endcase
-                end
-            end
-        end
-    end
-    `EX_LSU: begin        
-        if (rd_float) begin
-            case (`INST_LSU_BITS'(op_type))
-                `INST_LSU_LW: `TRACE(level, ("FLW"));
-                `INST_LSU_LD: `TRACE(level, ("FLD"));
-                `INST_LSU_SW: `TRACE(level, ("FSW"));
-                `INST_LSU_SD: `TRACE(level, ("FSD"));
-                default:      `TRACE(level, ("?"));
-            endcase
-        end else begin
-            case (`INST_LSU_BITS'(op_type))
-                `INST_LSU_LB: `TRACE(level, ("LB"));
-                `INST_LSU_LH: `TRACE(level, ("LH"));
-                `INST_LSU_LW: `TRACE(level, ("LW"));
-                `INST_LSU_LD: `TRACE(level, ("LD"));
-                `INST_LSU_LBU:`TRACE(level, ("LBU"));
-                `INST_LSU_LHU:`TRACE(level, ("LHU"));
-                `INST_LSU_LWU:`TRACE(level, ("LWU"));
-                `INST_LSU_SB: `TRACE(level, ("SB"));
-                `INST_LSU_SH: `TRACE(level, ("SH"));
-                `INST_LSU_SW: `TRACE(level, ("SW"));
-                `INST_LSU_SD: `TRACE(level, ("SD"));
-                `INST_LSU_FENCE:`TRACE(level,("FENCE"));
-                default:      `TRACE(level, ("?"));
-            endcase
-        end
-    end
-    `EX_FPU: begin
-        case (`INST_FPU_BITS'(op_type))
-            `INST_FPU_ADD: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FADD.D"));
-                else
-                    `TRACE(level, ("FADD.S"));
-            end
-            `INST_FPU_SUB: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FSUB.D"));
-                else
-                    `TRACE(level, ("FSUB.S"));
-            end
-            `INST_FPU_MUL: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FMUL.D"));
-                else
-                    `TRACE(level, ("FMUL.S"));
-            end
-            `INST_FPU_DIV: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FDIV.D"));
-                else
-                    `TRACE(level, ("FDIV.S"));
-            end
-            `INST_FPU_SQRT: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FSQRT.D"));
-                else
-                    `TRACE(level, ("FSQRT.S"));
-            end
-            `INST_FPU_MADD: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FMADD.D"));
-                else
-                    `TRACE(level, ("FMADD.S"));
-            end
-            `INST_FPU_MSUB: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FMSUB.D"));
-                else
-                    `TRACE(level, ("FMSUB.S"));
-            end
-            `INST_FPU_NMADD: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FNMADD.D"));
-                else
-                    `TRACE(level, ("FNMADD.S"));
-            end
-            `INST_FPU_NMSUB: begin
-                if  (fdst_d) 
-                    `TRACE(level, ("FNMSUB.D"));
-                else
-                    `TRACE(level, ("FNMSUB.S"));
-            end
-            `INST_FPU_CMP: begin
-                if  (fdst_d) begin
-                    case (op_mod[1:0])
-                    0:       `TRACE(level, ("FLE.D"));
-                    1:       `TRACE(level, ("FLT.D"));
-                    2:       `TRACE(level, ("FEQ.D"));
-                    default: `TRACE(level, ("?"));
-                    endcase
-                end else begin
-                    case (op_mod[1:0])
-                    0:       `TRACE(level, ("FLE.S"));
-                    1:       `TRACE(level, ("FLT.S"));
-                    2:       `TRACE(level, ("FEQ.S"));
-                    default: `TRACE(level, ("?"));
-                    endcase
-                end
-            end
-            `INST_FPU_F2F: begin
-                if (fdst_d) begin
-                    `TRACE(level, ("FCVT.D.S"));
-                end else begin
-                    `TRACE(level, ("FCVT.S.D"));
-                end
-            end
-            `INST_FPU_F2I: begin
-                if (fdst_d) begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.L.D"));
-                    end else begin
-                        `TRACE(level, ("FCVT.W.D"));
-                    end
-                end else begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.L.S"));
-                    end else begin
-                        `TRACE(level, ("FCVT.W.S"));
-                    end
-                end
-            end
-            `INST_FPU_F2U: begin
-                if (fdst_d) begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.LU.D"));
-                    end else begin
-                        `TRACE(level, ("FCVT.WU.D"));
-                    end
-                end else begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.LU.S"));
-                    end else begin
-                        `TRACE(level, ("FCVT.WU.S"));
-                    end
-                end
-            end
-            `INST_FPU_I2F: begin
-                if (fdst_d) begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.D.L"));
-                    end else begin
-                        `TRACE(level, ("FCVT.D.W"));
-                    end
-                end else begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.S.L"));
-                    end else begin
-                        `TRACE(level, ("FCVT.S.W"));
-                    end
-                end
-            end
-            `INST_FPU_U2F: begin
-                if (fdst_d) begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.D.LU"));
-                    end else begin
-                        `TRACE(level, ("FCVT.D.WU"));
-                    end
-                end else begin
-                    if (fcvt_l) begin
-                        `TRACE(level, ("FCVT.S.LU"));
-                    end else begin
-                        `TRACE(level, ("FCVT.S.WU"));
-                    end
-                end
-            end
-            `INST_FPU_MISC: begin
-                if  (fdst_d) begin
-                    case (op_mod)
-                        0: `TRACE(level, ("FSGNJ.D"));
-                        1: `TRACE(level, ("FSGNJN.D"));
-                        2: `TRACE(level, ("FSGNJX.D"));
-                        3: `TRACE(level, ("FCLASS.D"));
-                        4: `TRACE(level, ("FMV.X.D"));
-                        5: `TRACE(level, ("FMV.D.X"));
-                        6: `TRACE(level, ("FMIN.D"));
-                        7: `TRACE(level, ("FMAX.D"));
-                    endcase
-                end else begin
-                    case (op_mod)
-                        0: `TRACE(level, ("FSGNJ.S"));
-                        1: `TRACE(level, ("FSGNJN.S"));
-                        2: `TRACE(level, ("FSGNJX.S"));
-                        3: `TRACE(level, ("FCLASS.S"));
-                        4: `TRACE(level, ("FMV.X.S"));
-                        5: `TRACE(level, ("FMV.S.X"));
-                        6: `TRACE(level, ("FMIN.S"));
-                        7: `TRACE(level, ("FMAX.S"));
-                    endcase
-                end
-            end
-            default: `TRACE(level, ("?"));
-        endcase
-    end
-    `EX_SFU: begin
-            case (`INST_SFU_BITS'(op_type))
-            `INST_SFU_TMC:   `TRACE(level, ("TMC"));
-            `INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN"));
-            `INST_SFU_SPLIT: `TRACE(level, ("SPLIT"));
-            `INST_SFU_JOIN:  `TRACE(level, ("JOIN"));
-            `INST_SFU_BAR:   `TRACE(level, ("BAR"));
-            `INST_SFU_PRED:  `TRACE(level, ("PRED"));
-            `INST_SFU_CSRRW: begin if (use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end
-            `INST_SFU_CSRRS: begin if (use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end
-            `INST_SFU_CSRRC: begin if (use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end
-            default:         `TRACE(level, ("?"));
-        endcase
-    end
-    default: `TRACE(level, ("?"));
-    endcase
-endtask
-
-task trace_base_dcr(input int level, input [`VX_DCR_ADDR_WIDTH-1:0] addr);
-    case (addr)
-        `VX_DCR_BASE_STARTUP_ADDR0: `TRACE(level, ("STARTUP_ADDR0"));
-        `VX_DCR_BASE_STARTUP_ADDR1: `TRACE(level, ("STARTUP_ADDR1"));
-        `VX_DCR_BASE_MPM_CLASS:     `TRACE(level, ("MPM_CLASS"));
-        default:                    `TRACE(level, ("?"));
-    endcase
-endtask
-
-`endif
-
-`endif // VX_TRACE_VH

hw/rtl/core/VX_wctl_unit.sv

@@ -1,156 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_define.vh"
-
-module VX_wctl_unit import VX_gpu_pkg::*; #(
-    parameter CORE_ID = 0,
-    parameter NUM_LANES = 1
-) (
-    input wire              clk,
-    input wire              reset,
-
-    // Inputs
-    VX_execute_if.slave     execute_if,
-    
-    // Outputs
-    VX_warp_ctl_if.master   warp_ctl_if,
-    VX_commit_if.master     commit_if
-);
-    `UNUSED_PARAM (CORE_ID)
-    localparam LANE_BITS  = `CLOG2(NUM_LANES);
-    localparam PID_BITS   = `CLOG2(`NUM_THREADS / NUM_LANES);
-    localparam PID_WIDTH  = `UP(PID_BITS);
-    localparam WCTL_WIDTH = $bits(tmc_t) + $bits(wspawn_t) + $bits(split_t) + $bits(join_t) + $bits(barrier_t);
-    localparam DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + WCTL_WIDTH + PID_WIDTH + 1 + 1;
-
-    `UNUSED_VAR (execute_if.data.rs3_data)
-    
-    tmc_t       tmc, tmc_r;
-    wspawn_t    wspawn, wspawn_r;    
-    split_t     split, split_r;
-    join_t      sjoin, sjoin_r;
-    barrier_t   barrier, barrier_r;
-
-    wire is_wspawn = (execute_if.data.op_type == `INST_SFU_WSPAWN);
-    wire is_tmc    = (execute_if.data.op_type == `INST_SFU_TMC);
-    wire is_pred   = (execute_if.data.op_type == `INST_SFU_PRED);
-    wire is_split  = (execute_if.data.op_type == `INST_SFU_SPLIT);
-    wire is_join   = (execute_if.data.op_type == `INST_SFU_JOIN);
-    wire is_bar    = (execute_if.data.op_type == `INST_SFU_BAR);
-
-    wire [`UP(LANE_BITS)-1:0] tid;
-    if (LANE_BITS != 0) begin
-        assign tid = execute_if.data.tid[0 +: LANE_BITS];
-    end else begin
-        assign tid = 0;
-    end
-    
-    wire [`XLEN-1:0] rs1_data = execute_if.data.rs1_data[tid];
-    wire [`XLEN-1:0] rs2_data = execute_if.data.rs2_data[tid];
-    `UNUSED_VAR (rs1_data)
-    
-    wire [NUM_LANES-1:0] taken;
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign taken[i] = execute_if.data.rs1_data[i][0];
-    end
-
-    reg [`NUM_THREADS-1:0] then_tmask_r, then_tmask_n;
-    reg [`NUM_THREADS-1:0] else_tmask_r, else_tmask_n;
-    always @(*) begin
-        then_tmask_n = then_tmask_r;
-        else_tmask_n = else_tmask_r;
-        if (execute_if.data.sop) begin
-            then_tmask_n = '0;
-            else_tmask_n = '0;
-        end
-        then_tmask_n[execute_if.data.pid * NUM_LANES +: NUM_LANES] = taken & execute_if.data.tmask;
-        else_tmask_n[execute_if.data.pid * NUM_LANES +: NUM_LANES] = ~taken & execute_if.data.tmask;
-    end
-    always @(posedge clk) begin
-        if (execute_if.valid) begin
-            then_tmask_r <= then_tmask_n;
-            else_tmask_r <= else_tmask_n;
-        end
-    end
-    wire has_then = (then_tmask_n != 0);
-    wire has_else = (else_tmask_n != 0);
-
-    // tmc / pred
-
-    wire [`NUM_THREADS-1:0] pred_mask = has_then ? then_tmask_n : rs2_data[`NUM_THREADS-1:0];
-    assign tmc.valid = (is_tmc || is_pred);
-    assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0];
-
-    // split
-    
-    assign split.valid      = is_split;
-    assign split.is_dvg     = has_then && has_else;
-    assign split.then_tmask = then_tmask_n;
-    assign split.else_tmask = else_tmask_n;
-    assign split.next_pc    = execute_if.data.PC + 4;
-
-    // join
-
-    assign sjoin.valid      = is_join;   
-    assign sjoin.is_dvg     = rs1_data[0];
-
-    // barrier
-    assign barrier.valid    = is_bar;
-    assign barrier.id       = rs1_data[`NB_WIDTH-1:0];
-`ifdef GBAR_ENABLE
-    assign barrier.is_global = rs1_data[31];
-`else
-    assign barrier.is_global = 1'b0;
-`endif
-    assign barrier.size_m1  = rs2_data[$bits(barrier.size_m1)-1:0] - $bits(barrier.size_m1)'(1);
-
-    // wspawn
-
-    wire [`NUM_WARPS-1:0] wspawn_wmask;
-    for (genvar i = 0; i < `NUM_WARPS; ++i) begin
-        assign wspawn_wmask[i] = (i < rs1_data[`NW_BITS:0]) && (i != execute_if.data.wid);
-    end
-    assign wspawn.valid = is_wspawn;
-    assign wspawn.wmask = wspawn_wmask;
-    assign wspawn.pc    = rs2_data;
-
-    // response
-    
-    VX_elastic_buffer #(
-        .DATAW (DATAW),
-        .SIZE  (2)
-    ) rsp_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (execute_if.valid),
-        .ready_in  (execute_if.ready),
-        .data_in   ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, {tmc, wspawn, split, sjoin, barrier}}),
-        .data_out  ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop, {tmc_r, wspawn_r, split_r, sjoin_r, barrier_r}}),
-        .valid_out (commit_if.valid),
-        .ready_out (commit_if.ready)
-    );
-
-    assign warp_ctl_if.valid   = commit_if.valid && commit_if.ready && commit_if.data.eop;
-    assign warp_ctl_if.wid     = commit_if.data.wid;
-    assign warp_ctl_if.tmc     = tmc_r;
-    assign warp_ctl_if.wspawn  = wspawn_r;
-    assign warp_ctl_if.split   = split_r;
-    assign warp_ctl_if.sjoin   = sjoin_r;
-    assign warp_ctl_if.barrier = barrier_r;
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign commit_if.data.data[i] = `XLEN'(split_r.is_dvg);
-    end
-
-endmodule

hw/rtl/fpu/VX_fpu_class.sv

@@ -1,45 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-module VX_fpu_class import VX_fpu_pkg::*; #(    
-    parameter MAN_BITS = 23,
-    parameter EXP_BITS = 8
-) (
-    input  [EXP_BITS-1:0] exp_i,
-    input  [MAN_BITS-1:0] man_i,
-    output fclass_t       clss_o
-);
-    wire is_normal    = (exp_i != '0) && (exp_i != '1);
-    wire is_zero      = (exp_i == '0) && (man_i == '0);
-    wire is_subnormal = (exp_i == '0) && (man_i != '0);
-    wire is_inf       = (exp_i == '1) && (man_i == '0); 
-    wire is_nan       = (exp_i == '1) && (man_i != '0);
-    wire is_signaling = is_nan && ~man_i[MAN_BITS-1];
-    wire is_quiet     = is_nan && ~is_signaling;
-
-    assign clss_o.is_normal    = is_normal;
-    assign clss_o.is_zero      = is_zero;
-    assign clss_o.is_subnormal = is_subnormal;
-    assign clss_o.is_inf       = is_inf;
-    assign clss_o.is_nan       = is_nan;
-    assign clss_o.is_quiet     = is_quiet;
-    assign clss_o.is_signaling = is_signaling;
-
-endmodule
-`endif
-

hw/rtl/fpu/VX_fpu_cvt.sv

@@ -1,394 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-/// Modified port of cast module from fpnew Libray 
-/// reference: https://github.com/pulp-platform/fpnew
-
-module VX_fpu_cvt import VX_fpu_pkg::*; #(
-    parameter NUM_LANES = 1,
-    parameter TAGW = 1
-) (
-    input wire clk,
-    input wire reset, 
-
-    output wire ready_in,
-    input wire  valid_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire is_itof,
-    input wire is_signed,
-
-    input wire [NUM_LANES-1:0][31:0]  dataa,
-    output wire [NUM_LANES-1:0][31:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);   
-    // Constants
- 
-    localparam MAN_BITS = 23;
-    localparam EXP_BITS = 8;
-    localparam EXP_BIAS = 2**(EXP_BITS-1)-1;
-    
-    // Use 32-bit integer
-    localparam INT_WIDTH = 32;
-
-    // The internal mantissa includes normal bit or an entire integer
-    localparam INT_MAN_WIDTH = `MAX(MAN_BITS + 1, INT_WIDTH);
-
-    // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection
-    localparam LZC_RESULT_WIDTH = `CLOG2(INT_MAN_WIDTH);
-
-    // The internal exponent must be able to represent the smallest denormal input value as signed
-    // or the number of bits in an integer
-    localparam INT_EXP_WIDTH = `MAX(`CLOG2(INT_WIDTH), `MAX(EXP_BITS, `CLOG2(EXP_BIAS + MAN_BITS))) + 1;
-
-    localparam FMT_SHIFT_COMPENSATION = INT_MAN_WIDTH - 1 - MAN_BITS;
-    localparam NUM_FP_STICKY  = 2 * INT_MAN_WIDTH - MAN_BITS - 1;   // removed mantissa, 1. and R
-    localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - INT_WIDTH;  // removed int and R
-    
-    // Input processing
-    
-    fclass_t [NUM_LANES-1:0] fclass;
-      
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        VX_fpu_class #( 
-            .EXP_BITS (EXP_BITS),
-            .MAN_BITS (MAN_BITS)
-        ) fp_class (
-            .exp_i  (dataa[i][INT_WIDTH-2:MAN_BITS]),
-            .man_i  (dataa[i][MAN_BITS-1:0]),
-            .clss_o (fclass[i])
-        );
-    end
-
-    wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant;
-    wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp;    
-    wire [NUM_LANES-1:0]                    input_sign;
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire i2f_sign = dataa[i][INT_WIDTH-1];
-        wire f2i_sign = dataa[i][INT_WIDTH-1] && is_signed;
-        wire [INT_MAN_WIDTH-1:0] f2i_mantissa = f2i_sign ? (-dataa[i]) : dataa[i];
-        wire [INT_MAN_WIDTH-1:0] i2f_mantissa = INT_MAN_WIDTH'({fclass[i].is_normal, dataa[i][MAN_BITS-1:0]});
-        assign input_exp[i]  = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} + INT_EXP_WIDTH'({1'b0, fclass[i].is_subnormal});
-        assign input_mant[i] = is_itof ? f2i_mantissa : i2f_mantissa;
-        assign input_sign[i] = is_itof ? f2i_sign : i2f_sign;
-    end
-
-    // Pipeline stage0
-    
-    wire                 valid_in_s0;
-    wire [NUM_LANES-1:0] lane_mask_s0;
-    wire [TAGW-1:0]      tag_in_s0;
-    wire                 is_itof_s0;
-    wire                 is_signed_s0;
-    wire [2:0]           rnd_mode_s0;
-    fclass_t [NUM_LANES-1:0] fclass_s0;
-    wire [NUM_LANES-1:0] input_sign_s0;
-    wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0;
-    wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0;
-
-    wire stall;
-
-    VX_pipe_register #(
-        .DATAW  (1 + NUM_LANES + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)),
-        .RESETW (1)
-    ) pipe_reg0 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (~stall),
-        .data_in  ({valid_in, lane_mask, tag_in, is_itof, is_signed, frm, fclass, input_sign, input_exp, input_mant}),
-        .data_out ({valid_in_s0, lane_mask_s0, tag_in_s0, is_itof_s0, is_signed_s0, rnd_mode_s0, fclass_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0})
-    );
-    
-    // Normalization
-
-    wire [NUM_LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt_s0; // renormalization shift amount
-    wire [NUM_LANES-1:0] mant_is_zero_s0;                       // for integer zeroes
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire mant_is_nonzero_s0;
-        VX_lzc #(
-            .N (INT_MAN_WIDTH)
-        ) lzc (
-            .data_in   (encoded_mant_s0[i]),
-            .data_out  (renorm_shamt_s0[i]),
-            .valid_out (mant_is_nonzero_s0)
-        );
-        assign mant_is_zero_s0[i] = ~mant_is_nonzero_s0;  
-    end
-
-    wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_n_s0;    // normalized input mantissa    
-    wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_n_s0;     // unbiased true exponent
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-       // Realign input mantissa, append zeroes if destination is wider
-        assign input_mant_n_s0[i] = encoded_mant_s0[i] << renorm_shamt_s0[i];
-
-        // Unbias exponent and compensate for shift
-        wire [INT_EXP_WIDTH-1:0] i2f_input_exp_s0 = fmt_exponent_s0[i] + INT_EXP_WIDTH'(FMT_SHIFT_COMPENSATION - EXP_BIAS) - INT_EXP_WIDTH'({1'b0, renorm_shamt_s0[i]});
-        wire [INT_EXP_WIDTH-1:0] f2i_input_exp_s0 = INT_EXP_WIDTH'(INT_MAN_WIDTH-1) - INT_EXP_WIDTH'({1'b0, renorm_shamt_s0[i]});
-        assign input_exp_n_s0[i] = is_itof_s0 ? f2i_input_exp_s0 : i2f_input_exp_s0;
-    end
-
-    // Pipeline stage1
-
-    wire                 valid_in_s1;
-    wire [NUM_LANES-1:0] lane_mask_s1;
-    wire [TAGW-1:0]      tag_in_s1;
-    wire                 is_itof_s1;
-    wire                 is_signed_s1;
-    wire [2:0]           rnd_mode_s1;
-    fclass_t [NUM_LANES-1:0] fclass_s1;
-    wire [NUM_LANES-1:0] input_sign_s1;
-    wire [NUM_LANES-1:0] mant_is_zero_s1;
-    wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1;
-    wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1;
-
-    VX_pipe_register #(
-        .DATAW  (1 + NUM_LANES + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)),
-        .RESETW (1)
-    ) pipe_reg1 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (~stall),
-        .data_in  ({valid_in_s0, lane_mask_s0, tag_in_s0, is_itof_s0, is_signed_s0, rnd_mode_s0, fclass_s0, input_sign_s0, mant_is_zero_s0, input_mant_n_s0, input_exp_n_s0}),
-        .data_out ({valid_in_s1, lane_mask_s1, tag_in_s1, is_itof_s1, is_signed_s1, rnd_mode_s1, fclass_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1})
-    );
-
-    // Perform adjustments to mantissa and exponent
-
-    wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s1;
-    wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1;
-    wire [NUM_LANES-1:0] of_before_round_s1;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [INT_EXP_WIDTH-1:0] denorm_shamt = INT_EXP_WIDTH'(INT_WIDTH-1) - input_exp_s1[i];
-        wire overflow = ($signed(denorm_shamt) <= -$signed(INT_EXP_WIDTH'(!is_signed_s1)));
-        wire underflow = ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(-1)));
-        reg [INT_EXP_WIDTH-1:0] denorm_shamt_q;
-        always @(*) begin
-            if (overflow) begin
-                denorm_shamt_q = '0;
-            end else if (underflow) begin
-                denorm_shamt_q = INT_WIDTH+1;
-            end else begin
-                denorm_shamt_q = denorm_shamt;
-            end
-        end
-        assign destination_mant_s1[i] = is_itof_s1 ? {input_mant_s1[i], 33'b0} : ({input_mant_s1[i], 33'b0} >> denorm_shamt_q);
-        assign final_exp_s1[i]        = input_exp_s1[i] + INT_EXP_WIDTH'(EXP_BIAS);
-        assign of_before_round_s1[i]  = overflow;
-    end
-
-    // Pipeline stage2
-    
-    wire                 valid_in_s2;
-    wire [NUM_LANES-1:0] lane_mask_s2;
-    wire [TAGW-1:0]      tag_in_s2;
-    wire                 is_itof_s2;
-    wire                 is_signed_s2;
-    wire [2:0]           rnd_mode_s2;
-    fclass_t [NUM_LANES-1:0] fclass_s2;   
-    wire [NUM_LANES-1:0] mant_is_zero_s2;
-    wire [NUM_LANES-1:0] input_sign_s2;
-    wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s2;
-    wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s2;
-    wire [NUM_LANES-1:0] of_before_round_s2;
-    
-    VX_pipe_register #(
-        .DATAW  (1 + NUM_LANES + TAGW + 1 + 1 + `INST_FRM_BITS + NUM_LANES * ($bits(fclass_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)),
-        .RESETW (1)
-    ) pipe_reg2 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (~stall),
-        .data_in  ({valid_in_s1, lane_mask_s1, tag_in_s1, is_itof_s1, is_signed_s1, rnd_mode_s1, fclass_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}),
-        .data_out ({valid_in_s2, lane_mask_s2, tag_in_s2, is_itof_s2, is_signed_s2, rnd_mode_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2})
-    );
-
-    wire [NUM_LANES-1:0] rounded_sign_s2;
-    wire [NUM_LANES-1:0][INT_WIDTH-1:0] rounded_abs_s2; // absolute value of result after rounding
-    wire [NUM_LANES-1:0] f2i_round_has_sticky_s2;
-    wire [NUM_LANES-1:0] i2f_round_has_sticky_s2;
-    
-    // Rouding and classification
-   
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [MAN_BITS-1:0]  final_mant_s2;  // mantissa after adjustments
-        wire [INT_WIDTH-1:0] final_int_s2;   // integer shifted in position
-        wire [1:0]           round_sticky_bits_s2;
-        wire [INT_WIDTH-1:0] fmt_pre_round_abs_s2;
-        wire [INT_WIDTH-1:0] pre_round_abs_s2;
-        wire [1:0]           f2i_round_sticky_bits_s2, i2f_round_sticky_bits_s2;
-
-        // Extract final mantissa and round bit, discard the normal bit (for FP)
-        assign {final_mant_s2, i2f_round_sticky_bits_s2[1]} = destination_mant_s2[i][2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1];
-        assign {final_int_s2, f2i_round_sticky_bits_s2[1]} = destination_mant_s2[i][2*INT_MAN_WIDTH   : 2*INT_MAN_WIDTH   - (INT_WIDTH+1) + 1];
-
-        // Collapse sticky bits
-        assign i2f_round_sticky_bits_s2[0] = (| destination_mant_s2[i][NUM_FP_STICKY-1:0]);
-        assign f2i_round_sticky_bits_s2[0] = (| destination_mant_s2[i][NUM_INT_STICKY-1:0]);
-        assign i2f_round_has_sticky_s2[i]  = (| i2f_round_sticky_bits_s2);
-        assign f2i_round_has_sticky_s2[i]  = (| f2i_round_sticky_bits_s2);
-
-        // select RS bits for destination operation
-        assign round_sticky_bits_s2 = is_itof_s2 ? i2f_round_sticky_bits_s2 : f2i_round_sticky_bits_s2;
-
-        // Pack exponent and mantissa into proper rounding form
-        assign fmt_pre_round_abs_s2 = {1'b0, final_exp_s2[i][EXP_BITS-1:0], final_mant_s2[MAN_BITS-1:0]};
-
-        // Select output with destination format and operation
-        assign pre_round_abs_s2 = is_itof_s2 ? fmt_pre_round_abs_s2 : final_int_s2;
-
-        // Perform the rounding
-        VX_fpu_rounding #(
-            .DAT_WIDTH (32)
-        ) fp_rounding (
-            .abs_value_i (pre_round_abs_s2),
-            .sign_i      (input_sign_s2[i]),
-            .round_sticky_bits_i (round_sticky_bits_s2),
-            .rnd_mode_i  (rnd_mode_s2),
-            .effective_subtraction_i (1'b0),
-            .abs_rounded_o (rounded_abs_s2[i]),
-            .sign_o      (rounded_sign_s2[i]),
-            `UNUSED_PIN  (exact_zero_o)
-        );
-    end
-
-    // Pipeline stage3
-
-    wire                 valid_in_s3;
-    wire [NUM_LANES-1:0] lane_mask_s3;
-    wire [TAGW-1:0]      tag_in_s3;
-    wire                 is_itof_s3;
-    wire                 is_signed_s3;
-    fclass_t [NUM_LANES-1:0] fclass_s3;   
-    wire [NUM_LANES-1:0] mant_is_zero_s3;
-    wire [NUM_LANES-1:0] input_sign_s3;
-    wire [NUM_LANES-1:0] rounded_sign_s3;
-    wire [NUM_LANES-1:0][INT_WIDTH-1:0] rounded_abs_s3;
-    wire [NUM_LANES-1:0] of_before_round_s3;   
-    wire [NUM_LANES-1:0] f2i_round_has_sticky_s3;
-    wire [NUM_LANES-1:0] i2f_round_has_sticky_s3; 
-
-    VX_pipe_register #(
-        .DATAW  (1 + NUM_LANES + TAGW + 1 + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + 32 + 1 + 1 + 1 + 1)),
-        .RESETW (1)
-    ) pipe_reg3 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (~stall),
-        .data_in  ({valid_in_s2, lane_mask_s2, tag_in_s2, is_itof_s2, is_signed_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2, of_before_round_s2, f2i_round_has_sticky_s2, i2f_round_has_sticky_s2}),
-        .data_out ({valid_in_s3, lane_mask_s3, tag_in_s3, is_itof_s3, is_signed_s3, fclass_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3, f2i_round_has_sticky_s3, i2f_round_has_sticky_s3})
-    );
-     
-    wire [NUM_LANES-1:0][INT_WIDTH-1:0] fmt_result_s3;
-    wire [NUM_LANES-1:0][INT_WIDTH-1:0] rounded_int_res_s3; // after possible inversion
-    wire [NUM_LANES-1:0] rounded_int_res_zero_s3;  // after rounding
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        // Assemble regular result, nan box short ones. Int zeroes need to be detected
-        assign fmt_result_s3[i] = mant_is_zero_s3[i] ? 0 : {rounded_sign_s3[i], rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:0]};
-
-        // Negative integer result needs to be brought into two's complement
-        assign rounded_int_res_s3[i] = rounded_sign_s3[i] ? (-rounded_abs_s3[i]) : rounded_abs_s3[i];
-        assign rounded_int_res_zero_s3[i] = (rounded_int_res_s3[i] == 0);
-    end
-
-    // F2I Special case handling
-
-    reg [NUM_LANES-1:0][INT_WIDTH-1:0] f2i_special_result_s3;
-    fflags_t [NUM_LANES-1:0] f2i_special_status_s3;
-    wire [NUM_LANES-1:0] f2i_result_is_special_s3;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-         // Assemble result according to destination format
-        always @(*) begin
-            if (input_sign_s3[i] && !fclass_s3[i].is_nan) begin
-                f2i_special_result_s3[i][INT_WIDTH-2:0] = '0;            // alone yields 2**(31)-1
-                f2i_special_result_s3[i][INT_WIDTH-1]   = is_signed_s3;  // for unsigned casts yields 2**31
-            end else begin
-                f2i_special_result_s3[i][INT_WIDTH-2:0] = 2**(INT_WIDTH-1) - 1;   // alone yields 2**(31)-1
-                f2i_special_result_s3[i][INT_WIDTH-1]   = ~is_signed_s3;   // for unsigned casts yields 2**31
-            end
-        end            
-
-        // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned)
-        assign f2i_result_is_special_s3[i] = fclass_s3[i].is_nan 
-                                           | fclass_s3[i].is_inf
-                                           | of_before_round_s3[i]
-                                           | (input_sign_s3[i] & ~is_signed_s3 & ~rounded_int_res_zero_s3[i]);
-                                        
-        // All integer special cases are invalid
-        assign f2i_special_status_s3[i] = {1'b1, 4'h0};
-    end
-
-    // Result selection and Output handshake
-
-    fflags_t [NUM_LANES-1:0] tmp_fflags_s3;    
-    wire [NUM_LANES-1:0][INT_WIDTH-1:0] tmp_result_s3;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin                                  
-        fflags_t i2f_regular_status_s3, f2i_regular_status_s3;
-        fflags_t i2f_status_s3, f2i_status_s3;
-
-        assign i2f_regular_status_s3 = {4'h0, i2f_round_has_sticky_s3[i]};
-        assign f2i_regular_status_s3 = {4'h0, f2i_round_has_sticky_s3[i]};
-
-        assign i2f_status_s3 = i2f_regular_status_s3;
-        assign f2i_status_s3 = f2i_result_is_special_s3[i] ? f2i_special_status_s3[i] : f2i_regular_status_s3;
-
-        wire [INT_WIDTH-1:0] i2f_result_s3 = fmt_result_s3[i];
-        wire [INT_WIDTH-1:0] f2i_result_s3 = f2i_result_is_special_s3[i] ? f2i_special_result_s3[i] : rounded_int_res_s3[i];
-
-        assign tmp_result_s3[i] = is_itof_s3 ? i2f_result_s3 : f2i_result_s3;
-        assign tmp_fflags_s3[i] = is_itof_s3 ? i2f_status_s3 : f2i_status_s3;
-    end
-
-    assign stall = ~ready_out && valid_out;
-
-    fflags_t fflags_merged;
-    `FPU_MERGE_FFLAGS(fflags_merged, tmp_fflags_s3, lane_mask_s3, NUM_LANES);
-
-    VX_pipe_register #(
-        .DATAW  (1 + TAGW + (NUM_LANES * 32) + `FP_FLAGS_BITS),
-        .RESETW (1)
-    ) pipe_reg4 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (!stall),
-        .data_in  ({valid_in_s3, tag_in_s3, tmp_result_s3, fflags_merged}),
-        .data_out ({valid_out, tag_out, result, fflags})
-    );
-
-    assign ready_in = ~stall;
-    assign has_fflags = 1'b1;
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_define.vh

@@ -1,42 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_FPU_DEFINE_VH
-`define VX_FPU_DEFINE_VH
-
-`include "VX_define.vh"
-
-`ifdef SV_DPI
-`include "float_dpi.vh"
-`endif
-
-`define FPU_MERGE_FFLAGS(out, in, mask, lanes) \
-    fflags_t __``out; \
-    always @(*) begin \
-        __``out = '0; \
-        for (integer __i = 0; __i < lanes; ++__i) begin \
-            if (mask[__i]) begin \
-                __``out.NX |= in[__i].NX; \
-                __``out.UF |= in[__i].UF; \
-                __``out.OF |= in[__i].OF; \
-                __``out.DZ |= in[__i].DZ; \
-                __``out.NV |= in[__i].NV; \
-            end \
-        end \
-    end \
-    assign out = __``out
-    
-`define FP_CLASS_BITS   $bits(VX_fpu_pkg::fclass_t)
-`define FP_FLAGS_BITS   $bits(VX_fpu_pkg::fflags_t)
-
-`endif // VX_FPU_DEFINE_VH

hw/rtl/fpu/VX_fpu_div.sv

@@ -1,137 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-module VX_fpu_div import VX_fpu_pkg::*; #(
-    parameter NUM_LANES = 1,
-    parameter TAGW = 1
-) (
-    input wire clk,
-    input wire reset, 
-
-    output wire ready_in,
-    input wire  valid_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-
-    input wire [`INST_FRM_BITS-1:0] frm,
-    
-    input wire [NUM_LANES-1:0][31:0]  dataa,
-    input wire [NUM_LANES-1:0][31:0]  datab,
-    output wire [NUM_LANES-1:0][31:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);
-    `UNUSED_VAR (frm)
-
-    wire stall  = ~ready_out && valid_out;
-    wire enable = ~stall;
-
-    fflags_t [NUM_LANES-1:0] per_lane_fflags;
-    wire [NUM_LANES-1:0] lane_mask_out;
-
-    VX_shift_register #(
-        .DATAW  (1 + NUM_LANES + TAGW),
-        .DEPTH  (`LATENCY_FDIV),
-        .RESETW (1)
-    ) shift_reg (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (enable),
-        .data_in  ({valid_in, lane_mask, tag_in}),
-        .data_out ({valid_out, lane_mask_out, tag_out})
-    );
-
-    assign ready_in = enable;
-
-`ifdef QUARTUS
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        acl_fdiv fdiv (
-            .clk    (clk),
-            .areset (1'b0),
-            .en     (enable),
-            .a      (dataa[i]),
-            .b      (datab[i]),
-            .q      (result[i])
-        );
-    end    
-    
-    assign has_fflags = 0;
-    assign per_lane_fflags = 'x;
-
-`elsif VIVADO
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [3:0] tuser;
-
-        xil_fdiv fdiv (
-            .aclk                (clk),
-            .aclken              (enable),
-            .s_axis_a_tvalid     (1'b1),
-            .s_axis_a_tdata      (dataa[i]),
-            .s_axis_b_tvalid     (1'b1),
-            .s_axis_b_tdata      (datab[i]),
-            `UNUSED_PIN (m_axis_result_tvalid),
-            .m_axis_result_tdata (result[i]),
-            .m_axis_result_tuser (tuser)
-        );
-                                    // NV, DZ, OF, UF, NX
-        assign per_lane_fflags[i] = {tuser[2], tuser[3], tuser[1], tuser[0], 1'b0};
-    end
-
-     assign has_fflags = 1;
-
-`else    
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin       
-        reg [63:0] r;
-        `UNUSED_VAR (r)
-        
-        fflags_t f;
-
-        always @(*) begin        
-            dpi_fdiv (enable && valid_in, int'(0), {32'hffffffff, dataa[i]}, {32'hffffffff,  datab[i]}, frm, r, f);
-        end
-
-        VX_shift_register #(
-            .DATAW  (32 + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FDIV)
-        ) shift_req_dpi (
-            .clk      (clk),
-            `UNUSED_PIN (reset),
-            .enable   (enable),
-            .data_in  ({r[31:0], f}),
-            .data_out ({result[i], per_lane_fflags[i]})
-        );
-    end
-
-    assign has_fflags = 1;
-
-`endif
-
-`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES);
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_dpi.sv

@@ -1,490 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DPI
-
-module VX_fpu_dpi import VX_fpu_pkg::*; #( 
-    parameter NUM_LANES = 1,
-    parameter TAGW      = 1,
-    parameter OUT_REG   = 0
-) (
-    input wire clk,
-    input wire reset,
-
-    input wire  valid_in,
-    output wire ready_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-    
-    input wire [`INST_FPU_BITS-1:0] op_type,
-    input wire [`INST_FMT_BITS-1:0] fmt,
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  dataa,
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  datab,
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  datac,
-    output wire [NUM_LANES-1:0][`XLEN-1:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);
-    localparam FPU_FMA     = 0;
-    localparam FPU_DIVSQRT = 1;
-    localparam FPU_CVT     = 2;
-    localparam FPU_NCP     = 3;
-    localparam NUM_FPC     = 4;
-    localparam FPC_BITS    = `LOG2UP(NUM_FPC);
-
-    localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAGW;
-    
-    wire [NUM_FPC-1:0] per_core_ready_in;
-    wire [NUM_FPC-1:0][NUM_LANES-1:0][`XLEN-1:0] per_core_result;
-    wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out;
-    reg  [NUM_FPC-1:0] per_core_ready_out;
-    wire [NUM_FPC-1:0] per_core_valid_out;    
-    wire [NUM_FPC-1:0] per_core_has_fflags;  
-    fflags_t [NUM_FPC-1:0] per_core_fflags;  
-
-    wire div_ready_in, sqrt_ready_in;
-    wire [NUM_LANES-1:0][`XLEN-1:0] div_result, sqrt_result;
-    wire [TAGW-1:0] div_tag_out, sqrt_tag_out;
-    wire div_ready_out, sqrt_ready_out;
-    wire div_valid_out, sqrt_valid_out;    
-    wire div_has_fflags, sqrt_has_fflags;  
-    fflags_t div_fflags, sqrt_fflags;
-
-    reg [FPC_BITS-1:0] core_select;
-
-    reg is_fadd, is_fsub, is_fmul, is_fmadd, is_fmsub, is_fnmadd, is_fnmsub;
-    reg is_div, is_fcmp, is_itof, is_utof, is_ftoi, is_ftou, is_f2f;    
-    reg dst_fmt, int_fmt;
-
-    reg [NUM_LANES-1:0][63:0] operands [3];
-    
-    always @(*) begin
-        for (integer i = 0; i < NUM_LANES; ++i) begin
-            operands[0][i] = 64'(dataa[i]);
-            operands[1][i] = 64'(datab[i]);
-            operands[2][i] = 64'(datac[i]);
-        end
-    end
-
-    `UNUSED_VAR (fmt)
-
-    always @(*) begin
-        is_fadd   = 0;
-        is_fsub   = 0;        
-        is_fmul   = 0;        
-        is_fmadd  = 0;
-        is_fmsub  = 0;
-        is_fnmadd = 0;           
-        is_fnmsub = 0; 
-        is_div    = 0;      
-        is_fcmp   = 0;
-        is_itof   = 0;
-        is_utof   = 0;
-        is_ftoi   = 0;
-        is_ftou   = 0;
-        is_f2f    = 0;
-        
-        dst_fmt   = 0;
-        int_fmt   = 0;
-        
-    `ifdef FLEN_64
-        dst_fmt = fmt[0];
-    `endif
-
-    `ifdef XLEN_64
-        int_fmt = fmt[1];
-    `endif
-
-        case (op_type)
-            `INST_FPU_ADD:   begin core_select = FPU_FMA; is_fadd = 1; end
-            `INST_FPU_SUB:   begin core_select = FPU_FMA; is_fsub = 1; end
-            `INST_FPU_MUL:   begin core_select = FPU_FMA; is_fmul = 1; end
-            `INST_FPU_MADD:  begin core_select = FPU_FMA; is_fmadd = 1; end
-            `INST_FPU_MSUB:  begin core_select = FPU_FMA; is_fmsub = 1; end
-            `INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end
-            `INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end
-            `INST_FPU_DIV:   begin core_select = FPU_DIVSQRT; is_div = 1; end
-            `INST_FPU_SQRT:  begin core_select = FPU_DIVSQRT; end
-            `INST_FPU_CMP:   begin core_select = FPU_NCP; is_fcmp = 1; end
-            `INST_FPU_F2I:   begin core_select = FPU_CVT; is_ftoi = 1; end
-            `INST_FPU_F2U:   begin core_select = FPU_CVT; is_ftou = 1; end
-            `INST_FPU_I2F:   begin core_select = FPU_CVT; is_itof = 1; end
-            `INST_FPU_U2F:   begin core_select = FPU_CVT; is_utof = 1; end
-            `INST_FPU_F2F:   begin core_select = FPU_CVT; is_f2f  = 1; end            
-            default:         begin core_select = FPU_NCP; end
-        endcase
-    end
-
-    generate 
-    begin : fma
-        
-        reg [NUM_LANES-1:0][`XLEN-1:0] result_fma;
-        wire [NUM_LANES-1:0][63:0] result_fadd;
-        wire [NUM_LANES-1:0][63:0] result_fsub;
-        wire [NUM_LANES-1:0][63:0] result_fmul;
-        wire [NUM_LANES-1:0][63:0] result_fmadd;
-        wire [NUM_LANES-1:0][63:0] result_fmsub;
-        wire [NUM_LANES-1:0][63:0] result_fnmadd;
-        wire [NUM_LANES-1:0][63:0] result_fnmsub;
-        
-        fflags_t [NUM_LANES-1:0] fflags_fma;
-        fflags_t [NUM_LANES-1:0] fflags_fadd;
-        fflags_t [NUM_LANES-1:0] fflags_fsub;
-        fflags_t [NUM_LANES-1:0] fflags_fmul;
-        fflags_t [NUM_LANES-1:0] fflags_fmadd;
-        fflags_t [NUM_LANES-1:0] fflags_fmsub;
-        fflags_t [NUM_LANES-1:0] fflags_fnmadd;
-        fflags_t [NUM_LANES-1:0] fflags_fnmsub;
-
-        wire fma_valid = (valid_in && core_select == FPU_FMA);
-        wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA];
-        wire fma_fire  = fma_valid && fma_ready;
-
-        always @(*) begin        
-            for (integer i = 0; i < NUM_LANES; ++i) begin
-                dpi_fadd   (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fadd[i], fflags_fadd[i]);
-                dpi_fsub   (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fsub[i], fflags_fsub[i]);
-                dpi_fmul   (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fmul[i], fflags_fmul[i]);
-                dpi_fmadd  (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmadd[i], fflags_fmadd[i]);
-                dpi_fmsub  (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmsub[i], fflags_fmsub[i]);
-                dpi_fnmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmadd[i], fflags_fnmadd[i]);
-                dpi_fnmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmsub[i], fflags_fnmsub[i]);
-
-                result_fma[i] = is_fadd   ? result_fadd[i][`XLEN-1:0] :
-                                is_fsub   ? result_fsub[i][`XLEN-1:0] :
-                                is_fmul   ? result_fmul[i][`XLEN-1:0] :
-                                is_fmadd  ? result_fmadd[i][`XLEN-1:0] :               
-                                is_fmsub  ? result_fmsub[i][`XLEN-1:0] :
-                                is_fnmadd ? result_fnmadd[i][`XLEN-1:0] :               
-                                is_fnmsub ? result_fnmsub[i][`XLEN-1:0] :
-                                            '0;
-
-                fflags_fma[i] = is_fadd   ? fflags_fadd[i] :
-                                is_fsub   ? fflags_fsub[i] :
-                                is_fmul   ? fflags_fmul[i] :
-                                is_fmadd  ? fflags_fmadd[i] :               
-                                is_fmsub  ? fflags_fmsub[i] :
-                                is_fnmadd ? fflags_fnmadd[i] :               
-                                is_fnmsub ? fflags_fnmsub[i] : 
-                                            '0;                
-            end
-        end
-
-        fflags_t fflags_merged;
-        `FPU_MERGE_FFLAGS(fflags_merged, fflags_fma, lane_mask, NUM_LANES);
-
-        VX_shift_register #(
-            .DATAW  (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FMA),
-            .RESETW (1)
-        ) shift_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (fma_ready),
-            .data_in  ({fma_valid, tag_in, result_fma, fflags_merged}),
-            .data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]})
-        );
-
-        assign per_core_has_fflags[FPU_FMA] = 1;
-        assign per_core_ready_in[FPU_FMA] = fma_ready;
-
-    end
-    endgenerate
-
-    generate 
-    begin : fdiv
-
-        reg [NUM_LANES-1:0][`XLEN-1:0] result_fdiv_r;
-        wire [NUM_LANES-1:0][63:0] result_fdiv;
-        fflags_t [NUM_LANES-1:0] fflags_fdiv;
-
-        wire fdiv_valid = (valid_in && core_select == FPU_DIVSQRT) && is_div;
-        wire fdiv_ready = div_ready_out || ~div_valid_out;
-        wire fdiv_fire  = fdiv_valid && fdiv_ready;
-        
-        always @(*) begin        
-            for (integer i = 0; i < NUM_LANES; ++i) begin                
-                dpi_fdiv (fdiv_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fdiv[i], fflags_fdiv[i]);
-                result_fdiv_r[i] = result_fdiv[i][`XLEN-1:0];
-            end
-        end
-
-        fflags_t fflags_merged;
-        `FPU_MERGE_FFLAGS(fflags_merged, fflags_fdiv, lane_mask, NUM_LANES);
-
-        VX_shift_register #(
-            .DATAW  (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FDIV),
-            .RESETW (1)
-        ) shift_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (fdiv_ready),
-            .data_in  ({fdiv_valid, tag_in, result_fdiv_r, fflags_merged}),
-            .data_out ({div_valid_out, div_tag_out, div_result, div_fflags})
-        );
-
-        assign div_has_fflags = 1;
-        assign div_ready_in = fdiv_ready;
-
-    end
-    endgenerate
-
-    generate 
-    begin : fsqrt
-
-        reg [NUM_LANES-1:0][`XLEN-1:0] result_fsqrt_r;
-        wire [NUM_LANES-1:0][63:0] result_fsqrt;
-        fflags_t [NUM_LANES-1:0] fflags_fsqrt;
-
-        wire fsqrt_valid = (valid_in && core_select == FPU_DIVSQRT) && ~is_div;
-        wire fsqrt_ready = sqrt_ready_out || ~sqrt_valid_out;                
-        wire fsqrt_fire  = fsqrt_valid && fsqrt_ready;
-        
-        always @(*) begin        
-            for (integer i = 0; i < NUM_LANES; ++i) begin
-                dpi_fsqrt (fsqrt_fire, int'(dst_fmt), operands[0][i], frm, result_fsqrt[i], fflags_fsqrt[i]);
-                result_fsqrt_r[i] = result_fsqrt[i][`XLEN-1:0];
-            end
-        end
-
-        fflags_t fflags_merged;
-        `FPU_MERGE_FFLAGS(fflags_merged, fflags_fsqrt, lane_mask, NUM_LANES);
-
-        VX_shift_register #(
-            .DATAW  (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FSQRT),
-            .RESETW (1)
-        ) shift_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (fsqrt_ready),
-            .data_in  ({fsqrt_valid, tag_in, result_fsqrt_r, fflags_merged}),
-            .data_out ({sqrt_valid_out, sqrt_tag_out, sqrt_result, sqrt_fflags})
-        );
-
-        assign sqrt_has_fflags = 1;
-        assign sqrt_ready_in = fsqrt_ready;
-
-    end
-    endgenerate
-
-    generate
-    begin : fcvt
-
-        reg [NUM_LANES-1:0][`XLEN-1:0] result_fcvt;
-        wire [NUM_LANES-1:0][63:0] result_itof;
-        wire [NUM_LANES-1:0][63:0] result_utof;
-        wire [NUM_LANES-1:0][63:0] result_ftoi;
-        wire [NUM_LANES-1:0][63:0] result_ftou;
-        wire [NUM_LANES-1:0][63:0] result_f2f;
-        
-        fflags_t [NUM_LANES-1:0] fflags_fcvt;
-        fflags_t [NUM_LANES-1:0] fflags_itof;
-        fflags_t [NUM_LANES-1:0] fflags_utof;
-        fflags_t [NUM_LANES-1:0] fflags_ftoi;
-        fflags_t [NUM_LANES-1:0] fflags_ftou;
-
-        wire fcvt_valid = (valid_in && core_select == FPU_CVT);
-        wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT];
-        wire fcvt_fire  = fcvt_valid && fcvt_ready;
-                
-        always @(*) begin        
-            for (integer i = 0; i < NUM_LANES; ++i) begin
-                dpi_itof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_itof[i], fflags_itof[i]);
-                dpi_utof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_utof[i], fflags_utof[i]);
-                dpi_ftoi (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftoi[i], fflags_ftoi[i]);
-                dpi_ftou (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftou[i], fflags_ftou[i]);
-                dpi_f2f  (fcvt_fire, int'(dst_fmt), operands[0][i], result_f2f[i]);                
-
-                result_fcvt[i] = is_itof ? result_itof[i][`XLEN-1:0] :
-                                is_utof ? result_utof[i][`XLEN-1:0] :
-                                is_ftoi ? result_ftoi[i][`XLEN-1:0] :
-                                is_ftou ? result_ftou[i][`XLEN-1:0] : 
-                                is_f2f  ? result_f2f[i][`XLEN-1:0] : 
-                                        '0;
-
-                fflags_fcvt[i] = is_itof ? fflags_itof[i] :
-                                is_utof ? fflags_utof[i] :
-                                is_ftoi ? fflags_ftoi[i] :
-                                is_ftou ? fflags_ftou[i] :
-                                       '0;
-            end
-        end
-
-        fflags_t fflags_merged;
-        `FPU_MERGE_FFLAGS(fflags_merged, fflags_fcvt, lane_mask, NUM_LANES);
-
-        VX_shift_register #(
-            .DATAW  (1 + TAGW + NUM_LANES * `XLEN + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FCVT),
-            .RESETW (1)
-        ) shift_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (fcvt_ready),
-            .data_in  ({fcvt_valid, tag_in, result_fcvt, fflags_merged}),
-            .data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]})
-        );
-
-        assign per_core_has_fflags[FPU_CVT] = 1;
-        assign per_core_ready_in[FPU_CVT] = fcvt_ready;
-
-    end
-    endgenerate
-
-    generate 
-    begin : fncp
-
-        reg [NUM_LANES-1:0][`XLEN-1:0]  result_fncp;
-        wire [NUM_LANES-1:0][63:0] result_fclss;
-        wire [NUM_LANES-1:0][63:0] result_flt;
-        wire [NUM_LANES-1:0][63:0] result_fle;
-        wire [NUM_LANES-1:0][63:0] result_feq;
-        wire [NUM_LANES-1:0][63:0] result_fmin;
-        wire [NUM_LANES-1:0][63:0] result_fmax;
-        wire [NUM_LANES-1:0][63:0] result_fsgnj;
-        wire [NUM_LANES-1:0][63:0] result_fsgnjn;
-        wire [NUM_LANES-1:0][63:0] result_fsgnjx;
-        reg [NUM_LANES-1:0][63:0] result_fmvx;
-        reg [NUM_LANES-1:0][63:0] result_fmvf;
-
-        fflags_t [NUM_LANES-1:0] fflags_fncp;
-        fflags_t [NUM_LANES-1:0] fflags_flt;
-        fflags_t [NUM_LANES-1:0] fflags_fle;
-        fflags_t [NUM_LANES-1:0] fflags_feq;
-        fflags_t [NUM_LANES-1:0] fflags_fmin;
-        fflags_t [NUM_LANES-1:0] fflags_fmax;
-
-        wire fncp_valid = (valid_in && core_select == FPU_NCP);
-        wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP];
-        wire fncp_fire  = fncp_valid && fncp_ready;
-                
-        always @(*) begin        
-            for (integer i = 0; i < NUM_LANES; ++i) begin
-                dpi_fclss  (fncp_fire, int'(dst_fmt), operands[0][i], result_fclss[i]);
-                dpi_fle    (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fle[i], fflags_fle[i]);
-                dpi_flt    (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_flt[i], fflags_flt[i]);                
-                dpi_feq    (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_feq[i], fflags_feq[i]);
-                dpi_fmin   (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmin[i], fflags_fmin[i]);
-                dpi_fmax   (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmax[i], fflags_fmax[i]);            
-                dpi_fsgnj  (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnj[i]);
-                dpi_fsgnjn (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjn[i]);
-                dpi_fsgnjx (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjx[i]);
-                result_fmvx[i] = dst_fmt ? operands[0][i] : 64'($signed(operands[0][i][31:0]));      // sign-extension
-                result_fmvf[i] = dst_fmt ? operands[0][i] : (operands[0][i] | 64'hffffffff00000000); // nan-boxing
-            end
-        end
-
-        always @(*) begin
-            result_fncp = 'x;
-            fflags_fncp = 'x;
-            for (integer i = 0; i < NUM_LANES; ++i) begin
-                case (frm)
-                0:  begin result_fncp[i] = is_fcmp ? result_fle[i][`XLEN-1:0] : result_fsgnj[i][`XLEN-1:0];  fflags_fncp[i] = fflags_fle[i]; end
-                1:  begin result_fncp[i] = is_fcmp ? result_flt[i][`XLEN-1:0] : result_fsgnjn[i][`XLEN-1:0]; fflags_fncp[i] = fflags_flt[i]; end
-                2:  begin result_fncp[i] = is_fcmp ? result_feq[i][`XLEN-1:0] : result_fsgnjx[i][`XLEN-1:0]; fflags_fncp[i] = fflags_feq[i]; end
-                3:  begin result_fncp[i] = result_fclss[i][`XLEN-1:0]; end
-                4:  begin result_fncp[i] = result_fmvx[i][`XLEN-1:0]; end
-                5:  begin result_fncp[i] = result_fmvf[i][`XLEN-1:0]; end
-                6:  begin result_fncp[i] = result_fmin[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmin[i]; end
-                7:  begin result_fncp[i] = result_fmax[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmax[i]; end
-                endcase
-            end
-        end
-
-        fflags_t fflags_merged;
-        `FPU_MERGE_FFLAGS(fflags_merged, fflags_fncp, lane_mask, NUM_LANES);
-
-        wire has_fflags_fncp = (frm >= 6) || is_fcmp;
-
-        VX_shift_register #(
-            .DATAW  (1 + TAGW + 1 + NUM_LANES * `XLEN + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FNCP),
-            .RESETW (1)
-        ) shift_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (fncp_ready),
-            .data_in  ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_merged}),
-            .data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]})
-        );
-        
-        assign per_core_ready_in[FPU_NCP] = fncp_ready;
-
-    end
-    endgenerate
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in;
-
-    VX_stream_arb #(
-        .NUM_INPUTS (2),
-        .DATAW      (RSP_DATAW), 
-        .ARBITER    ("R"),
-        .OUT_REG    (0)
-    ) div_sqrt_arb (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  ({sqrt_valid_out, div_valid_out}), 
-        .ready_in  ({sqrt_ready_out, div_ready_out}),
-        .data_in   ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out}, 
-                     {div_result, div_has_fflags, div_fflags, div_tag_out}}),
-        .data_out  ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}),
-        .valid_out (per_core_valid_out[FPU_DIVSQRT]),
-        .ready_out (per_core_ready_out[FPU_DIVSQRT]),
-        `UNUSED_PIN (sel_out)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    wire [NUM_FPC-1:0][RSP_DATAW-1:0] per_core_data_out;
-
-    for (genvar i = 0; i < NUM_FPC; ++i) begin
-        assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
-    end
-
-    VX_stream_arb #(
-        .NUM_INPUTS (NUM_FPC),
-        .DATAW      (RSP_DATAW), 
-        .ARBITER    ("R"),
-        .OUT_REG    (OUT_REG)
-    ) rsp_arb (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (per_core_valid_out), 
-        .ready_in  (per_core_ready_out),
-        .data_in   (per_core_data_out),
-        .data_out  ({result, has_fflags, fflags, tag_out}),
-        .valid_out (valid_out),
-        .ready_out (ready_out),
-        `UNUSED_PIN (sel_out)
-    );
-
-    assign ready_in = per_core_ready_in[core_select];
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_dsp.sv

@@ -1,325 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-module VX_fpu_dsp import VX_fpu_pkg::*; #(
-    parameter NUM_LANES = 4, 
-    parameter TAGW      = 4,
-    parameter OUT_REG   = 0
-) (
-    input wire clk,
-    input wire reset,
-
-    input wire  valid_in,
-    output wire ready_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-    
-    input wire [`INST_FPU_BITS-1:0] op_type,
-    input wire [`INST_FMT_BITS-1:0] fmt,
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  dataa,
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  datab,
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  datac,
-    output wire [NUM_LANES-1:0][`XLEN-1:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);
-    localparam FPU_FMA     = 0;
-    localparam FPU_DIVSQRT = 1;
-    localparam FPU_CVT     = 2;
-    localparam FPU_NCP     = 3;
-    localparam NUM_FPC     = 4;
-    localparam FPC_BITS    = `LOG2UP(NUM_FPC);
-
-    localparam RSP_DATAW = (NUM_LANES * 32) + 1 + $bits(fflags_t) + TAGW;
-
-    `UNUSED_VAR (fmt)    
-
-    wire [NUM_FPC-1:0] per_core_ready_in;
-    wire [NUM_FPC-1:0][NUM_LANES-1:0][31:0] per_core_result;
-    wire [NUM_FPC-1:0][TAGW-1:0] per_core_tag_out;
-    wire [NUM_FPC-1:0] per_core_ready_out;
-    wire [NUM_FPC-1:0] per_core_valid_out;    
-    wire [NUM_FPC-1:0] per_core_has_fflags;  
-    fflags_t [NUM_FPC-1:0] per_core_fflags;
-
-    wire div_ready_in, sqrt_ready_in;
-    wire [NUM_LANES-1:0][31:0] div_result, sqrt_result;
-    wire [TAGW-1:0] div_tag_out, sqrt_tag_out;
-    wire div_ready_out, sqrt_ready_out;
-    wire div_valid_out, sqrt_valid_out;    
-    wire div_has_fflags, sqrt_has_fflags;  
-    fflags_t div_fflags, sqrt_fflags;
-
-    reg [FPC_BITS-1:0] core_select;
-    reg is_madd, is_sub, is_neg, is_div, is_itof, is_signed;
-
-    always @(*) begin
-        is_madd   = 0;
-        is_sub    = 0;        
-        is_neg    = 0;
-        is_div    = 0;
-        is_itof   = 0;
-        is_signed = 0;
-        case (op_type)
-            `INST_FPU_ADD:    begin core_select = FPU_FMA; end
-            `INST_FPU_SUB:    begin core_select = FPU_FMA; is_sub = 1; end
-            `INST_FPU_MUL:    begin core_select = FPU_FMA; is_neg = 1; end
-            `INST_FPU_MADD:   begin core_select = FPU_FMA; is_madd = 1; end
-            `INST_FPU_MSUB:   begin core_select = FPU_FMA; is_madd = 1; is_sub = 1; end
-            `INST_FPU_NMADD:  begin core_select = FPU_FMA; is_madd = 1; is_neg = 1; end
-            `INST_FPU_NMSUB:  begin core_select = FPU_FMA; is_madd = 1; is_sub = 1; is_neg = 1; end
-            `INST_FPU_DIV:    begin core_select = FPU_DIVSQRT; is_div = 1; end
-            `INST_FPU_SQRT:   begin core_select = FPU_DIVSQRT; end
-            `INST_FPU_F2I:    begin core_select = FPU_CVT; is_signed = 1; end
-            `INST_FPU_F2U:    begin core_select = FPU_CVT; end
-            `INST_FPU_I2F:    begin core_select = FPU_CVT; is_itof = 1; is_signed = 1; end
-            `INST_FPU_U2F:    begin core_select = FPU_CVT; is_itof = 1; end
-            default:          begin core_select = FPU_NCP; end
-        endcase
-    end
-
-    `RESET_RELAY (fma_reset, reset);
-    `RESET_RELAY (div_reset, reset);
-    `RESET_RELAY (sqrt_reset, reset);
-    `RESET_RELAY (cvt_reset, reset);
-    `RESET_RELAY (ncp_reset, reset);
-
-    wire [NUM_LANES-1:0][31:0] dataa_s;
-    wire [NUM_LANES-1:0][31:0] datab_s;
-    wire [NUM_LANES-1:0][31:0] datac_s;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign dataa_s[i] = dataa[i][31:0];
-        assign datab_s[i] = datab[i][31:0];
-        assign datac_s[i] = datac[i][31:0];
-    end
-
-    `UNUSED_VAR (dataa)
-    `UNUSED_VAR (datab)
-    `UNUSED_VAR (datac)
-
-    VX_fpu_fma #(
-        .NUM_LANES (NUM_LANES),
-        .TAGW      (TAGW)
-    ) fpu_fma (
-        .clk        (clk), 
-        .reset      (fma_reset), 
-        .valid_in   (valid_in && (core_select == FPU_FMA)),
-        .ready_in   (per_core_ready_in[FPU_FMA]),
-        .lane_mask  (lane_mask),
-        .tag_in     (tag_in), 
-        .frm        (frm),
-        .is_madd    (is_madd),
-        .is_sub     (is_sub),
-        .is_neg     (is_neg),
-        .dataa      (dataa_s), 
-        .datab      (datab_s), 
-        .datac      (datac_s), 
-        .has_fflags (per_core_has_fflags[FPU_FMA]),
-        .fflags     (per_core_fflags[FPU_FMA]),
-        .result     (per_core_result[FPU_FMA]),
-        .tag_out    (per_core_tag_out[FPU_FMA]),
-        .ready_out  (per_core_ready_out[FPU_FMA]),
-        .valid_out  (per_core_valid_out[FPU_FMA])
-    );
-
-    VX_fpu_div #(
-        .NUM_LANES (NUM_LANES),
-        .TAGW      (TAGW)
-    ) fpu_div (
-        .clk        (clk), 
-        .reset      (div_reset), 
-        .valid_in   (valid_in && (core_select == FPU_DIVSQRT) && is_div),
-        .ready_in   (div_ready_in),
-        .lane_mask  (lane_mask),
-        .tag_in     (tag_in),
-        .frm        (frm), 
-        .dataa      (dataa_s), 
-        .datab      (datab_s), 
-        .has_fflags (div_has_fflags),
-        .fflags     (div_fflags), 
-        .result     (div_result),
-        .tag_out    (div_tag_out),
-        .valid_out  (div_valid_out),
-        .ready_out  (div_ready_out)
-    );
-
-    VX_fpu_sqrt #(
-        .NUM_LANES (NUM_LANES),
-        .TAGW      (TAGW)
-    ) fpu_sqrt (
-        .clk        (clk), 
-        .reset      (sqrt_reset), 
-        .valid_in   (valid_in && (core_select == FPU_DIVSQRT) && ~is_div),
-        .ready_in   (sqrt_ready_in),
-        .lane_mask  (lane_mask),
-        .tag_in     (tag_in),
-        .frm        (frm), 
-        .dataa      (dataa_s), 
-        .has_fflags (sqrt_has_fflags),
-        .fflags     (sqrt_fflags),
-        .result     (sqrt_result),
-        .tag_out    (sqrt_tag_out),
-        .valid_out  (sqrt_valid_out),
-        .ready_out  (sqrt_ready_out)
-    );
-
-    wire cvt_rt_int_in = ~is_itof;
-    wire cvt_rt_int_out;
-
-    VX_fpu_cvt #(
-        .NUM_LANES (NUM_LANES),
-        .TAGW      (TAGW+1)
-    ) fpu_cvt (
-        .clk        (clk), 
-        .reset      (cvt_reset), 
-        .valid_in   (valid_in && (core_select == FPU_CVT)),
-        .ready_in   (per_core_ready_in[FPU_CVT]),
-        .lane_mask  (lane_mask),
-        .tag_in     ({cvt_rt_int_in, tag_in}), 
-        .frm        (frm),
-        .is_itof    (is_itof), 
-        .is_signed  (is_signed), 
-        .dataa      (dataa_s), 
-        .has_fflags (per_core_has_fflags[FPU_CVT]),
-        .fflags     (per_core_fflags[FPU_CVT]),
-        .result     (per_core_result[FPU_CVT]),
-        .tag_out    ({cvt_rt_int_out, per_core_tag_out[FPU_CVT]}),
-        .valid_out  (per_core_valid_out[FPU_CVT]),
-        .ready_out  (per_core_ready_out[FPU_CVT])
-    );
-
-    wire ncp_rt_int_in = (op_type == `INST_FPU_CMP)
-                      || `INST_FPU_IS_CLASS(op_type, frm) 
-                      || `INST_FPU_IS_MVXW(op_type, frm);
-    wire ncp_rt_int_out;
-
-    wire ncp_rt_sext_in = `INST_FPU_IS_MVXW(op_type, frm);
-    wire ncp_rt_sext_out;
-    
-    VX_fpu_ncomp #(
-        .NUM_LANES (NUM_LANES),
-        .TAGW      (TAGW+2)
-    ) fpu_ncomp (
-        .clk        (clk),
-        .reset      (ncp_reset), 
-        .valid_in   (valid_in && (core_select == FPU_NCP)),
-        .ready_in   (per_core_ready_in[FPU_NCP]),
-        .lane_mask  (lane_mask),
-        .tag_in     ({ncp_rt_sext_in, ncp_rt_int_in, tag_in}),
-        .op_type    (op_type),
-        .frm        (frm),
-        .dataa      (dataa_s),
-        .datab      (datab_s), 
-        .result     (per_core_result[FPU_NCP]), 
-        .has_fflags (per_core_has_fflags[FPU_NCP]),
-        .fflags     (per_core_fflags[FPU_NCP]),
-        .tag_out    ({ncp_rt_sext_out, ncp_rt_int_out, per_core_tag_out[FPU_NCP]}),
-        .valid_out  (per_core_valid_out[FPU_NCP]),
-        .ready_out  (per_core_ready_out[FPU_NCP])
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in;
-
-    VX_stream_arb #(
-        .NUM_INPUTS (2),
-        .DATAW      (RSP_DATAW), 
-        .ARBITER    ("R"),
-        .OUT_REG    (0)
-    ) div_sqrt_arb (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  ({sqrt_valid_out, div_valid_out}), 
-        .ready_in  ({sqrt_ready_out, div_ready_out}),
-        .data_in   ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out}, 
-                     {div_result, div_has_fflags, div_fflags, div_tag_out}}),
-        .data_out  ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}),
-        .valid_out (per_core_valid_out[FPU_DIVSQRT]),
-        .ready_out (per_core_ready_out[FPU_DIVSQRT]),
-        `UNUSED_PIN (sel_out)
-    );
-
-    ///////////////////////////////////////////////////////////////////////////
-
-    reg [NUM_FPC-1:0][RSP_DATAW+2-1:0] per_core_data_out;
-    
-    always @(*) begin
-        for (integer i = 0; i < NUM_FPC; ++i) begin
-            per_core_data_out[i][RSP_DATAW+1:2] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
-            per_core_data_out[i][1:0] = '0;
-        end        
-        per_core_data_out[FPU_CVT][1:0] = {1'b1, cvt_rt_int_out};
-        per_core_data_out[FPU_NCP][1:0] = {ncp_rt_sext_out, ncp_rt_int_out};
-    end
-
-    wire [NUM_LANES-1:0][31:0] result_s;
-    wire [1:0] op_rt_int_out;
-
-    VX_stream_arb #(
-        .NUM_INPUTS (NUM_FPC),
-        .DATAW      (RSP_DATAW + 2), 
-        .ARBITER    ("R"),
-        .OUT_REG    (OUT_REG)
-    ) rsp_arb (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (per_core_valid_out), 
-        .ready_in  (per_core_ready_out),
-        .data_in   (per_core_data_out),
-        .data_out  ({result_s, has_fflags, fflags, tag_out, op_rt_int_out}),
-        .valid_out (valid_out),
-        .ready_out (ready_out),
-        `UNUSED_PIN (sel_out)
-    );
-
-`ifndef FPU_RV64F
-    `UNUSED_VAR (op_rt_int_out)
-`endif
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin        
-    `ifdef FPU_RV64F
-        reg [`XLEN-1:0] result_r;
-        always @(*) begin
-            case (op_rt_int_out)
-            2'b11:   result_r = `XLEN'($signed(result_s[i]));
-            2'b01:   result_r = {32'h00000000, result_s[i]};
-            default: result_r = {32'hffffffff, result_s[i]};
-            endcase
-        end
-        assign result[i] = result_r;
-    `else
-        assign result[i] = result_s[i];
-    `endif
-    end
-
-    // can accept new request?
-    assign ready_in = per_core_ready_in[core_select];
-
-endmodule
-`endif 

hw/rtl/fpu/VX_fpu_fma.sv

@@ -1,170 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-module VX_fpu_fma import VX_fpu_pkg::*; #(
-    parameter NUM_LANES = 1, 
-    parameter TAGW = 1
-) (
-    input wire clk,
-    input wire reset, 
-
-    output wire ready_in,
-    input wire  valid_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-    
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire  is_madd,
-    input wire  is_sub,
-    input wire  is_neg,
-
-    input wire [NUM_LANES-1:0][31:0]  dataa,
-    input wire [NUM_LANES-1:0][31:0]  datab,
-    input wire [NUM_LANES-1:0][31:0]  datac,
-    output wire [NUM_LANES-1:0][31:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);
-    `UNUSED_VAR (frm)
-
-    wire stall = ~ready_out && valid_out;
-    wire enable = ~stall;
-
-    fflags_t [NUM_LANES-1:0] per_lane_fflags;
-    wire [NUM_LANES-1:0] lane_mask_out;
-
-    VX_shift_register #(
-        .DATAW  (1 + NUM_LANES + TAGW),
-        .DEPTH  (`LATENCY_FMA),
-        .RESETW (1)
-    ) shift_reg (
-        .clk(clk),
-        .reset    (reset),
-        .enable   (enable),
-        .data_in  ({valid_in, lane_mask, tag_in}),
-        .data_out ({valid_out, lane_mask_out, tag_out})
-    );
-
-    assign ready_in = enable;
-
-    reg [NUM_LANES-1:0][31:0] a, b, c;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            if (is_madd) begin
-                // MADD / MSUB / NMADD / NMSUB
-                a[i] = is_neg ? {~dataa[i][31], dataa[i][30:0]} : dataa[i];                    
-                b[i] = datab[i];
-                c[i] = (is_neg ^ is_sub) ? {~datac[i][31], datac[i][30:0]} : datac[i];
-            end else begin
-                if (is_neg) begin
-                    // MUL
-                    a[i] = dataa[i];
-                    b[i] = datab[i];
-                    c[i] = '0;
-                end else begin
-                    // ADD / SUB
-                    a[i] = 32'h3f800000; // 1.0f
-                    b[i] = dataa[i];
-                    c[i] = is_sub ? {~datab[i][31], datab[i][30:0]} : datab[i];
-                end
-            end    
-        end
-    end
-
-`ifdef QUARTUS
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        acl_fmadd fmadd (
-            .clk    (clk),
-            .areset (1'b0),
-            .en     (enable),
-            .a      (a[i]),
-            .b      (b[i]),
-            .c      (c[i]),
-            .q      (result[i])
-        );
-    end
-    
-    assign has_fflags = 0;
-    assign per_lane_fflags = 'x;
-
-`elsif VIVADO
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [2:0] tuser;
-        
-        xil_fma fma (
-            .aclk                (clk),
-            .aclken              (enable),
-            .s_axis_a_tvalid     (1'b1),
-            .s_axis_a_tdata      (a[i]),
-            .s_axis_b_tvalid     (1'b1),
-            .s_axis_b_tdata      (b[i]),
-            .s_axis_c_tvalid     (1'b1),
-            .s_axis_c_tdata      (c[i]),
-            `UNUSED_PIN (m_axis_result_tvalid),
-            .m_axis_result_tdata (result[i]),
-            .m_axis_result_tuser (tuser)
-        );
-                                    // NV, DZ, OF, UF, NX
-        assign per_lane_fflags[i] = {tuser[2], 1'b0, tuser[1], tuser[0], 1'b0};
-    end
-
-    assign has_fflags = 1;
-
-`else
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        reg [63:0] r;
-        `UNUSED_VAR (r)
-
-        fflags_t f;
-
-        always @(*) begin        
-            dpi_fmadd (enable && valid_in, int'(0), {32'hffffffff, a[i]}, {32'hffffffff, b[i]}, {32'hffffffff, c[i]}, frm, r, f);
-        end
-
-        VX_shift_register #(
-            .DATAW  (32 + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FMA)
-        ) shift_req_dpi (
-            .clk      (clk),
-            `UNUSED_PIN (reset),
-            .enable   (enable),
-            .data_in  ({r[31:0], f}),
-            .data_out ({result[i], per_lane_fflags[i]})
-        );
-    end
-
-    assign has_fflags = 1;
-
-`endif
-
-`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES);
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_fpnew.sv

@@ -1,286 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_FPNEW
-
-module VX_fpu_fpnew 
-    import VX_fpu_pkg::*; 
-    import fpnew_pkg::*; 
-    import cf_math_pkg::*; 
-    import defs_div_sqrt_mvp::*;
-#(      
-    parameter NUM_LANES = 1,
-    parameter TAGW      = 1,
-    parameter OUT_REG   = 0
-) (
-    input wire clk,
-    input wire reset,
-
-    input wire  valid_in,
-    output wire ready_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-    
-    input wire [`INST_FPU_BITS-1:0] op_type,
-    input wire [`INST_FMT_BITS-1:0] fmt,
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  dataa,
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  datab,
-    input wire [NUM_LANES-1:0][`XLEN-1:0]  datac,
-    output wire [NUM_LANES-1:0][`XLEN-1:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);  
-    localparam LATENCY_FDIVSQRT = `MAX(`LATENCY_FDIV, `LATENCY_FSQRT);
-    localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAGW;
-
-`ifdef XLEN_64
-    // use scalar configuration for mixed formats
-    localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
-        Width:         unsigned'(`XLEN),
-        EnableVectors: 1'b0,
-        EnableNanBox:  1'b1,
-    `ifdef FLEN_64
-        FpFmtMask:     5'b11000,
-    `else
-        FpFmtMask:     5'b11000, // TODO: added FP64 to fix CVT bug in FpNew
-    `endif
-        IntFmtMask:    4'b0011
-    };
-`else
-    localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
-        Width:         unsigned'(`XLEN * NUM_LANES),
-        EnableVectors: 1'b1,
-        EnableNanBox:  1'b0,
-        FpFmtMask:     5'b10000,
-        IntFmtMask:    4'b0010
-    };
-`endif
-
-    localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
-      PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL
-                 '{default: unsigned'(LATENCY_FDIVSQRT)}, // DIVSQRT
-                 '{default: `LATENCY_FNCP}, // NONCOMP
-                 '{default: `LATENCY_FCVT}}, // CONV
-      UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
-                  '{default: fpnew_pkg::MERGED}, // DIVSQRT
-                  '{default: fpnew_pkg::PARALLEL}, // NONCOMP
-                  '{default: fpnew_pkg::MERGED}}, // CONV
-      PipeConfig: fpnew_pkg::DISTRIBUTED
-    };
-    
-    wire fpu_ready_in, fpu_valid_in;    
-    wire fpu_ready_out, fpu_valid_out;
-
-    reg [TAGW-1:0] fpu_tag_in, fpu_tag_out;
-    
-    reg [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands;
-
-    wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result;
-    fpnew_pkg::status_t fpu_status;
-
-    fpnew_pkg::operation_e fpu_op;
-    reg [`INST_FRM_BITS-1:0] fpu_rnd;
-    reg fpu_op_mod;
-    reg fpu_has_fflags, fpu_has_fflags_out;
-    fpnew_pkg::fp_format_e fpu_src_fmt, fpu_dst_fmt;
-    fpnew_pkg::int_format_e fpu_int_fmt;
-
-    `UNUSED_VAR (fmt)
-
-    always @(*) begin
-        fpu_op          = 'x;
-        fpu_rnd         = frm;  
-        fpu_op_mod      = 0;        
-        fpu_has_fflags  = 1;
-        fpu_operands[0] = dataa;
-        fpu_operands[1] = datab;
-        fpu_operands[2] = datac;    
-        fpu_dst_fmt     = fpnew_pkg::FP32;
-        fpu_int_fmt     = fpnew_pkg::INT32;
-
-    `ifdef FLEN_64
-        if (fmt[0]) begin
-            fpu_dst_fmt = fpnew_pkg::FP64;
-        end
-    `endif
-
-    `ifdef XLEN_64
-        if (fmt[1]) begin
-            fpu_int_fmt = fpnew_pkg::INT64;
-        end
-    `endif
-
-        fpu_src_fmt = fpu_dst_fmt;
-        
-        case (op_type)
-            `INST_FPU_ADD: begin
-                fpu_op = fpnew_pkg::ADD;
-                fpu_operands[1] = dataa;
-                fpu_operands[2] = datab;
-            end
-            `INST_FPU_SUB: begin 
-                fpu_op = fpnew_pkg::ADD; 
-                fpu_operands[1] = dataa;
-                fpu_operands[2] = datab;
-                fpu_op_mod = 1; 
-            end
-            `INST_FPU_MUL:   begin fpu_op = fpnew_pkg::MUL; end
-            `INST_FPU_DIV:   begin fpu_op = fpnew_pkg::DIV; end
-            `INST_FPU_SQRT:  begin fpu_op = fpnew_pkg::SQRT; end
-            `INST_FPU_MADD:  begin fpu_op = fpnew_pkg::FMADD; end
-            `INST_FPU_MSUB:  begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end            
-            `INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
-            `INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
-        `ifdef FLEN_64
-            `INST_FPU_F2F: begin fpu_op = fpnew_pkg::F2F; fpu_src_fmt = fmt[0] ? fpnew_pkg::FP32 : fpnew_pkg::FP64; end
-        `endif
-            `INST_FPU_F2I,
-            `INST_FPU_F2U: begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = op_type[0]; end
-            `INST_FPU_I2F,
-            `INST_FPU_U2F: begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = op_type[0]; end
-            `INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
-            `INST_FPU_MISC:begin
-                case (frm)
-                    0,1,2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = {1'b0, frm[1:0]}; fpu_has_fflags = 0; end // FSGNJ
-                    3:     begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end // CLASS                     
-                    4,5:   begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_op_mod = ~frm[0]; fpu_has_fflags = 0; end // FMV.X.W, FMV.W.X
-                    6,7:   begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = {2'b00, frm[0]}; end // MIN, MAX
-                endcase    
-            end
-            default:;
-        endcase
-
-    `ifdef FPU_RV64F
-        // apply nan-boxing to floating-point operands
-        for (integer i = 0; i < NUM_LANES; ++i) begin                    
-            if (op_type != `INST_FPU_I2F && op_type != `INST_FPU_U2F) begin
-                fpu_operands[0][i] |= 64'hffffffff00000000;
-            end
-            fpu_operands[1][i] |= 64'hffffffff00000000;
-            fpu_operands[2][i] |= 64'hffffffff00000000;        
-        end
-    `endif
-    end
-
-`ifdef XLEN_64
-    `UNUSED_VAR (lane_mask)
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire [(TAGW+1)-1:0] fpu_tag;        
-        wire fpu_valid_out_uq;
-        wire fpu_ready_in_uq;
-        fpnew_pkg::status_t fpu_status_uq;
-        `UNUSED_VAR (fpu_tag)
-        `UNUSED_VAR (fpu_valid_out_uq)
-        `UNUSED_VAR (fpu_ready_in_uq)
-        `UNUSED_VAR (fpu_status_uq)
-
-        fpnew_top #( 
-            .Features       (FPU_FEATURES),
-            .Implementation (FPU_IMPLEMENTATION),
-            .TagType        (logic[(TAGW+1)-1:0])
-        ) fpnew_core (
-            .clk_i          (clk),
-            .rst_ni         (~reset),
-            .operands_i     ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}),
-            .rnd_mode_i     (fpnew_pkg::roundmode_e'(fpu_rnd)),
-            .op_i           (fpu_op),
-            .op_mod_i       (fpu_op_mod),
-            .src_fmt_i      (fpu_src_fmt),
-            .dst_fmt_i      (fpu_dst_fmt),
-            .int_fmt_i      (fpu_int_fmt),
-            `UNUSED_PIN (vectorial_op_i),
-            `UNUSED_PIN (simd_mask_i),
-            .tag_i          ({fpu_tag_in, fpu_has_fflags}),            
-            .in_valid_i     (fpu_valid_in),
-            .in_ready_o     (fpu_ready_in_uq),
-            .flush_i        (reset),
-            .result_o       (fpu_result[i]),
-            .status_o       (fpu_status_uq),
-            .tag_o          (fpu_tag),
-            .out_valid_o    (fpu_valid_out_uq),
-            .out_ready_i    (fpu_ready_out),
-            `UNUSED_PIN (busy_o)
-        );
-        
-        if (i == 0) begin
-            assign {fpu_tag_out, fpu_has_fflags_out} = fpu_tag;            
-            assign fpu_valid_out = fpu_valid_out_uq;
-            assign fpu_ready_in = fpu_ready_in_uq;
-            assign fpu_status = fpu_status_uq;
-        end
-    end
-`else
-    fpnew_top #( 
-        .Features       (FPU_FEATURES),
-        .Implementation (FPU_IMPLEMENTATION),
-        .TagType        (logic[(TAGW+1)-1:0]),
-        .TrueSIMDClass  (1),
-        .EnableSIMDMask (1)
-    ) fpnew_core (
-        .clk_i          (clk),
-        .rst_ni         (~reset),
-        .operands_i     (fpu_operands),
-        .rnd_mode_i     (fpnew_pkg::roundmode_e'(fpu_rnd)),
-        .op_i           (fpu_op),
-        .op_mod_i       (fpu_op_mod),
-        .src_fmt_i      (fpu_src_fmt),
-        .dst_fmt_i      (fpu_dst_fmt),
-        .int_fmt_i      (fpu_int_fmt),
-        .vectorial_op_i (1'b1),
-        .simd_mask_i    (lane_mask),
-        .tag_i          ({fpu_tag_in, fpu_has_fflags}),        
-        .in_valid_i     (fpu_valid_in),
-        .in_ready_o     (fpu_ready_in),
-        .flush_i        (reset),
-        .result_o       (fpu_result),
-        .status_o       (fpu_status),
-        .tag_o          ({fpu_tag_out, fpu_has_fflags_out}),
-        .out_valid_o    (fpu_valid_out),
-        .out_ready_i    (fpu_ready_out),
-        `UNUSED_PIN (busy_o)
-    );
-`endif
-
-    assign fpu_valid_in = valid_in;
-    assign ready_in = fpu_ready_in;
-    assign fpu_tag_in = tag_in;
-
-    VX_elastic_buffer #(
-        .DATAW   (RSP_DATAW),
-        .SIZE    (`OUT_REG_TO_EB_SIZE(OUT_REG)),
-        .OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
-    ) rsp_buf (
-        .clk       (clk),
-        .reset     (reset),
-        .valid_in  (fpu_valid_out),
-        .ready_in  (fpu_ready_out),
-        .data_in   ({fpu_result, fpu_has_fflags_out, fpu_status, fpu_tag_out}),
-        .data_out  ({result, has_fflags, fflags, tag_out}),
-        .valid_out (valid_out),
-        .ready_out (ready_out)
-    );
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_ncomp.sv

@@ -1,292 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-/// Modified port of noncomp module from fpnew Libray 
-/// reference: https://github.com/pulp-platform/fpnew
-
-module VX_fpu_ncomp import VX_fpu_pkg::*; #(
-    parameter NUM_LANES = 1,
-    parameter TAGW = 1
-) (
-    input wire clk,
-    input wire reset,
-
-    output wire ready_in,
-    input wire  valid_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-
-    input wire [`INST_FPU_BITS-1:0] op_type,
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire [NUM_LANES-1:0][31:0]  dataa,
-    input wire [NUM_LANES-1:0][31:0]  datab,
-    output wire [NUM_LANES-1:0][31:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);  
-    localparam  EXP_BITS = 8;
-    localparam  MAN_BITS = 23;
-        
-    localparam  NEG_INF     = 32'h00000001,
-                NEG_NORM    = 32'h00000002,
-                NEG_SUBNORM = 32'h00000004,
-                NEG_ZERO    = 32'h00000008,
-                POS_ZERO    = 32'h00000010,
-                POS_SUBNORM = 32'h00000020,
-                POS_NORM    = 32'h00000040,
-                POS_INF     = 32'h00000080,
-                //SIG_NAN   = 32'h00000100,
-                QUT_NAN     = 32'h00000200;
-
-    wire [NUM_LANES-1:0]        a_sign, b_sign;
-    wire [NUM_LANES-1:0][7:0]   a_exponent, b_exponent;
-    wire [NUM_LANES-1:0][22:0]  a_mantissa, b_mantissa;
-    fclass_t [NUM_LANES-1:0]    a_fclass, b_fclass;
-    wire [NUM_LANES-1:0]        a_smaller, ab_equal;
-
-    // Setup
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        assign     a_sign[i] = dataa[i][31]; 
-        assign a_exponent[i] = dataa[i][30:23];
-        assign a_mantissa[i] = dataa[i][22:0];
-
-        assign     b_sign[i] = datab[i][31]; 
-        assign b_exponent[i] = datab[i][30:23];
-        assign b_mantissa[i] = datab[i][22:0];
-
-        VX_fpu_class #( 
-            .EXP_BITS (EXP_BITS),
-            .MAN_BITS (MAN_BITS)
-        ) fp_class_a (
-            .exp_i  (a_exponent[i]),
-            .man_i  (a_mantissa[i]),
-            .clss_o (a_fclass[i])
-        );
-
-        VX_fpu_class #( 
-            .EXP_BITS (EXP_BITS),
-            .MAN_BITS (MAN_BITS)
-        ) fp_class_b (
-            .exp_i  (b_exponent[i]),
-            .man_i  (b_mantissa[i]),
-            .clss_o (b_fclass[i])
-        );
-
-        assign a_smaller[i] = (dataa[i] < datab[i]) ^ (a_sign[i] || b_sign[i]);
-        assign ab_equal[i]  = (dataa[i] == datab[i]) 
-                           || (a_fclass[i].is_zero && b_fclass[i].is_zero); // +0 == -0
-    end  
-
-    // Pipeline stage0
-
-    wire                        valid_in_s0;
-    wire [NUM_LANES-1:0]        lane_mask_s0;
-    wire [TAGW-1:0]             tag_in_s0;
-    wire [3:0]                  op_mod_s0;
-    wire [NUM_LANES-1:0][31:0]  dataa_s0, datab_s0;
-    wire [NUM_LANES-1:0]        a_sign_s0, b_sign_s0;
-    wire [NUM_LANES-1:0][7:0]   a_exponent_s0;
-    wire [NUM_LANES-1:0][22:0]  a_mantissa_s0;
-    fclass_t [NUM_LANES-1:0]    a_fclass_s0, b_fclass_s0;
-    wire [NUM_LANES-1:0]        a_smaller_s0, ab_equal_s0;
-
-    wire stall;
-
-    wire [3:0] op_mod = {(op_type == `INST_FPU_CMP), frm};
-
-    VX_pipe_register #(
-        .DATAW  (1 + NUM_LANES + TAGW + 4 + NUM_LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fclass_t) + 1 + 1)),
-        .RESETW (1)
-    ) pipe_reg0 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (!stall),
-        .data_in  ({valid_in, lane_mask, tag_in, op_mod, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_fclass, b_fclass, a_smaller, ab_equal}),
-        .data_out ({valid_in_s0, lane_mask_s0, tag_in_s0, op_mod_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_fclass_s0, b_fclass_s0, a_smaller_s0, ab_equal_s0})
-    ); 
-
-    // FCLASS
-    reg [NUM_LANES-1:0][31:0] fclass_mask_s0;  // generate a 10-bit mask for integer reg
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin 
-            if (a_fclass_s0[i].is_normal) begin
-                fclass_mask_s0[i] = a_sign_s0[i] ? NEG_NORM : POS_NORM;
-            end 
-            else if (a_fclass_s0[i].is_inf) begin
-                fclass_mask_s0[i] = a_sign_s0[i] ? NEG_INF : POS_INF;
-            end 
-            else if (a_fclass_s0[i].is_zero) begin
-                fclass_mask_s0[i] = a_sign_s0[i] ? NEG_ZERO : POS_ZERO;
-            end 
-            else if (a_fclass_s0[i].is_subnormal) begin
-                fclass_mask_s0[i] = a_sign_s0[i] ? NEG_SUBNORM : POS_SUBNORM;
-            end 
-            else if (a_fclass_s0[i].is_nan) begin
-                fclass_mask_s0[i] = {22'h0, a_fclass_s0[i].is_quiet, a_fclass_s0[i].is_signaling, 8'h0};
-            end 
-            else begin                     
-                fclass_mask_s0[i] = QUT_NAN;
-            end
-        end
-    end
-
-    // Min/Max    
-    reg [NUM_LANES-1:0][31:0] fminmax_res_s0;
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            if (a_fclass_s0[i].is_nan && b_fclass_s0[i].is_nan)
-                fminmax_res_s0[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN
-            else if (a_fclass_s0[i].is_nan) 
-                fminmax_res_s0[i] = datab_s0[i];
-            else if (b_fclass_s0[i].is_nan) 
-                fminmax_res_s0[i] = dataa_s0[i];
-            else begin 
-                // FMIN, FMAX
-                fminmax_res_s0[i] = (op_mod_s0[0] ^ a_smaller_s0[i]) ? dataa_s0[i] : datab_s0[i];
-            end
-        end
-    end
-
-    // Sign injection    
-    reg [NUM_LANES-1:0][31:0] fsgnj_res_s0;    // result of sign injection
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            case (op_mod_s0[1:0])
-                0: fsgnj_res_s0[i] = { b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]};
-                1: fsgnj_res_s0[i] = {~b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]};
-          default: fsgnj_res_s0[i] = { a_sign_s0[i] ^ b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]};
-            endcase
-        end
-    end
-
-    // Comparison    
-    reg [NUM_LANES-1:0] fcmp_res_s0;        // result of comparison
-    reg [NUM_LANES-1:0] fcmp_fflags_NV_s0;  // comparison fflags
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            case (op_mod_s0[1:0])
-                0: begin // LE                    
-                    if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
-                        fcmp_res_s0[i]       = 0;
-                        fcmp_fflags_NV_s0[i] = 1;
-                    end else begin
-                        fcmp_res_s0[i]       = (a_smaller_s0[i] | ab_equal_s0[i]);
-                        fcmp_fflags_NV_s0[i] = 0;
-                    end
-                end
-                1: begin // LT
-                    if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
-                        fcmp_res_s0[i]       = 0;
-                        fcmp_fflags_NV_s0[i] = 1;
-                    end else begin
-                        fcmp_res_s0[i]       = (a_smaller_s0[i] & ~ab_equal_s0[i]);
-                        fcmp_fflags_NV_s0[i] = 0;
-                    end                    
-                end
-                2: begin // EQ
-                    if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
-                        fcmp_res_s0[i]       = 0;
-                        fcmp_fflags_NV_s0[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling; 
-                    end else begin
-                        fcmp_res_s0[i]       = ab_equal_s0[i];
-                        fcmp_fflags_NV_s0[i] = 0;
-                    end
-                end
-                default: begin
-                    fcmp_res_s0[i]       = 'x;
-                    fcmp_fflags_NV_s0[i] = 'x;                        
-                end
-            endcase
-        end
-    end
-
-    // outputs
-
-    reg [NUM_LANES-1:0][31:0] result_s0;
-    reg [NUM_LANES-1:0] fflags_NV_s0;
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        always @(*) begin
-            case (op_mod_s0[2:0])
-                0,1,2: begin
-                    // SGNJ, CMP
-                    result_s0[i] = op_mod_s0[3] ? 32'(fcmp_res_s0[i]) : fsgnj_res_s0[i];
-                    fflags_NV_s0[i] = fcmp_fflags_NV_s0[i];
-                end
-                3: begin
-                    // CLASS
-                    result_s0[i] = fclass_mask_s0[i];
-                    fflags_NV_s0[i] = 'x;
-                end
-                4,5: begin
-                    // FMV
-                    result_s0[i] = dataa_s0[i];
-                    fflags_NV_s0[i] = 'x;
-                end                
-                6,7: begin
-                    // MIN/MAX
-                    result_s0[i] = fminmax_res_s0[i];
-                    fflags_NV_s0[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
-                end
-            endcase
-        end
-    end
-
-    // only MIN/MAX and CMP return status flags
-    wire has_fflags_s0 = (op_mod_s0[2:0] >= 6) || op_mod_s0[3];
-
-    assign stall = ~ready_out && valid_out;
-
-    wire fflags_NV;
-    reg fflags_merged;
-
-    always @(*) begin
-        fflags_merged = 0;
-        for (integer i = 0; i < NUM_LANES; ++i) begin
-            if (lane_mask_s0[i]) begin
-                fflags_merged |= fflags_NV_s0[i];
-            end
-        end
-    end
-
-    VX_pipe_register #(
-        .DATAW  (1 + TAGW + (NUM_LANES * 32) + 1 + 1),
-        .RESETW (1)
-    ) pipe_reg1 (
-        .clk      (clk),
-        .reset    (reset),
-        .enable   (!stall),
-        .data_in  ({valid_in_s0, tag_in_s0, result_s0, has_fflags_s0, fflags_merged}),
-        .data_out ({valid_out, tag_out, result, has_fflags, fflags_NV})
-    );
-
-    assign ready_in = ~stall;
-
-                  // NV, DZ, OF, UF, NX
-    assign fflags = {fflags_NV, 1'b0, 1'b0, 1'b0, 1'b0};
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_pkg.sv

@@ -1,41 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`ifndef VX_FPU_PKG_VH
-`define VX_FPU_PKG_VH
-
-`include "VX_define.vh"
-
-package VX_fpu_pkg;
-
-typedef struct packed {
-    logic is_normal;
-    logic is_zero;
-    logic is_subnormal;
-    logic is_inf;
-    logic is_nan;
-    logic is_quiet;
-    logic is_signaling;    
-} fclass_t;
-
-typedef struct packed {
-    logic NV; // 4-Invalid
-    logic DZ; // 3-Divide by zero
-    logic OF; // 2-Overflow
-    logic UF; // 1-Underflow
-    logic NX; // 0-Inexact
-} fflags_t;
-
-endpackage
-
-`endif // VX_FPU_PKG_VH

hw/rtl/fpu/VX_fpu_rounding.sv

@@ -1,78 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-/// Modified port of rouding module from fpnew Libray
-/// reference: https://github.com/pulp-platform/fpnew
-
-module VX_fpu_rounding #(
-    parameter DAT_WIDTH = 2 // Width of the abolute value, without sign bit
-) (
-    // inputs
-    input wire [DAT_WIDTH-1:0]  abs_value_i, // absolute value without sign
-    input wire                  sign_i,
-    // rounding information
-    input wire [1:0]            round_sticky_bits_i, // round and sticky bits {RS}
-    input wire [2:0]            rnd_mode_i,
-    input wire                  effective_subtraction_i, // sign of inputs affects rounding of zeroes
-    // outputs
-    output wire [DAT_WIDTH-1:0] abs_rounded_o, // absolute value without sign
-    output wire                 sign_o,
-    output wire                 exact_zero_o             // output is an exact zero
-);
-
-    reg round_up; // Rounding decision
-
-    // Take the rounding decision according to RISC-V spec
-    // RoundMode | Mnemonic | Meaning
-    // :--------:|:--------:|:-------
-    //    000    |   RNE    | Round to Nearest, ties to Even
-    //    001    |   RTZ    | Round towards Zero
-    //    010    |   RDN    | Round Down (towards -\infty)
-    //    011    |   RUP    | Round Up (towards \infty)
-    //    100    |   RMM    | Round to Nearest, ties to Max Magnitude
-    //  others   |          | *invalid*
-
-    always @(*) begin
-        case (rnd_mode_i)
-            `INST_FRM_RNE: // Decide accoring to round/sticky bits
-                case (round_sticky_bits_i)
-                      2'b00, 
-                      2'b01: round_up = 1'b0;            // < ulp/2 away, round down
-                      2'b10: round_up = abs_value_i[0];  // = ulp/2 away, round towards even result
-                      2'b11: round_up = 1'b1;            // > ulp/2 away, round up
-                endcase
-            `INST_FRM_RTZ: round_up = 1'b0; // always round down
-            `INST_FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i;  // to 0 if +, away if -
-            `INST_FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if +
-            `INST_FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up
-            default:  round_up = 1'bx; // propagate x
-        endcase
-    end
-
-    // Perform the rounding, exponent change and overflow to inf happens automagically
-    assign abs_rounded_o = abs_value_i + DAT_WIDTH'(round_up);
-
-    // True zero result is a zero result without dirty round/sticky bits
-    assign exact_zero_o = (abs_value_i == 0) && (round_sticky_bits_i == 0);
-
-    // In case of effective subtraction (thus signs of addition operands must have differed) and a
-    // true zero result, the result sign is '-' in case of RDN and '+' for other modes.
-    assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == `INST_FRM_RDN)
-                                                              : sign_i;
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_sqrt.sv

@@ -1,134 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-`ifdef FPU_DSP
-
-module VX_fpu_sqrt import VX_fpu_pkg::*; #( 
-    parameter NUM_LANES = 1,
-    parameter TAGW = 1    
-) (
-    input wire clk,
-    input wire reset, 
-
-    output wire ready_in,
-    input wire  valid_in,
-
-    input wire [NUM_LANES-1:0] lane_mask,
-
-    input wire [TAGW-1:0] tag_in,
-    
-    input wire [`INST_FRM_BITS-1:0] frm,
-
-    input wire [NUM_LANES-1:0][31:0]  dataa,
-    output wire [NUM_LANES-1:0][31:0] result, 
-
-    output wire has_fflags,
-    output wire [`FP_FLAGS_BITS-1:0] fflags,
-
-    output wire [TAGW-1:0] tag_out,
-
-    input wire  ready_out,
-    output wire valid_out
-);
-
-    `UNUSED_VAR (frm)
-    
-    wire stall = ~ready_out && valid_out;
-    wire enable = ~stall;
-
-    fflags_t [NUM_LANES-1:0] per_lane_fflags;
-    wire [NUM_LANES-1:0] lane_mask_out;
-
-    VX_shift_register #(
-        .DATAW  (1 + NUM_LANES + TAGW),
-        .DEPTH  (`LATENCY_FSQRT),
-        .RESETW (1)
-    ) shift_reg (
-        .clk(clk),
-        .reset    (reset),
-        .enable   (enable),
-        .data_in  ({valid_in, lane_mask, tag_in}),
-        .data_out ({valid_out, lane_mask_out, tag_out})
-    );
-
-    assign ready_in = enable;    
-
-`ifdef QUARTUS
-    
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        acl_fsqrt fsqrt (
-            .clk    (clk),
-            .areset (1'b0),
-            .en     (enable),
-            .a      (dataa[i]),
-            .q      (result[i])
-        );
-    end
-
-    assign has_fflags = 0;
-    assign per_lane_fflags = 'x;
-
-`elsif VIVADO
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        wire tuser;       
-
-        xil_fsqrt fsqrt (
-            .aclk                (clk),
-            .aclken              (enable),
-            .s_axis_a_tvalid     (1'b1),
-            .s_axis_a_tdata      (dataa[i][31:0]),
-            `UNUSED_PIN (m_axis_result_tvalid),
-            .m_axis_result_tdata (result[i][31:0]),
-            .m_axis_result_tuser (tuser)
-        );
-                                    // NV, DZ, OF, UF, NX
-        assign per_lane_fflags[i] = {tuser, 1'b0, 1'b0, 1'b0, 1'b0};
-    end
-
-    assign has_fflags = 1;
-
-`else
-
-    for (genvar i = 0; i < NUM_LANES; ++i) begin
-        reg [63:0] r;
-        `UNUSED_VAR (r)
-
-        fflags_t f;
-
-        always @(*) begin        
-            dpi_fsqrt (enable && valid_in, int'(0), {32'hffffffff, dataa[i]}, frm, r, f);
-        end
-        
-        VX_shift_register #(
-            .DATAW  (32 + $bits(fflags_t)),
-            .DEPTH  (`LATENCY_FSQRT)
-        ) shift_req_dpi (
-            .clk      (clk),
-            `UNUSED_PIN (reset),
-            .enable   (enable),
-            .data_in  ({r[31:0], f}),
-            .data_out ({result[i], per_lane_fflags[i]})
-        );
-    end
-
-    assign has_fflags = 1;
-
-`endif
-
-`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES);
-
-endmodule
-`endif

hw/rtl/fpu/VX_fpu_to_csr_if.sv

@@ -1,43 +0,0 @@
-// Copyright © 2019-2023
-// 
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-// 
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-`include "VX_fpu_define.vh"
-
-interface VX_fpu_to_csr_if import VX_fpu_pkg::*; ();
-
-    wire                    write_enable;
-    wire [`NW_WIDTH-1:0]    write_wid;
-    fflags_t                write_fflags;
-
-    wire [`NW_WIDTH-1:0]    read_wid;
-    wire [`INST_FRM_BITS-1:0] read_frm;
-
-    modport master (
-        output write_enable,
-        output write_wid,
-        output write_fflags,
-
-        output read_wid,
-        input  read_frm
-    );
-
-    modport slave (
-        input  write_enable,
-        input  write_wid,
-        input  write_fflags,
-        
-        input  read_wid,
-        output read_frm
-    );
-
-endinterface